High-performance Thin-film Transistors Research Articles

Fabrication of high-performance tin halide perovskite thin-film transistors via chemical solution-based composition engineering

Fabrication of high-performance tin halide perovskite thin-film transistors via chemical solution-based composition engineering

High mobility crystallized stacked-channel thin-film transistors induced by low-temperature thermal annealing

A high mobility crystallized stacked-channel thin-film transistor (TFT) was fabricated and characterized. The stacked IGO/IGZO channel film consisting of an In-rich IGO layer and a conventional IGZO layer was fabricated by atomic layer deposition technology, where the upper layer of amorphous IGZO is induced into nanocrystals by the lower layer of preferentially oriented polycrystalline IGO during thermal annealing at a low temperature of 300 °C. The preferential growth of nanocrystalline IGZO with matched crystal structure in the channel favors the transport of electrons. In addition, the accumulation of a large number of electrons at the heterojunction due to energy band bending provides a strong guarantee for high mobility. The crystallized stacked IGO/IGZO TFT exhibits a superior field effect mobility of 95.7 cm2 V−1 s−1, which is 55.9% higher than that of single-layer IGO TFT. At the same time, the stability of the device was also dramatically improved. The proposed strategy is a simple and promising approach to prepare high performance TFTs for future display and semiconductor applications.

Influence of radio-frequency magnetron sputtering power on electrical characteristics and positive bias stress stability of indium tin zinc oxide thin-film transistors

Abstract As the pursuit of high-quality display panels intensifies, the importance of high-performance thin-film transistors (TFTs) becomes increasingly prominent. Indium tin zinc oxide (ITZO) TFTs, as one of the promising directions for high-performance metal oxide TFTs, impose high demands on their performance and reliability. In this study, the performance and stability of ITZO TFTs fabricated under different radio-frequency magnetron sputtering power conditions were systematically tested and investigated. After sputtering power optimization, the field effect mobility of ITZO TFTs reaches 29.68 cm2V–1.s, with a steep sub-threshold swing of 0.17 V/decade, near-zero threshold voltage, and good stability. Using atomic force microscopy and x-ray photoelectron spectroscopy characterization techniques, the thin films were analyzed to elucidate the relationship between sputtering power variations and oxygen vacancies.

High-performance trench-structured thin film transistor with a micropatterned double-layer oxide semiconductor of varying thickness

High-performance trench-structured thin film transistor with a micropatterned double-layer oxide semiconductor of varying thickness

All Solution-Processed High-Performance MoS2 Thin Film Transistors with the High-k Perovskite Oxide Dielectric

Solution-processable van der Waals (vdW) materials with atomic layered crystal structures, are increasingly recognized as promising components for emerging electronic device applications. These materials offer exceptional quality and stability, coupled with the advantage of large-scale and low-temperature processability. Among these, van der Waals-assembled thin films made from transition metal dichalcogenides in solution have recently emerged as highly potential candidates for fabricating high-performance thin-film transistors (TFTs). Despite recent progress, fully solution-processed vdW electronics remain elusive, primarily due to the absence of suitable dielectric materials and scalable fabrication methodologies. In this report, we introduce the all solution-processed MoS2 TFTs, incorporating perovskite oxides as high-k gate dielectrics. The fabrication process involves preparing colloidal inks for each constituent layer through chemical or electrochemical exfoliation methods, followed by sequential assembly processes forming the semiconductor/dielectric heterostructure. All fabrication steps are performed at temperatures below 250 ℃. The resulting MoS2 TFTs, utilizing Dion-Jacobson-phase perovskite as the dielectric layer, demonstrate superior device characteristics. Notably, they exhibit an ON/OFF ratio exceeding 106, including high mobility (>10 cm2 V-1s-1). Additionally, the integration of high-k dielectric materials enables the transistors to operate at low leakage current (~10-11 A) and very low voltages, around approximately 5 V, significantly reducing power consumption. These TFTs are also compatible with flexible substrates, which further demonstrates their robustness and adaptability in a variety of electronic applications. The successful demonstration of low-temperature fabrication techniques for high-performance MoS2 TFTs not only marks a significant advancement in the field of solution-processable electronic devices but also paves the way for cost-effective, scalable electronics that are capable of hetero-integration.

High Quality Carbon Nanotube Thin Films for Transistor Application

Semiconducting carbon nanotubes (s-CNTs) are promising channel materials for both high-performance ultra-scaled field-effect transistors (FETs) and thin film transistors (TFTs) due to their excellent electronic properties. Many research groups have demonstrated the application of s-CNTs in either logical computing circuits or large area electronics. However, before the CNT-based electronics technology takes real impact, many challenges should be overcome, such as achieving high purity of s-CNTs, reliable methods for their deposition and alignment, development of scalable and cost-effective production techniques, and corresponding quality characterization metrology. In this presentation, we will report our progress on the s-CNT materials and their application for FETs and TFTs.Conjugated polymer wrapping method was used to extract s-CNTs from the raw CNT materials. We have developed a closed-loop recycling strategy, in which raw materials (CNTs and polymers) and solvents were all recycled and reused for multiple separation cycles, thus high-purity (99.9999%) and high structural quality s-CNTs were mass produced. The cost was reduced to ~ 1% in comparison with commercially available products, and total yield was increased to 36% in comparison with 2%–5% of usual separation methods.Highly unform and density-controllable thin films of random-oriented CNTs (R-CNTs) were fabricated by a dip-coating method on 4-inch/8-inch Si wafers and 2.5th generation (G2.5) backplane glasses (370 mm × 470 mm). Ultra-clean wafer-scale aligned s-CNTs (A-CNTs) were fabricated by a modified dimension-limited self-alignment (m-DLSA) method. To quantify the overall quality of both R-CNT and A-CNT films, we proposed a four-parameter metrology which includes the local tube density (DL), global density uniformity (Cv), local degree of order (OL), and the relative tube proportion in a certain orientation (Pθ) at a location. The four-parameter metrology is not only powerful for overall quality evaluation of CNT films, but also able to predict the performance fluctuation of fabricated devices.TFTs fabricated using the R-CNTs show mobility of 45-55 cm2/Vs with a high-performance uniformity (Cv ≈ 11%–13%) on a 4-inch wafer. A micro-LED display with 32×32 pixels were driven successfully by 2T1C AMTFT back plane based on R-CNT TFTs. Top-gated FETs based on A-CNTs exhibit excellent electronic performance with an on-state current (Ion) of 2.2 mA/μm, peak transconductance (gm) of 1.1 mS/μm, low contact resistance (Rc) of 191 Ω•μm and negligible hysteresis, among the best reported performance of CNT FETs. We believe our progress in the s-CNT materials will greatly push the CNT-based electronics technology into practical applications.

(Invited) Development of High-Performance Sn Based Halide Perovskite Transistors

Developing high-mobility p-type semiconductors that can be grown using cost-effective scalable methods at low temperatures, has remained challenging in the electronics community for the integration of complementary electronics with the well-developed n-type metal oxide counterparts. Tin (Sn2+) halide perovskites emerge as promising p-type candidates but suffer from low crystallisation controllability and high film defect density, which result in uncompetitive device performance. In this talk, I would like to introduce a general overview and recent progress of our group of p-type Sn-based metal halide perovskites for the application of field-effect transistors (FETs). In the first part of the talk, I will mainly address inorganic perovskite thin-film transistors with exceptional performance using high-crystallinity and uniform cesium-tin-triiodide-based semiconducting layers with moderate hole concentrations and superior Hall mobilities, which are enabled by the judicious engineering of film composition and crystallization. The optimized devices exhibit high field-effect hole mobilities of over 50 cm2 V− 1 s− 1, large current modulation greater than 108, and high operational stability and reproducibility [1,2]. In the second part of the talk, I will introduce A-site cation engineering method to achieve high-performance pure-Sn perovskite thin-film transistors (TFTs). We explore triple A-cations of caesium-formamidinium-phenethylammonium to create high-quality cascaded Sn perovskite channel films, especially with low-defect phase-pure perovskite/dielectric interface. As such, the optimized TFTs show record hole mobilities of over 70 cm2 V− 1 s− 1 and on/off current ratios of over 108, comparable to the commercial low-temperature polysilicon technique level [3]. The p-channel perovskite TFTs also show high processability and compatibility with the n-type metal oxides, enabling the integration of high-gain complementary inverters and rail-to-rail logic gates. References Liu, Y.-Y. Noh et al, Nature Electronics 5, 78-83 (2022).Liu Y.-Y. Noh et al, Nature Electronics 6, 559-571 (2023).H. Zhu, Y.-Y. Noh et al, Nature Electronics 6, 650-657 (2023).

(Invited) Advancements in High-Performance Metal-Oxide TFTs Via Atomic-Layer Deposition: A Path Towards Next-Gen Display and Memory Technology

This paper delves into the recent advancements in crafting high-performance metal-oxide thin-film transistors (TFTs) via the atomic-layer deposition (ALD) process. As metal-oxide TFTs emerge as pivotal backplane technology for cutting-edge display products like organic light-emitting diode (OLED) televisions and selectors for 3D-DRAM, relentless efforts are underway to push the boundaries of performance through diverse methodologies. Among these, two prominent avenues, namely, adjusting cation composition ratios and innovating novel structural designs, are spotlighted. Both pathways leverage the myriad advantages offered by the ALD process over conventional sputtering methods. The paper elucidates the state-of-the-art characteristics of ALD-deposited oxide semiconductors, revealing promising prospects for ALD-derived metal oxide TFTs to emerge as prime contenders for the next generation of high-end active-matrix displays and 3D DRAM devices.This work was supported by Institute of Information & communications Technology Planning & Evaluation (IITP) under the artificial intelligence semiconductor support program to nurture the best talents (IITP-2024-RS-2023-00253914) grant funded by the Korea government.

Active Layer Thickness-Dependent Reliability of Solution-Processed Indium-Gallium-Zinc Oxide Thin-Film Transistors Under Bias Stress

Amorphous indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) have been widely investigated because of their high carrier mobility and excellent uniformity. The IGZO TFTs’ device performances have significantly advanced, and commercial products based on IGZO TFTs have been released on the display market. On the other hand, solution-processed IGZO TFTs have also been researched to reduce fabrication costs [1]. However, the electrical properties and reliability of solution-processed IGZO TFTs should be improved for display applications compared to vacuum-processed IGZO TFTs. Because the IGZO layer is deposited using different processes, the improvement method of device performance should be investigated considering the solution process characteristics compared to the vacuum process.The thickness control method is one of the different points between the solution and vacuum process. In the vacuum process, the deposition time can control the layer thickness. However, the thickness of the solution-processed IGZO layer can be controlled by the layer stacking or the molarity of the precursor solution. Then, the thin film properties of the solution-processed IGZO layer can be varied depending on thickness. Therefore, the effect of thickness on the IGZO thin film properties should be considered when investigating the device performances of solution-processed IGZO TFTs with different active layer thicknesses.In this study, we investigated the reliability of solution-processed IGZO TFTs under bias stress as active layer thickness varied. Solution-processed IGZO TFTs were fabricated on a heavily doped p-type silicon wafer and thermally grown silicon dioxide using the gate electrode and gate insulator, respectively. The IGZO layer was deposited via a spin coating process using the precursor solution, which was prepared by dissolving indium acetate, gallium nitrate, and zinc acetate into 2-methoxyethanol. After annealing and patterning the IGZO layer, aluminum source and drain electrodes were deposited using thermal evaporation. We controlled the thickness of the solution-processed IGZO layer by controlling the molarity of the precursor solution and fabricated IGZO TFTs with active layer thicknesses of 15 and 80 nm.Solution-processed IGZO TFTs with a thick active layer (Device A) exhibited a negatively shifted threshold voltage and low field-effect mobility compared to devices with a thin active layer (Device B). Moreover, Device A was more significantly influenced by the constant bias stress than Device B. The threshold voltage shift (ΔV th) of Device A was 29.6 V, and that of Device B was 19.8 V, as shown in Figure 1. In other words, the reliability of solution-processed IGZO TFTs was degraded as the active layer thickness increased. The results of electrical properties and reliability of solution-processed IGZO TFTs with different active layer thicknesses were closely related to the defect state level of the IGZO layer. We analyzed the density-of-states (DOS) of solution-processed IGZO TFTs with different active layer thicknesses using the field-effect method [2]. Devices A and B exhibited DOS levels of 1.8×1017 and 9.8×1015 cm-3eV-1, respectively. In other words, the defect states increased as the thickness of solution-processed IGZO TFTs increased. The DOS variations depending on the IGZO layer thickness were attributed to the pin holes or disorder formed during the IGZO layer deposition process. Consequently, we concluded that the thin-film properties, including the DOS level, should be carefully controlled when controlling the active layer thickness to obtain high-performance solution-processed IGZO TFTs. Figure 1

Four-Terminal Polycrystalline-Silicon Vertical Thin-Film Transistors on Glass Substrates for pH Sensor Applications

Thin-film transistors (TFTs) with small footprints, high performance, and low power consumption are essential for forming integrated circuits on glass substrates. Miniaturization of gate length is the most effective means of achieving high performance TFTs. However, owing to the thermal shrinkage of the glass substrate during the manufacturing process, miniaturizing the channel length to the nanometer scale is difficult, as is the case for MOSFETs on Si wafers. To achieve shorter channel lengths, TFTs with vertical, rather than planar, structures have been proposed. Vertical TFTs (VTFTs) are not limited by photolithography equipment because the channel length can be easily controlled by changing the thickness of the spacer layer, and their structure is tolerant to the thermal shrinkage of the glass substrate. Therefore, VTFTs are useful for realizing nanometer-scale channel lengths on glass substrates. In addition, a four-terminal (4T) structure has been reported to achieve higher TFT performance. This structure exhibits the best performance in a double-gate (DG) drive in which the top gate (TG) and bottom gate (BG) operate simultaneously. Moreover, threshold voltage (Vth) control is possible in a 4T drive in which the TG and BG are separated and driven independently. We recently developed a 4T poly-Si VTFT on a glass substrate. This structure can be applied to an extended-gate (EG) pH sensor. In this study, we applied the n-channel 4T poly-Si VTFT, that has both vertical and 4T structures, to pH sensors.A fused quartz glass substrate was used in this study. First, 40 nm of Mo was sputtered, and a BG was formed using photolithography and wet etching. Then, using the BG as a hard mask, the fused quartz glass was etched 150 nm deep using reactive ion etching (RIE) to form sidewalls. Next, 50-nm thick SiO2 was deposited as the BG dielectric, and 50-nm thick non-doped amorphous silicon (a-Si) was deposited as the active region by plasma-enhanced chemical vapor deposition (PECVD). The non-doped a-Si was then crystallized by nickel metal-induced crystallization (Ni-MIC) at 580 ℃ for 8 h. Phosphorus (P) was implanted in the source–drain (S/D) region at a tilt angle of 30°. Next, a 50-nm thick SiO2 was deposited as the TG dielectric using PECVD, followed by activation heat treatment. A Mo film was then formed via sputtering, and the TG metal was formed via wet etching. Subsequently, a 200-nm thick SiO2 layer was deposited as an isolation layer, and the contact holes for the S/D, TG, and BG were opened by RIE. The electrodes were formed using aluminum sputtering and wet etching. Finally, hydrogenation treatment was performed at 380 ℃ for 2 h.The fabricated 4T poly-Si VTFTs can be operated in four drive modes depending on the wiring connections: TG, BG, DG, and 4T. The pH sensor is operated by connecting the glass electrode to the TG. This measurement method is advantageous because the TG strongly interacts with the BG because of its structure. The variations in the drain current can be confirmed under BG driving when the TG voltage is varied in 20 mV steps. A variation of 20 mV in the TG voltage corresponds to a change of approximately 0.5 pH in glass electrode. The actual construction of the sensor circuit showed that the output voltage changed in accordance with the pH change, and the maximum sensitivity was confirmed to be greater than 59 mV/pH at Vdd = 1.0 V. Figure 1

All Inkjet-Printed Electronics from Electrochemically Exfoliated Two-Dimensional Nanomaterials

Inkjet printing is in the spotlight as a cost-effective and scalable method to assemble colloidal materials into desired patterns in a vacuum- and lithography-free manner. Two-dimensional (2D) nanosheets represent a promising class of nanomaterials for the fabrication of printed electronics due to their excellent adaptability to solution- based processing which facilitates the creation of stable ink formulations, accommodating a diverse array of electronic properties from metals, semiconductors, to insulators. Additionally, their dangling bond-free surface enables atomically thin, electronically-active thin films with van der Waals contacts which significantly reduce the junction resistance. This research presents a demonstration of fully inkjet- printed thin-film electronics consisting of electrochemically exfoliated graphene, MoS2, and HfO2 as metallic electrodes, a semiconducting channel, and a high-k dielectric layer, respectively. In particular, the high-k dielectric layer is prepared via two-step; electrochemical exfoliation of semiconducting HfS2 followed by thermal oxidation process to overcome incompatibility of electrochemical exfoliation with insulating crystals. Consequently, all inkjet-printed 2D nanosheets with various electronic types enable the fabrication of high-performance thin-film transistors, which exhibit enhanced field-effect mobilities and current on/off ratios of ~10 cm2 V-1s-1 and >105, respectively, at low operating voltage. Figure 1

P-Type Oxide Thin-Film Transistor with Unprecedented Hole Field-Effect Mobility for an All-Oxide CMOS CFET-like Inverter Suitable for Monolithic 3D Integration.

The lack of low temperature processable, high-performance p-type oxide thin-film transistors (TFTs) limits their implementation in monolithically integrated back-end-of-line (BEOL) CMOS circuitries. In this work, we demonstrate a reactive magnetron-sputtered SnOx TFT with unprecedented hole field-effect mobility (μFE-hole) of 38.7 cm2/V·s, as well as an on/off current ratio (Ion/off) of 2.5 × 103 and lower subthreshold swing (SS) of 240.9 mV/dec when compared to reported works on p-type oxide-based TFTs. Material characterization correlated with the SnOx TFTs' electrical behavior elucidated the performance to the structural and compositional phase modulation of the SnOx thin films, modulated by O2 partial pressure during deposition and post-encapsulation annealing. By integrating the SnOx TFT with an IGZO TFT in both planar and stacked complementary FET-like form, we demonstrated a true oxide-based CMOS inverter, achieving one of the highest voltage gains of 57 and the lowest static power consumption down to 34 pW for both on and off states.

A Tricyclic Framework with Integrated B←N and Cyano Dual Functionalization for Superior n-Type Organic Electronics.

n-Type conjugated polymers featuring low-lying lowest unoccupied molecular orbital (LUMO) energy levels are essential for achieving high-performance n-type organic thin-film transistors (OTFTs) and organic thermoelectrics (OTEs). However, the synthesis of acceptors with strong electron-withdrawing characteristics presents a significant challenge. Herein, a peripheral functionalization strategy is employed on the tricyclic framework anthracene by introducing dual N,O-bidentate BF2/B(CN)2 groups to enhance its electron-withdrawing capability. This approach successfully navigates synthetic challenges, leading to the development of two novel acceptor building blocks: DBNF and DBNCN. Compared to the counterparts with a single N,O-bidentate BF2/B(CN)2 moiety, DBNF and DBNCN exhibit an extended π-backbone, enhanced molecular packing, and improved electron-withdrawing properties. Utilizing these innovative acceptor monomers, copolymers, PDBNF and PDBNCN, are synthesized, which exhibit considerably suppressed LUMO ≈-4.0 eV. The deep LUMO of PDBNF together with its favourable bimodal packing orientation leads to remarkable electron mobility of 3.04 cm2 V-1 s-1 with improved stability in OTFTs. Importantly, efficient n-doping in OTEs is achieved with PDBNCN, exhibiting exceptional conductivity of 95.5 S cm-1 and a maximum power factor of 147.8 μW m-1 K-2-among the highest reported for solution-processed n-type polymers. This work underscores the effectiveness of introducing dual B←N and cyano functionalities in attaining high-performance n-type plastic electronics.

Combustion-assisted low-temperature ZrO2/SnO2 films for high-performance flexible thin film transistors

We developed high-performance flexible oxide thin-film transistors (TFTs) using SnO2 semiconductor and high-k ZrO2 dielectric, both formed through combustion-assisted sol-gel processes. This method involves the exothermic reaction of fuels and oxidizers to produce high-quality oxide films without extensive external heating. The combustion ZrO2 films were revealed to have an amorphous structure with a higher proportion of oxygen corresponding to the oxide network, which contributes to the low leakage current and frequency-independent dielectric properties. The ZrO2/SnO2 TFTs fabricated on flexible substrates using combustion synthesis exhibited excellent electrical characteristics, including a field-effect mobility of 26.16 cm2/Vs, a subthreshold swing of 0.125 V/dec, and an on/off current ratio of 1.13 × 106 at a low operating voltage of 3 V. Furthermore, we demonstrated flexible ZrO2/SnO2 TFTs with robust mechanical stability, capable of withstanding 5000 cycles of bending tests at a bending radius of 2.5 mm, achieved by scaling down the device dimensions.

Reliability analysis under bias stress and elevated temperature of dual-gate IGZO TFT

Indium–gallium–zinc oxide (IGZO) as a star material has been broadly applied in multiple functional devices, including planar displays, flexible electronic devices, and photoelectronics. In recent years, the development of artificial intelligence and great data also extends the application of IGZO-based thin film transistors (TFTs) to memory, memristors, and neuromorphic computing. Thus, the research of high performance and reliable IGZO TFTs attracts tremendous attention worldwide. Herein, a high-quality IGZO thin film was deposited via atomic layer deposition, and a dual-gate (DG) IGZO TFT was fabricated. Comprehensive electrical characterization was conducted on the fabricated DG IGZO TFTs, revealing that DG IGZO TFTs exhibited good performance for reliability analysis. The reliability and degradation mechanism of the DG IGZO TFT was systematically investigated under bias stress at room temperature and elevated temperatures of 350, 400, and 450 K by the comprehensive electrical characterization. Results indicate that the defects of the dual gate insulators and the interfaces majorly influence the degradation under bias stresses, while the carrier scattering of the IGZO channel is the major degradation mechanism under elevated temperatures. These findings highlight the degradation mechanism of the DG IGZO TFT under bias stress and elevated temperatures from a novel viewpoint, which provides a utilizable reference to its application in circuits.

A Novel Strategy to Achieve High-Performance Titanium-Doped InZnO Thin-Film Transistors Using Atomic Layer Deposition

A Novel Strategy to Achieve High-Performance Titanium-Doped InZnO Thin-Film Transistors Using Atomic Layer Deposition

Impact of atomic layer deposition supercycle design on the reliability of heterogenous IGZO channel TFTs

Oxide semiconductor thin-film transistors (TFTs) are promising candidates for application in display backplanes and memory devices. To ensure both high performance and stable electrical properties of oxide TFTs over long-term use, superior mobility and device stability need to be obtained. In this regard, atomic layer deposition (ALD) has gained attention as a facile method for obtaining conformal oxide films under defect-free conditions and adjusting the composition or distribution for targeted TFT performance. Here, we propose that, even with the same bulk composition, variations in the local composition using an ALD supercycle design can significantly affect the TFT performance, particularly the bias-temperature stability. To ascertain the influence of the local cation distribution on the performance, we compared two supercycle designs by reversing the sub-cycles of indium, gallium, and zinc with identical bulk In–Ga–Zn ratios. Despite minimal changes in the electrical characteristics, such as the mobility and threshold voltage, of the two TFTs designed with ALD supercycles, there was a significant difference in their reliability. Devices with an indium-rich IGZO active layer on the back channel exhibited a hump phenomenon and approximately five times greater Vth degradation (ΔVth: −0.67 V to −3.36 V). By conducting an additional case study of IGZO TFTs and film analysis, we confirmed that mobility is largely governed by the bulk composition, whereas the local surface composition, serving as the back channel, is the key to reliability. The device performance results could be confirmed through the surface and bulk analyses of heterogeneous films engineered through the ALD supercycle design. Furthermore, it has been proposed that optimizing the ALD supercycle design is the key to obtaining high-performance oxide semiconductor TFTs.

Plasma-enhanced atomic layer deposition of indium-free ZnSnOx thin films for thin-film transistors

An appropriate synthesis technique for growing high-quality indium-free ZnSnOx (ZTO) films should be developed to achieve high-performance thin-film transistors (TFTs) utilizing ZTO films. This study investigated the growth characteristics and electrical properties of ZTO thin films grown via plasma-enhanced atomic layer deposition (PEALD) using bis(1-dimethylamino-2-methyl-2-propoxide)Sn, diethylzinc, and O2 plasma to optimize the composition and enhance the device performance. Deviations were observed in the growth per cycle when using PEALD for ZTO, compared with binary oxides. In the PEALD of the ZTO films, the introduction of the SnO2 sub-cycle enhanced the mass gain in the ZnO sub-cycle, whereas the mass gain in the SnO2 sub-cycle decreased with the addition of the ZnO sub-cycle. This was attributed to changes in the density of the functional groups on the reaction surface. Precise control over the composition was achieved, enabling the identification of the optimal Zn58Sn42Ox composition. Post-deposition annealing significantly improved the TFT performance, with devices showing enhanced mobility, positive shifts in the threshold voltage, and reduced subthreshold swing values. These improvements stemmed from reductions in oxygen vacancies and sub-gap defect states. These findings highlight the potential of PEALD-grown ZTO films for use in high-performance, cost-effective TFTs, facilitating their integration into modern semiconductor electronics.

Novel solution-gated transistor sensor-based SnO2 epitaxial thin films grown by pulsed laser deposition for nitrite detection.

A solution-gate controlled thin-film transistor with SnO2 epitaxial thin films (SnO2-SGTFT) is successfully utilized for highly sensitive detection of nitrite. The SnO2 films are deposited as channel materials on a c-plane sapphire (c-Al2O3) substrate through pulsed laser deposition (PLD), with superior crystal quality and out-of-plane atomic ordering. PtAu NPs/rGO nanocomposites are electrodeposited on agold electrode to function as a transistor gate to further enhance the nitrite catalytic performance of thedevice. The change in effective gate voltage due to the electrooxidation of nitrite on the gate electrode is the primary sensing mechanism of the device. Based on the inherent amplification effect of transistors, the superior electrical properties of SnO2, and the high electrocatalytic activity of PtAu NPs/rGO, the SnO2-SGTFT sensor has a low detection limit of 0.1nM and a wide linear detection range of 0.1nM ~ 50mM at VGS = 1.0V. Furthermore, the sensor has excellent characteristics such as rapid response time, selectivity, and stability. The practicability of the device has been confirmed by the quantitative detection of nitrite in natural lake water. SnO2 epitaxial films grown by PLD provide a simple and efficient way to fabricate nitrite SnO2-SGTFT sensors in environmental monitoring and food safety, among others. It also provides a reference for the construction of other high-performance thin-film transistor sensors.

Junctionless Structure Indium-Tin Oxide Thin-Film Transistors Enabling Enhanced Mechanical and Contact Stability.

In recent years, considerable attention has focused on high-performance and flexible crystalline metal oxide thin-film transistors (TFTs). However, achieving both high performance and flexibility in semiconductor devices is challenging due to the inherently conductive and brittle nature of crystalline metal oxide. In this study, we propose a facile way to overcome this limitation by employing a junctionless (JL) TFT structure via oxygen plasma treatment of the crystalline indium-tin oxide (ITO) films. The oxygen plasma treatment significantly reduced oxygen vacancies in the ITO films, contributing to the significant reduction in the carrier concentration from 4.67 × 1020 to 1.39 × 1016. Importantly, this reduction was achieved without inducing any noticeable structural changes in the ITO, enabling the successful realization of ITO JL TFTs with an adjustable threshold voltage. Furthermore, the ITO JL TFTs demonstrate good stability and reliability under various bias stress conditions, aging in the air atmosphere, and high-temperature processes. In addition, the ITO JL TFTs exhibit low light sensitivity due to the wide bandgap of ITO and further suppression of Vo defects, making them suitable for applications requiring stable performance under light exposure. To compare and analyze the flexibility of the JL structure and conventional structure with additional source/drain (S/D) junction in ITO TFTs with nonencapsulation, we utilized mechanical simulations and transmission line method (TLM). By employing the JL structure in ITO TFT through carefully optimized oxygen plasma treatment, we successfully mitigated stress concentration at the S/D-channel interface. This resulted in a JL ITO TFT that exhibited a change in contact resistance of less than 20% even after 20,000 bending cycles. Consequently, a stable and flexible ITO TFT with field-effect mobility (μFE) of 12.74 cm2/(V s) was realized, outperforming conventionally structured ITO TFTs with additional S/D junction, where the contact resistance nearly tripled.