High-performance Thin-film Transistors Research Articles

Order of magnitude improvement in the transport performance of carbon nanotube films by completely removing surfactants

Surfactant-based separation techniques have been developed for the high-efficiency production of high-purity semiconducting single-wall carbon nanotubes (s-SWCNTs), which establish an important material foundation for the preparation of high-performance carbon-based electronic devices. However, surfactant molecules wrapping around SWCNTs during structural separation inevitably degrade the resulting device performances due to increasing contact resistance between the SWCNTs and electrodes and between individual SWCNTs. Here, we developed a simple and effective strategy for completely removing the surfactant molecules around separated s-SWCNTs by annealing and rinsing. With this technique, defects were not clearly increased in the crystal structure of SWCNTs, and the transport performances of SWCNT-based thin film transistors (TFTs), including the on-state current and mobility, were improved by approximately an order of magnitude, while the on-off ratio increased by nearly 1.5 orders of magnitude. Upon shortening of the channel lengths of the devices, high-performance TFTs were fabricated based on an increase in the proportion of individualized SWCNTs that directly connected the source and drain electrodes. The present technique provides an important foundation for promoting the development of carbon-based electronic devices.

High-performance thin-film transistors based on aligned carbon nanotubes for mini- and micro-LED displays

Inorganic mini-LEDs (mLEDs) and micro-LEDs (μLEDs) have ultrahigh luminance and long lifetimes, and are challenging liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays for next-generation displays. Backplane thin-film transistors (TFTs) for mLED/μLED displays with high mobility and large driving current are under development as currently widely used backplane active materials such as crystalline silicon (CMOS Si), amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), and metal oxides are facing difficulties to meet the requirements. Semiconducting carbon nanotubes (s-CNTs) have long been considered as promising materials for TFTs because of their unique electronic properties. However, TFTs based on s-CNT random networks show inadequate performance due to large amounts of inter-tube junctions. Here, we report high performance TFTs based on wafer-scale, high-density aligned s-CNT array (A-CNT) for mLED/μLED driving backplanes. These A-CNT TFTs with micrometer scale channel length were fabricated using standard semiconductor manufacturing process, and exhibited mobility as high as 160 cm2/Vs and driving current as large as 417 μA/μm at operation voltage of ∼3 V, exceeding commercially available TFTs with similar device sizes. In addition, these A-CNT TFTs have demonstrated good driving capability for commercial mLEDs in a one-transistor-one-diode (1T1D) pixel circuit configuration, and been capable of driving commercially available mLED/μLED displays. Moreover, a prototype display with 2 × 2 mLED array have been demonstrated with full control of each pixel, manifesting the great potential for A-CNT TFT technology for backplane of mLED/μLED displays.

Photolithographic Rugged Electrode for High-Density Low-Contact-Resistance Coplanar Organic Transistors.

The realization of high-performance photolithographic coplanar organic thin film transistors (OTFTs) is fundamental to boost cosmicallycommercial applications of organic electronics. However, photolithographic coplanar OTFTs generally suffer from poor charge injection and therefore poor filed-effect performance. Here, a simple and effective strategy is developed to fabricate photolithographic rugged electrodes, and successfully achieve high-density low-contact-resistance photolithographic coplanar OTFTs. Based on this versatile electrode, the wafer-scale photolithographic rugged electrode can be easily achieved, and the device density of the coplanar OTFTs is as high as 28000cm-2 . The device shows excellent electrical properties with mobility up to 2.01cm2 V-1 s-1 and Rc as low as 7.8kΩcm, which is superior to all the reported Ag-electrode coplanar OTFTs. This work shows a reliable strategy to reduce the contact resistance of photolithographic coplanar OTFTs and elucidates the effect of injection resistance (Rinj ) and access resistance (Racc ) on coplanar OTFTs.

Atomically Thin Amorphous Indium-Oxide Semiconductor Film Developed Using a Solution Process for High-Performance Oxide Transistors.

High-performance oxide transistors have recently attracted significant attention for use in various electronic applications, such as displays, sensors, and back-end-of-line transistors. In this study, we demonstrate atomically thin indium-oxide (InOx) semiconductors using a solution process for high-performance thin-film transistors (TFTs). To achieve superior field-effect mobility and switching characteristics in TFTs, the bandgap and thickness of the InOx were tuned by controlling the InOx solution molarity. As a result, a high field-effect mobility and on/off-current ratio of 13.95 cm2 V-1 s-1 and 1.42 × 1010, respectively, were achieved using 3.12-nanometer-thick InOx. Our results showed that the charge transport of optimized InOx with a thickness of 3.12 nm is dominated by percolation conduction due to its low surface roughness and appropriate carrier concentration. Furthermore, the atomically thin InOx TFTs showed superior positive and negative gate bias stress stabilities, which are important in electronic applications. The proposed oxide TFTs could provide an effective means of the fabrication of scalable, high-throughput, and high-performance transistors for next-generation electronic applications.

Synthesis of a Tellurium Semiconductor with an Organic–Inorganic Hybrid Passivation Layer for High-Performance p-Type Thin Film Transistors

Synthesis of a Tellurium Semiconductor with an Organic–Inorganic Hybrid Passivation Layer for High-Performance p-Type Thin Film Transistors

As-Grown Crystalline InGaZnO by Spray Pyrolysis on a Flexible Substrate for a Thin-Film Transistor with Excellent Stability.

The development of low-cost, high-mobility oxide thin-film transistors (TFTs) with excellent stability is of increasing interest. The coplanar oxide TFTs can be used for high-speed, large-area, and high-resolution displays. Here, we report highly oriented, as-grown crystalline InGaZnO (c-IGZO) with very low oxygen vacancy defects using spray pyrolysis at the substrate temperature of 425 °C. The c-IGZO exhibits a highly oriented, c-axis aligned crystal perpendicular to the substrate with a high mass density of 6.73 g cm-3 without any disordered incubation layer. Its resistivity can be decreased to 0.42 mΩ cm by NF3 plasma doping, which is essential to achieving high-performance coplanar TFT. We have demonstrated the application of this material to high-performance flexible TFTs. The self-aligned, coplanar c-IGZO TFTs on the polyimide substrate exhibit an average field-effect mobility of 39.60 cm2 V-1 s-1, threshold voltage of -1.00 V, subthreshold swing of 0.21 V dec-1, and on/off current ratio over 108. The ring oscillator and gate driver made of the c-IGZO TFTs exhibit a propagation delay of 8.77 ns/stage and rising/falling times of 648/564 ns, respectively. Therefore, the as-grown c-IGZO by spray pyrolysis has the potential to be utilized as a new oxide semiconductor for the production of low-cost, flexible TFT electronics.

Utilizing Dip-Coating to Fabricate Gate Dielectric and Semiconductor for Thin-Film Transistors

The potential applications of advanced electronic materials in large-area, printable, and flexible electronics have generated significant interest. However, creating high-performance, low-voltage thin-film transistors (TFTs) for these applications remains difficult due to a lack of advanced gate dielectric and semiconductor materials that meet both ease-of-fabrication requirements and high electrical performance. In this study, we present high-performance gate dielectric thin-films, which were fabricated using a facile solution-based technique, and then employed to realize low operating voltage organic and metal oxide semiconductor-based thin-film transistors. The high-k oxide gate dielectrics were produced via a simple dip-coating method, resulting in the formation of thin-oxide layers. These novel oxide gate dielectrics demonstrated exceptional dielectric properties, with large capacitances (up to 430 nF/ cm2), low-level leakage current densities (< 3 × 10-8A/cm2 at 4 V), featureless morphology (rms roughness < 0.36 nm), and high transparency (> 85%). Consequently, these dip-coated gate dielectrics can be incorporated into thin-film transistors, utilizing pentacene as p-type organic semiconductors. Furthermore, by employing dip-coating, indium oxide and indium-gallium-zinc oxide can be utilized as n-type inorganic semiconductors, allowing for the fabrication of low-voltage operation and high-performance inorganic TFTs. The resulting TFTs functioned at ultralow voltages (< ± 2 V) and achieved high transistor performance (hole mobility: 0.28 cm2V-1·s-1, electron mobility: ~2.0 cm2V-1·s-1 and on/off current ratio >105).

Interfacial molecular screening of polyimide dielectric towards high-performance organic field-effect transistors

The compatibility of the gate dielectrics with semiconductors is vital for constructing efficient conducting channel for high charge transport. However, it is still a highly challenging mission to clearly clarify the relationship between the dielectric layers and the chemical structure of semiconductors, especially vacuum-deposited small molecules. Here, interfacial molecular screening of polyimide (Kapton) dielectric in organic field-effect transistors (OFETs) is comprehensively studied. It is found that the semiconducting small molecules with alkyl side chains prefer to form a high-quality charge transport layer on polyimide (PI) dielectrics compared with the molecules without alkyl side chains. On this basis, the fabricated transistors could reach the mobility of 1.2 cm2 V−1 s−1 the molecule with alkyl side chains on bare PI dielectric. What is more, the compatible semiconductor and dielectric would further produce a low activation energy (EA) of 3.01 meV towards efficient charge transport even at low temperature (e.g., 100 K, 0.9 cm2 V−1 s−1). Our research provides a guiding scheme for the construction of high-performance thin-film field-effect transistors based on PI dielectric layer at room and low temperatures.

All-Solution-Driven Thin-Film Transistor With Low Power Dissipation for Logic Electronics and Neuronal Synapse

For the realization of low-power consumption brain-inspired neuromorphic devices which mimic the biological neuronal information processing methodology, the development of transistors capable of synaptic behaviors and neuronal computation has attracted widespread attention. However, ultrathin, solid-state neuromorphic devices with ultralow energy consumption are still in the exploration stage. Herein, based on an all-solution strategy, oxide-based electrical-double-layer (EDL) thin film transistors (TFTs) have been constructed, demonstrating good operational stability and excellent logic operation functions. Motivated by these excellent characteristics, the TFTs devices triggered by electrical pulses can mimic synaptic behaviors, including excitatory postsynaptic current (EPSC) and paired-pulse facilitation (PPF). In addition, response to electrical stimulus, high-pass filtering characteristics, and short-term memory (STM) and long-term memory (LTM) characteristics have been achieved and investigated. These results reported here have demonstrated that all-solution-driven high-performance oxide-based TFTs enable the achievement of logic electronics with low-power consumption and brain-inspired neuromorphic devices.

Cascaded Logic Gates Based on High-Performance Ambipolar Dual-Gate WSe2 Thin Film Transistors.

Ambipolar dual-gate transistors based on low-dimensional materials, such as graphene, carbon nanotubes, black phosphorus, and certain transition metal dichalcogenides (TMDs), enable reconfigurable logic circuits with a suppressed off-state current. These circuits achieve the same logical output as complementary metal-oxide semiconductor (CMOS) with fewer transistors and offer greater flexibility in design. The primary challenge lies in the cascadability and power consumption of these logic gates with static CMOS-like connections. In this article, high-performance ambipolar dual-gate transistors based on tungsten diselenide (WSe2) are fabricated. A high on-off ratio of 108 and 106, a low off-state current of 100 to 300 fA, a negligible hysteresis, and an ideal subthreshold swing of 62 and 63 mV/dec are measured in the p- and n-type transport, respectively. We demonstrate cascadable and cascaded logic gates using ambipolar TMD transistors with minimal static power consumption, including inverters, XOR, NAND, NOR, and buffers made by cascaded inverters. A thorough study of both the control gate and the polarity gate behavior is conducted. The noise margin of the logic gates is measured and analyzed. The large noise margin enables the implementation of VT-drop circuits, a type of logic with reduced transistor number and simplified circuit design. Finally, the speed performance of the VT-drop and other circuits built by dual-gate devices is qualitatively analyzed. This work makes advancements in the field of ambipolar dual-gate TMD transistors, showing their potential for low-power, high-speed, and more flexible logic circuits.

Selectively Nitrogen Doped ALD-IGZO TFTs with Extremely High Mobility and Reliability.

Achieving high mobility and reliability in atomic layer deposition (ALD)-based IGZO thin-film transistors (TFTs) with an amorphous phase is vital for practical applications in relevant fields. Here, we suggest a method to effectively increase stability while maintaining high mobility by employing the selective application of nitrous oxide plasma reactant during plasma-enhanced ALD (PEALD) at 200 °C process temperature. The nitrogen-doping mechanism is highly dependent on the intrinsic carbon impurities or nature of each cation, as demonstrated by a combination of theoretical and experimental research. The Ga2O3 subgap states are especially dependent on plasma reactants. Based on these insights, we can obtain high-performance indium-rich PEALD-IGZO TFTs (threshold voltage: -0.47 V; field-effect mobility: 106.5 cm2/(V s); subthreshold swing: 113.5 mV/decade; hysteresis: 0.05 V). In addition, the device shows minimal threshold voltage shifts of +0.45 and -0.10 V under harsh positive/negative bias temperature stress environments (field stress: ±2 MV/cm; temperature stress: 95 °C) after 10000 s.

Room temperature-grown highly oriented p-type nanocrystalline tellurium thin-films transistors for large-scale CMOS circuits

Although facile fabrication of high-performance thin-film transistor (TFT)-based complementary metal oxide–semiconductor (CMOS) circuits over a large area has generated significant interest, the lack of reliable and uniform p-type TFTs is hindering it. In this study, we prepared high-performance CMOS circuits using room temperature deposited nanocrystalline tellurium (nc-Te) and sputtered amorphous-indium gallium zinc oxide (a-IGZO) TFTs. The facile polyethyleneimine (PEI) surface treatment enabled Te atom anchoring and crystal orientation control along with continuous surface coverage, resulting in a high-performance TFT with an average mobility of 21.1 cm2V−1s−1 and an Ion/Ioff ratio of 104. By introducing monolithic integration of nc-Te and a-IGZO TFTs, various CMOS circuits including inverter, NAND, and NOR circuits were fabricated and operated quite logically. Moreover, seven-stage ring oscillators comprising 14 cross-wired TFTs validated the cascading of multiple stages and device uniformity of the complementary system, achieving an oscillation frequency up to 392.16 kHz at VDD of 20 V. nc-Te on a PEI-treated surface offers a general route to producing high-performance and stable p-type semiconductors while ensuring compatibility with standard CMOS processing and large-scale on-chip device applications.

Hf-doped ZnO transistor with high bias stability and high field-effect mobility by modulation of oxygen vacancies and interfaces

ZnO-based thin film transistors (TFTs) with high bias stability are challenging due to the intrinsic defects and overhigh interface trap density. In this work, we fabricated Hf-doped ZnO films with different cycle ratio of Zn/Hf via atomic layer deposition and subsequent annealing treatment. The results show that the cycle ratio of Zn/Hf is optimized to be 10:1, and the corresponding atomic ratio is 2.24%. The threshold voltage and subthreshold swing of the devices are improved as the annealing temperature increases, owning to the decrease of the oxygen vacancies and interface trap density. Furthermore, we developed Hf-doped ZnO TFT with high bias stability by introducing HfO2 intermediate layer between the active layer and SiO2 dielectric layer, and the shift of threshold voltage is as low as -0.273 V, showing high bias stability. Also, the device has the high field-effective mobility of 52.4 cm2/Vs, low subthreshold swing of 0.68 V/dec and high Ion/Ioff of 3.6 × 108. The results indicate a promising fabrication method for high-performance ZnO-based TFTs, which may be applied in logic circuits, radio frequency identification and so on.

High-performance p-channel CuIBr thin-film transistor synthesized from solution in the atmosphere

The p-type transparent semiconductor CuI has a high potential to be used in thin film transistors (TFTs) due to high hole mobility and solution processability. However, the lower copper vacancy formation energy and the subsequent high hole concentration in CuI lead to a low on/off current ratio (ION/IOFF) for CuI TFT devices. The density functional theory results suggest that the copper vacancy formation energy increases with the CuBr content in the Br-doped CuI film, resulting in lower hole concentration. Alloying CuI with CuBr is proposed to reduce the hole concentration in the CuIBr alloy. The CuIBr TFTs with Br content ranging from 0% to 10% were fabricated using the solution method. It is found that the hole mobility decreases from 8 to 1 cm2 V−1 s−1, while the ION/IOFF ratio increases from 102 to 104 with the increasing Br content. The CuIBr TFT with 7.5% Br content exhibits a high hole mobility larger than 5 cm2 V−1 s−1 and high ION/IOFF ratio of 104, which paves the way for inorganic-based CMOS circuits on flexible and transparent substrates.

Design and analysis of high-performance double-gate ZnO nano-structured thin-film ISFET for pH sensing applications

This paper reports a high-performance double-gate zinc-oxide thin-film ion-sensitive field-effect transistor (DG-ZnO-ISFET) for pH sensing applications. The sensing mechanism of DG-ZnO-ISFET and a simulation model for pH sensing analysis are demonstrated herein. Various aspects of the device are elucidated through the study of channel conductance, electron density, energy band, and surface-potential profiles. The DG-ZnO-ISFETs enhance minor surface potential variations by capacitive coupling across the dielectrics of the top and bottom gates. Further, it operates by altering the bottom-gate voltage (VBG), obviating the need for a reference electrode system. The device depicts enhanced voltage sensitivity of 205.57 mV/pH, which is substantially 3.48 × greater than the Nernst limit sensitivity. In addition, the DG-ZnO-ISFET renders a maximum current sensitivity of 10.82 mA/mm.pH at VBG=5V. Furthermore, it exhibits high linearity in both voltage and current sensitivity, with the coefficient of determination (R2) values of 0.984 and 0.964, respectively. With their increased sensitivity and linearity, DG-ZnO-ISFETs have the potential device for next-generation biosensors.

High-Performance Thin-Film Transistors with ZnO:H/ZnO Double Active Layers Fabricated at Room Temperature.

H doping can enhance the performance of ZnO thin-film transistors (TFTs) to a certain extent, and the design of double active layers is an effective way to further improve a device's performance. However, there are few studies on the combination of these two strategies. We fabricated TFTs with ZnO:H (4 nm)/ZnO (20 nm) double active layers by magnetron sputtering at room temperature, and studied the effect of the hydrogen flow ratio on the devices' performance. ZnO:H/ZnO-TFT has the best overall performance when H2/(Ar + H2) = 0.13% with a mobility of 12.10 cm2/Vs, an on/off current ratio of 2.32 × 107, a subthreshold swing of 0.67 V/Dec, and a threshold voltage of 1.68 V, which is significantly better than the performance of single active layer ZnO:H-TFTs. This exhibits that the transport mechanism of carriers in double active layer devices is more complicated. On one hand, increasing the hydrogen flow ratio can more effectively suppress the oxygen-related defect states, thus reducing the carrier scattering and increasing the carrier concentration. On the other hand, the energy band analysis shows that electrons accumulate at the interface of the ZnO layer close to the ZnO:H layer, providing an additional path for carrier transport. Our research exhibits that the combination of a simple hydrogen doping process and double active layer construction can achieve the fabrication of high-performance ZnO-based TFTs, and that the whole room temperature process also provides important reference value for the subsequent development of flexible devices.

Energy-band engineering by 2D MXene doping for high-performance homojunction transistors and logic circuits

The homojunction based on Ti3C2Tx MXene-doped In2O3 and indium oxide as the channel layer is realized in high-performance metal oxide thin film transistors (TFTs). Doping of MXene into In2O3 results in n-type semiconductor behavior, realizing tunable work function of In2O3 from 5.11 to 4.79 eV as MXene content increases from 0 to 2 wt.%. MXene-doped In2O3-based homojunction TFT presents optimal performance with electron mobilities of greater than 27.10 cm2/(V s) at 240 °C, far exceeding the maximum mobility of 3.91 cm2/(V s) for single-layer In2O3 TFTs. The improved performance originates from boosting of a two-dimensional electron gas (2DEG) formed at carefully engineered In2O3/MXene-doped In2O3 oxide homojunction interface. Besides, the transformation in conduction mechanism leads to better stability of MXene-doped In2O3 homojunction devices compared to undoped bilayer In2O3. Low-frequency noise further illustrates that doping MXene into In2O3 helps to reduce the device trap density, demonstrating excellent electrical performance. A resistor-loaded unipolar inverter based on In2O3/0.5% MXene-In2O3 TFT has demonstrated full swing characteristics and a high gain of 13. The effective doping of MXene into constructed homojunction TFTs not only contributes to improved stability, but also provides an effective strategy for designing novel homojunction TFTs for low-cost oxide-based electronics.

Self-Doping Naphthalene Diimide Conjugated Polymers for Flexible Unipolar n-Type OTFTs.

The development of high-performance organic thin-film transistor (OTFT) materials is vital for flexible electronics. Numerous OTFTs are so far reported but obtaining high-performance and reliable OTFTs simultaneously for flexible electronics is still challenging. Herein, it is reported that self-doping in conjugated polymer enables high unipolar n-type charge mobility in flexible OTFTs, as well as good operational/ambient stability and bending resistance. New naphthalene diimide (NDI)-conjugated polymers PNDI2T-NM17 and PNDI2T-NM50 with different contents of self-doping groups on their side chains are designed and synthesized. The effects of self-doping on the electronic properties of resulting flexible OTFTs are investigated. The results reveal that the flexible OTFTs based on self-doped PNDI2T-NM17 exhibit unipolar n-type charge-carrier properties and good operational/ambient stability thanks to the appropriate doping level and intermolecular interactions. The charge mobility and on/off ratio are fourfold and four orders of magnitude higher than those of undoped model polymer, respectively. Overall, the proposed self-doping strategy is useful for rationally designing OTFT materials with high semiconducting performance and reliability.

Selective Purity Modulation of Semiconducting Single-Walled Carbon Nanotube Networks for High-Performance Thin-Film Transistors

Single-walled carbon nanotube (SWCNT) random networks have become strong candidates for next-generation electronics due to their exceptional mechanical, electrical, and optical properties. However, metallic nanotubes in networks generally incur a trade-off between the charge carrier mobility and on/off ratio, limiting the performance of SWCNT-based devices. Therefore, various methods to increase the purity of semiconducting nanotubes in entire random networks have been reported, but this direction has faced other issues, such as nanotube shortening, higher cost, and higher energy. Here, we introduce SWCNT random network-based thin-film transistors (SWCNT TFTs) with a varying purity profile of semiconducting SWCNTs across the channel, exploiting the superior mobility of metallic SWCNTs by partially tuning the semiconducting SWCNT purity and developing a novel perspective on metallic nanotubes in semiconductor channels. Based on the high-precision drop-on-demand capability of inkjet printing and various concentrations of semiconducting SWCNT ink, we form selectively patterned channel regions with different semiconducting SWCNT purities. The metallic nanotube-dominant region drastically increases the carrier density with a minimized Schottky barrier, while high-purity semiconducting regions at the channel boundaries effectively block off-state leakage through carrier depletion. As a result, the SWCNT TFTs with selectively patterned metallic nanotube regions show superior carrier mobility (75.50 cm2 V–1 s–1) and channel width normalized on-current (34.33 nA μm–1) without compromising the on/off ratio (1.62 × 107). To show the feasibility of our device in high-performance electronics, we demonstrate all-inkjet-printed flexible display driving circuits with two transistors that enable low-power, high-performance operation in display applications.

Diketopyrrolopyrrole-based Conjugated Polymers as Representative Semiconductors for High-Performance Organic Thin-Film Transistors and Circuits

Diketopyrrolopyrrole-based Conjugated Polymers as Representative Semiconductors for High-Performance Organic Thin-Film Transistors and Circuits