High-performance Microprocessors Research Articles

Dynamic voltage and frequency management for a low-power embedded microprocessor

High-performance and low-power microprocessors are key to PDA applications. A dynamic voltage and frequency management (DVFM) scheme with leakage power compensation effect is introduced in a microprocessor with 128-bit wideband 64-Mb embedded DRAM. The DVFM scheme autonomously controls clock frequency from 8 to 123 MHz in steps of 0.5 MHz and also adaptively controls supply voltage from 0.9 to 1.6 V in steps of 5 mV, achieving 82% power reduction in personal information management scheduler application and 40% power reduction in MPEG4 movie playback. This low-power embedded microprocessor, fabricated with 0.18-/spl mu/m CMOS embedded DRAM technology, enables high-performance operations such as audio and video applications. As process technology shrinks, this adaptive leakage power compensation scheme will become more important in realizing high-performance and low-power mobile consumer applications.

Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures

High-performance microprocessors are currently designed with the purpose of exploiting instruction level parallelism (ILP). The techniques used in their design and the aggressive scheduling techniques used to exploit this ILP tend to increase the register requirements of the loops. This paper reviews hardware and software techniques that alleviate the high register demands of aggressive scheduling heuristics on VLIW cores. From the software point of view, instruction scheduling can stretch lifetimes and reduce the register pressure. If more registers than those available in the architecture are required, some actions (such as the injection of spill code) have to be applied to reduce this pressure, at the expense of some performance degradation. From the hardware point of view, this degradation could be reduced if a high-capacity register file were included without causing a negative impact on the design of the processor (cycle time, area and power dissipation). Novel organizations for the register file based on clustering and hierarchical organization are necessary to meet the technology constraints. This paper proposes the used of a clustered organization and proposes an aggressive instruction scheduling technique that minimizes the negative effect of the limitations imposed by the register file organization.

Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models

Computer hardware components have changed significantly since the 1960s, 1970s, 1980s, and even since the early 1990s. Work concerning Rent's memos prior to the present paper has been based on a 1971 interpretation of two unpublished memoranda written in 1960 by E. F. Rent while working at IBM, even though today's computer components are significantly different from those in 1960 and 1971. However, because of the significant changes in the design and implementation of computer hardware components since 1960 and 1971, a new interpretation of Rent's memos is needed for today's components. We have obtained copies of Rent's two memos. In these memos, Rent describes the method that he used to obtain an empirical relationship between properties of the computer hardware components of the IBM 1401 and the IBM 1410 computers. We have studied these memos carefully in order to understand Rent's original intent. Based on our careful reading of these two memos, the personal knowledge of one of us with the 1401 and 1410 computers, and our experience designing ultralarge-scale integrated (ULSI) circuits for high-performance microprocessors, we have derived an historically equivalent interpretation of Rent's memos suitable for today's computer components. The purpose of this paper is to present a new interpretation of the memos and to present an application to wirelength distributions of real ULSI circuitry. In this paper, we will: 1) describe the contents of the memos and Rent's method; 2) provide an historically-equivalent interpretation of Rent's memos for today's computer components; and 3) apply this new interpretation to real ULSI control logic circuitry in the 1.3-GHz IBM POWER4 microprocessor. In this paper, we will show that this new interpretation of the two memos provides improved wirelength distribution models with better qualitative agreement with measurements and more accurate estimates of wirelength distributions and wirelength requirements for real ULSI designs compared with prior methods.

Reducing the soft-error rate of a high-performance microprocessor

Single-bit upsets from transient faults have emerged as a key challenge in microprocessor design. Soft errors will be an increasing burden for microprocessor designers as the number of on-chip transistors continues to grow exponentially. Unlike traditional approaches, which focus on detecting and recovering from faults, this article introduces techniques to reduce the probability that a fault will cause a declared error. The first approach reduces the time instructions sit in vulnerable storage structures. The second avoids declaring errors on benign faults. Applying these techniques to a microprocessor instruction queue significantly reduces its error rate with only minor performance degradation

Assessment of on-chip wire-length distribution models

Ultralarge-scale integrated (ULSI) chip design data is needed for an assessment of existing on-chip wirelength distribution models. Data extracted from modern chips such as high-performance microprocessors provide information about actual wire length requirements in ULSI chip designs. These requirements are compared with wirelength estimates obtained by evaluating existing models as functions of Rent's parameters that are extracted from the designs. This brief assesses the extent to which existing models estimate wirelength requirements in 100 ASIC-like control logic designs in the 1.3-GHz POWER4 microprocessor. For each design, physical design characteristics and wirelength requirements are measured and compared with model estimates. Lack of agreement between the data and models is observed for most designs, and possible reasons for the lack of agreement are discussed.

Sub-50 nm gate length SOI transistor development for high performance microprocessors

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI.

Timing Vulnerability Factors of Sequentials

Single-event upsets (SEU) from particle strikes have become a key challenge in microprocessor design. Modern superpipelined microprocessors typically contain many thousands of sequentials whose soft-error rate (SER) cannot be neglected any more. An accurate assessment of the SER of sequentials is therefore crucial. This work describes a method for computing timing vulnerability factors (TVFs) of sequentials. Our methology captures the impact of the circuit environment which sequentials are typically placed in. Further, upsets occurring in local clock nodes have been accounted for. Results are presented for master-slave type flip flops and for flow-through latches of a high-performance microprocessor. Our investigations demonstrate that TVFs are a strong function of the propagation delay of the combinational logic and typically vary between /spl sim/0% and 50%. For high-performance microprocessors, we predict average TVF values of the order of 20%-30%. Further, we expect TVFs to be largely technology independent for the same design.

Speeding Up Architectural Simulations for High-Performance Processors

Designing a high-performance microprocessor is extremely time-consuming, taking at least several years. In this article, the authors discuss these issues and propose a solution for each of them. As such, they present a new simulation methodology for designing high-performance microprocessors by combining several recently proposed techniques, such as statistical simulation, representative workload design, trace sampling, and reduced input sets. The major contribution of this study is to present a holistic view on speeding up the architectural design phase in which the above-mentioned techniques are integrated in one single architectural design framework. In this methodology, the authors first identify a region of interest in the huge design space through statistical simulation. As such, the authors conclude that this methodology can reduce the total simulation time considerably. In addition to presenting this new architectural modeling and simulation approach, a survey of related work of this fast-growing research field is presented.

Statistical Clock Skew Analysis Considering Intradie-Process Variations

With shrinking cycle times, clock skew has become an increasingly difficult and important problem for high performance designs. Traditionally, clock skew has been analyzed using case-files which cannot model intradie-process variations and hence result in a very optimistic skew analysis. In this paper, we present a statistical skew analysis method to model intradie process variations. We first present a formal model of the statistical clock-skew problem and then propose an algorithm based on propagation of joint probability density functions in a bottom-up fashion in a clock tree. The analysis accounts for topological correlations between path delays and has linear runtime with the size of the clock tree. The proposed method was tested on several large clock-tree circuits, including a clock tree from a large industrial high-performance microprocessor. The results are compared with Monte Carlo simulation for accuracy comparison and demonstrate the need for statistical analysis of clock skew.

Characterization of soft errors caused by single event upsets in CMOS processes

Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

Exploiting Resonant Behavior to Reduce Inductive Noise

Inductive noise in high-performance microprocessors is a reliabilityissue caused by variations in processor current (di/dt)which are converted to supply-voltage glitches by impedances inthe power-supply network. Inductive noise has been addressed byusing decoupling capacitors to maintain low impedance in thepower supply over a wide range of frequencies. However, evenwell-designed power supplies exhibit (a few) peaks of high impedanceat resonant frequencies caused by RLC resonant loops. Previousarchitectural proposals adjust current variations bycontrolling instruction fetch and issue, trading off performanceand energy for noise reduction. However, the proposals do notconsider some conceptual issues and have implementation challenges.The issues include requiring fast response, responding tovariations that do not threaten the noise margins, or respondingto variations only at the resonant frequency while the range ofhigh impedance extends to a resonance band around the resonantfrequency. While previous schemes reduce the magnitude of variations,our proposal, called resonance tuning, changes the frequencyof current variations away from the resonance band to anon-resonant frequency to be absorbed by the power supply.Because inductive noise is a resonance problem, resonance tuningreacts only to repeated variations in the resonance band, andnot to isolated variations. Reacting after a few repetitions allowsmore time for the response and reduces unnecessary responses,decreasing performance and energy loss.

Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor

Transient faults due to neutron and alpha particle strikes posea significant obstacle to increasing processor transistor counts infuture technologies. Although fault rates of individual transistorsmay not rise significantly, incorporating more transistors into adevice makes that device more likely to encounter a fault. Hence,maintaining processor error rates at acceptable levels will requireincreasing design effort.This paper proposes two simple approaches to reduce errorrates and evaluates their application to a microprocessor instructionqueue. The first technique reduces the time instructions sit invulnerable storage structures by selectively squashing instructionswhen long delays are encountered. A fault is less likely to cause anerror if the structure it affects does not contain valid instructions.We introduce a new metric, MITF (Mean Instructions To Failure),to capture the trade-off between performance and reliability introducedby this approach.The second technique addresses false detected errors. In theabsence of a fault detection mechanism, such errors would nothave affected the final outcome of a program. For example, a faultaffecting the result of a dynamically dead instruction would notchange the final program output, but could still be flagged by thehardware as an error. To avoid signalling such false errors, wemodify a pipeline's error detection logic to mark affected instructionsand data as possibly incorrect rather than immediately signalingan error. Then, we signal an error only if we determine laterthat the possibly incorrect value could have affected the program'soutput.

Chip-level microarchitecture trends

One year ago, in introducing IEEE Micro’s Hot Chips 14 special issue, I pointed out that features such as low power, reliability, security, and fault tolerance delivered to the customer at affordable cost might well serve as differentiating indices to the multidimensional entity called “system performance.” A year later, I cannot but overemphasize the emerging reality of that expectation. If anything, the focus on power dissipation as a primary design constraint has sharpened, with especially intense concerns about the static (leakage) component of power in future technologies. The basic uncertainty and variance of technology-related device and interconnect parameters (both across and within individually fabricated chips) that experts envisage are causing a major rethinking of the design stack (from high-level microarchitecture to physical design and layout). In addition, there are major implications in terms of design tool support for future, technology-aware microprocessor development. This year, the Hot Chips 15 special issue is guest edited by Michael Flynn and Pradeep Dubey. Their guest editors’ introduction covers the articles selected for publication in IEEE Micro. One of the trends in high-performance microprocessor chips is the increased level of on-chip integration that the technology has made available. IBM’s Power4 had previously started the trend of multicore designs with a dual-core chip multiprocessor offering. This issue of IEEE Micro includes an article on the follow-on chip called Power5, still a dual-core solution, but with each core supporting two independent program threads for a total of four concurrently executing threads per chip. Recent announcements by other vendors depict a similar trend, with an increasing emphasis on enhancing chip-level throughput through multiple cores and threads. In these future designs, each core or thread may not necessarily aim at delivering the highest frequency or performance that is achievable for the given technology. The power “wall” is definitely a factor that could accelerate this trend, since single-core frequencies might not scale up to meet prior trends. On the other hand, the chip-level power and area budgets (especially pertaining to leakage) place a natural limit on the number of cores for a given level of core complexity. This leads to some interesting power-performance tradeoffs that would balance single-thread performance against targets for chip-level throughput, working within a given power and cost budget. Yield and reliability aspects of the design equation (in an era of technological uncertainties) make the future space of design choices even more interesting! Of course, in some markets, singlethread performance might remain the primary driver of chip-level microarchitecture design. Here, to meet performance targets at affordable cost, cooling and packaging technologies must improve sufficiently to meet the challenge. I hope you enjoy reading the leadingedge articles in this special issue. They capture some of the latest advances, trends, and challenges in microprocessor design.

Modeling, Analysis and Design of Resonant Free Power Distribution Network for Modern Microprocessor Systems

This paper presents design-oriented analysis of the power distribution network (PDN) for high performance microprocessor systems to realize the resonant free, close to flat output impedance magnitude over a wide frequency range. Based on the frequency domain analysis, closed form design equations and parametric curves relating the system parameters are derived. A systematic method of estimating the optimum parameters of the decoupling capacitors used in a single or multistage PDN is described to realize the output impedance of specified magnitude for the noise-free, and critically damped voltage at the microprocessor core. The design examples and simulation results are discussed to demonstrate the application of the design equations and parametric curves.

B209 磁気センサ信号の可視化とその応用

In recent years, wide spreading use of microprocessors changes various apparatus as well as instruments into the smart functional products, dramatically. Even if the most high performance microprocessors and high speed memory is exploited; it is essential to exploit the high performance sensors which give original information of the computer instructions.High sensibility, toughness to the mechanical and environmental conditions such as stress, temperature and humidity are required to any types of sensors.Magnetic sensor is classified into two major categories. One is the semiconductor type, e.g. Hall sensor, and the other is sensing or picking up coil type. As is well known fact any types of semiconductor elements are greatly dominated by environmental temperature, and also depended on the mechanical stress. On the other side, sensing or picking up coil type magnetic sensor has reasonable tough properties to the mechanical and environmental conditions, even though they do not have high sensibility.In the present paper, we propose two types of magnetic sensors in order to sense the metallic materials. Our magnetic sensors belong to the sensing or picking up coil type, and are further classified into active and passive types. Proto type of these sensors is exploited and initial experiment is carried out.

The limits of semiconductor technology and oncoming challenges in computer micro architectures and architectures

In the last three decades the world of computers and especially that of microprocessors has been advanced at exponential rates in both productivity and performance. The integrated circuit industry has followed a steady path of constantly shrinking devices geometries and increased functionality that larger chips provide. The technology that enabled this exponential growth is a combination of advancements in process technology, micro architecture architecture and design and development tools. Together, these performances and functionality improvements have resulted in a history of new technology generations every two to three years, commonly referred to as-Moore Law. Each new generation has approximately doubled logic circuit density and increased performance by about 40%. This paper overviews some of the micro architectural techniques that are typical for contemporary high-performance microprocessors. The techniques are classified into those that increase the concurrency in instruction processing, while maintaining the appearance of sequential processing (pipelining, super-scalar execution out-of-order execution, etc), and those that exploit program behavior (memories hierarchies, branch predictors, trace caches, etc). In addition the paper also discusses micro architectural techniques likely to be used in the near future such as micro architectures with multiple sequencers and thread-level speculation, and micro architectural techniques intended for minimization of power consumption.

A methodology for optimal repeater insertion in pipelined interconnects

For many years, CMOS-process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reached a point where it takes several clock cycles for global signals to traverse a complex digital system such as a modern microprocessor. Thus, interconnect latency must be taken into account as a new design parameter in future synthesis and optimization tools at the architectural, as well as synthesis, level. To this purpose, this paper proposes a new latency-aware technique for the performance-driven concurrent insertion of flip-flops and repeaters in very large scale integration circuits, also taking clock skew into account. Pipelined interconnects are optimally designed for minimum latency or to meet latency constraints at the receivers. Given its generality, our methodology can be used to extend many existing techniques to the broader case of pipelined interconnects. An experimental scaling study showing overwhelming evidence of an exponential increase in the number of clocked repeaters every process generation, for high-performance microprocessors, as well as high-end application specific integrated circuits, is also presented. Such an increase indicates a radical change in current design methodologies to cope with this new emerging problem.

Coupled electro-thermal modeling and optimization of clock networks

In this paper a coupled electro-thermal model is used for the optimal design of the clock distribution tree of a high performance microprocessor. Such approach allows simultaneously to take into account both thermal and electrical constraints. In particular timing issues such as clock delay from the root of the tree to the leaves and skew between the leaves are optimized by a suitable wire and buffer sizing. At the same time the lifetime constraints of clock wires that are affected by the electromigration, enhanced by the high temperature reached in interconnects due to the Joule self-heating, are checked and respected.

Wearable computers: a new paradigm in computer systems and their applications

THE convergence of a variety of technologies makes possible an entirely new way of using information processing. Continued advances in semiconductor technology produce high performance microprocessors requiring less power and less space. Decades of research in computer science have provided the technology for hands-free computing using speech and gesturing for input. Miniature heads-up displays weighing less than a few ounces have been introduced. Combined with mobile communication technology, it is possible for users to access information anywhere and anytime. Body-worn computers providing hands-free operation offer compelling advantages in many applications. Wearable computers deal in information rather than programs, becoming tools in the user’s environment much like a pencil or a reference book. The wearable computer provides portable access to information. Furthermore, the information can be automatically accumulated by the system as the user interacts with and modifies the environment, thereby eliminating the costly and errorprone process of information acquisition. Much as personal computers allow accountants and bookkeepers to merge their information space with their workspace (i.e., a sheet of paper), wearable computers allow mobile processing and the superposition of information on the users workspace. When combined with pervasive computing, wearable computers will provide access to the right information at the right place and at the right time. Distractions are even more of a problem when they occur in mobile environments than desktop environments since the user is often preoccupied with walking, driving, or other real-world interactions. A pervasive computing environment that minimizes distraction has to be context aware. Context-aware computing describes the situation where a mobile computer is aware of its user’s state and surroundings and modifies its behavior based on this information. A user’s context can be quite rich, consisting of attributes such as physical location, physiological state (such as body temperature, heart rate, and skin resistance), emotional state (such as angry, distraught, or calm), personal history, daily behavioral patterns, etc. If a human assistant were given such context, he or she would make decisions in a proactive fashion, anticipating user needs. In making these decisions, the assistant would typically not disturb the user at inopportune moments except in an emergency. The goal is to enable mobile computers to play an analogous role, exploiting context information to significantly reduce demands on human attention. Combined with inferences about users’ intentions, context-aware computing would allow improvement in user-perceived network and application performance and reliability. Context-aware intelligent agents can deliver relevant information when a user needs that information. These data make possible many exciting new applications, such as augmented reality, context aware collaboration, wearable assisted living, augmented manufacturing, and maintenance. Wearable computing brings the power of a pervasive computing environment to a person by placing computing and sensory resources on the user in an unobtrusive way. These computers can be specialized and modular, like items of clothing. Unlike laptops or handheld computers, wearable computers offer many new models to interact beyond keyboards and touch screens, in a natural, intuitive way, such as sound and tactile feedback. Also, wearables can be easily reconfigured to meet specific needs of applications. Every wearable computer system must be viewed from three different axes: the human, the computer, and the application. Within each of these axes there are difficult problems that must be solved and there are problems that arise from the fact that there are three axes. The human axis emphasizes wearability, which is defined as the interaction between the human body and the wearable object. Dynamic wearability includes the human body in motion. Design for wearability considers the physical shape of objects and their active relationship with the human form. Researchers explored history and cultures, including topics such as clothing, costumes, protective wearables, and carried devices. These studies of physiology, biomechanics, and movement were codified into guidelines for designing wearable systems. User comfort is a critical design consideration in many applications. New technologies such as smart textiles will significantly improve the functionality and ergonomics of wearable computers. The computer axis deals with the problems related to construction of a system with particular fabrics, size, power consumption, and user interface software. The application axis emphasizes mobile application design challenges and efficient mapping of problem solving capabilities to application requirements. Wearable computers have established their first foothold in several application domains, such as vehicle and aircraft maintenance and manufacturing, inspection procedures, augmented reality, context aware collaboration, language translation, etc. IEEE TRANSACTIONS ON COMPUTERS, VOL. 52, NO. 8, AUGUST 2003 977

A practical methodology for verifying pipelined microarchitectures

Complete formal verification has thus far never been achieved for a state-of-the-art, high-performance commercial microprocessor. However, this article presents a completion functions methodology, based on theorem proving, that has been applied successfully to a large variety of example pipelined architectures.