High-performance Microprocessors Research Articles

Optimal wiresizing for interconnects with multiple sources

In this paper, we study the optimal wiresizing problem for nets with multiple sources under the RC tree model and the Elmore delay model. We decompose the routing tree for a multisource net into the source subtree (SST) and a set of loading subtrees (LSTs), and show that the optimal wiresizing solution satisfies a number of interesting properties, including: LST separability, the LST monotone property, the SST local monotone property, and the dominance property. Furthermore, we study the optimal wiresizing problem using a variable segment-division rather than an a priori fixed segment-division as in all previous works and reveal the bundled refinement property. These properties lead to efficient algorithms to compute the optimal solutions. We have tested our algorithm on nets extracted from the multilayer layout for a high-performance Intel microprocessor. Accurate SPICE simulation shows that our methods reduce the average delay by up to 23.5% and the maximum delay by up to 37.8%, respectively, for the submicron CMOS technology when compared to the minimal wire width solution. In addition, the algorithm based on the variable segment-division yields a speedup of over 100× time and does not lose any accuracy, when compared with the algorithm based on the a priori fixed segment-division.

Don't use the page number, but a pointer to it

Most newly announced high performance microprocessors support 64-bit virtual addresses and the width of physical addresses is also growing. As a result, the size of the address tags in the L1 cache is increasing. The impact of on chip area is particularly dramatic when small block sizes are used. At the same time, the performance of high performance microprocessors depends more and more on the accuracy of branch prediction and for reasons similar to those in the case of caches the size of the Branch Target Buffer is also increasing linearly with the address width.In this paper, we apply the simple principle stated in the title for limiting the tag size of on-chip caches. In the resulting indirect-tagged cache, the duplication of the page number in processors (in TLB and in cache tags) is removed. The tag check is then simplified and the tag cost does not depend on the address width. Applying the same principle to Branch Target Buffers, we propose the Reduced Branch Target Buffer. The storage size in a Reduced Branch Target Buffer does not depend on the address width and is dramatically smaller than the size of the conventional implementation of a Branch Target Buffer.

A transputer-based measuring system for decentralized signal processing, applied to two-phase flow

An innovative concept for decentralized processing of the signals of multiple sensors is presented. The basic idea is to connect every sensor via an analog-to-digital converter with a high-performance microprocessor, a transputer, that exclusively collects and processes its signal. The transputers are linked to a powerful network. Exemplarily, a measuring system based on this concept was used for the determination of local parameters of liquid–gas two-phase flows (e.g., local void fraction and bubble frequency). Up to six fiber-optical probes were utilized simultaneously to demonstrate the efficiency of the system. The signal processing under that special application may include on-line evaluation of flow parameters and on-line correction of errors of measurement due to sensor-induced effects. The concept of the new system, however, is basically independent of the number and type of sensors, as well as of the method of signal processing. The transputer-based measuring system thus provides a flexible, efficient tool for applications in which great amounts of data have to be evaluated or manipulated quickly.

Modeling and characterization of long on-chip interconnections for high-performance microprocessors

Long on-chip interconnections with dimensions larger than the minimum ground rules are rigorously analyzed and experimentally characterized for the first time. A test vehicle has been built and characterized with representative wiring found in high-performance CMOS microprocessor chips (line lengths of 0.8–1.6 cm, and line widths of 0.9–4.8 µm using a five-metal-layer structure). The need for distributed RLC transmission-line representation is highlighted through measured and simulated results. By showing the problems encountered when using long, nonuniform on-chip transmission lines, guidelines are developed to take advantage of the lower-resistance interconnections for use in high-speed, cycle-determining paths. Such guidelines are given both for current and optimized wiring practices and for cross-sectional structures.

VLSI on-chip interconnection performance simulations and measurements

We examine electrical performance issues associated with advanced VLSI semiconductor on-chip interconnections or “interconnects.” Performance can be affected by wiring geometry, materials, and processing details, as well as by processor-level needs. Simulations and measurements are used to study details of interconnect and insulator electrical properties, pulse propagation, and CPU cycle-time estimation, with particular attention to potential advantages of advanced materials and processes for wiring of high-performance CMOS microprocessors. Detailed performance improvements are presented for migration to copper wiring, low-ε dielectrics, and scaled-up interconnects on the final levels for long-line signal propagation.

Critical paths in circuits with level-sensitive latches

This paper extends the classical notion of critical paths in combinational circuits to the case of synchronous circuits that use level-sensitive latches. Critical paths in such circuits arise from setup, hold, and cyclic constraints on the data signals at the inputs of each latch and may extend through one or more latches. Two approaches are presented for identifying these critical paths and verifying their timing. The first implicitly checks all paths using a relaxation-based solution procedure. Results of this procedure are used to calculate slack values, which in turn identify satisfied and violated critical paths. The second approach is based on a constructive algorithm which generates all the critical paths in a circuit and then verifies that their timing constraints are satisfied. Algorithms are evaluated and compared using circuits from the ISCAS89 sequential benchmark suite and the Michigan High Performance Microprocessor Project.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Architecture validation for processors

Modem, high performance microprocessors are extremely complex machines which require substantial validation effort to ensure functional correctness prior to tapeout. Generating the corner cases to test these designs is a mostly manual process, where completion is hard to judge. Experience shows that the errors that are caught late in the design, many post-silicon, are interactions between different components in very improbable corner case situations. In this paper we present a technique that targets such error-causing interactions by automatically generat- ing test vectors that will cause the processor to exercise all transitions of the control logic in simulation. We use techniques from formal verification to derive transition tours of a fully enumerated state graph of the control logic of the processor. Our system works from a Verilog description of the original machine and is currently being used to validate an embedded dual-issue processor in the node controller of the Stanford FLASH Multiprocessor. Modeling the processor control results in 200K states and an 8M instruction trace to check all transitions of control arcs.

Future directions in microprocessor technology

The application trends and key design tradeoffs involved in the design of high performance microprocessors are discussed. In particular the growing importance of improved human interface technology and the need for high-performance, highly-connected systems combined with the need to continue to drive costs lower make design choices very difficult. Technical innovation in the areas of high bandwidth processor-memory interfaces, low-cost multiprocessors and software compatibility are needed in order to continue move forward.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors

A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 /spl mu/m CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4/spl times/ the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

6×86: the Cyrix solution to executing ×86 binaries on a high performance microprocessor

With the 6/spl times/86 microprocessor, Cyrix's design team demands optimum functionality and performance at an acceptable cost. Cyrix maintains that the way to get high performance is to keep larger units of processing together and to incorporate as much concurrency of execution as possible. To do the former, the microprocessor attempts to keep together all parts of an /spl times/86 instruction as it passes through its seven processing steps. To do the latter, it attempts to initiate the processing of two /spl times/86 instructions each cycle, and pipelines the processing of each instruction in seven stages. Most of this paper deals with issues involving keeping these seven stages of the two pipelines busy so the microprocessor can attempt to approach the twofold increase in performance that is made possible by the underlying structure.

On the upper bound of scheduling instructions on pipelined processors with delay

Abstract Several high performance microprocessor systems have been developed in recent years. Other than the fact that the system clocks were pushed to a higher rate than before, these systems were improved throughout by issuing more than one instruction within a cycle. Due to their increasingly complex pipeline structures as well as employment of multiple functional units, object codes of these systems are in general required to be reorganized in order to keep functional units busy and to avoid pipeline interlocks. Success of such a system design hence depends on not only how many hardware resources it provides, but primarily how efficiently these resources can be utilized. In this paper we analyze the worst case of applying a greedy method to schedule a set of instructions on m pipelined processors or functional units. Each instruction under discussion here will incur a delay of at most z cycles after it is issued to execute. The ultimate criterion is to minimize the completion time of the last completed instruction. The problem is NP‐hard. Let wg be the length of an arbitrary greedy schedule on m processors, and w0 be the length of an optimal schedule on m’ processors. We prove that wg/w0 ≤ (1+m'/m — 1/((z+1)m)). The results of this research can serve as the basis for superscalar instruction scheduling as well as some other related fields, such as superscalar architecture designs.

A cost-effective RISC/DSP microprocessor for embedded systems

Applications in telecommunications or multimedia require a new generation of fast and flexible microprocessors. We present a 32-bit RISC microprocessor with extended functionality for digital signal processing that reduces overall system cost. Due to its optimized design with just 210,000 transistors, this low-cost, medium- to high-performance microprocessor is well suited for a wide range of embedded system applications. >

A multiprocessor architecture combining fine-grained and coarse-grained parallelism strategies

A wide variety of computer architectures have been proposed that attempt to exploit parallelism at different granularities. For example, pipelined processors and multiple instruction issue processors exploit the fine-grained parallelism available at the machine instruction level, while shared memory multiprocessors exploit the coarse-grained parallelism available at the loop level. Using a register-transfer level simulation methodology, this paper examines the performance of a multiprocessor architecture that combines both coarse-grained and fine-grained parallelism strategies to minimize the execution time of a single application program. These simulations indicate that the best system performance is obtained by using a mix of fine-grained and coarse-grained parallelism in which any number of processors can be used, but each processor should be pipelined to a degree of 2 to 4, or each should be capable of issuing from 2 to 4 instructions per cycle. These results suggest that current high-performance microprocessors, which typically can have 2 to 4 instructions simultaneously executing, may provide excellent components with which to construct a multiprocessor system.

Microprocessors: From Desktops to Supercomputers

Continuing improvements in integrated circuit technology and computer architecture have driven microprocessors to performance levels that rival those of supercomputers-at a fraction of the price. The use of sophisticated memory hierarchies enables microprocessor-based machines to have very large memories built from commodity dynamic random access memory while retaining the high bandwidth and low access time needed in a high-performance machine. Parallel processors composed of these high-performance microprocessors are becoming the supercomputing technology of choice for scientific and engineering applications. The challenges for these new supercomputers have been in developing multiprocessor architectures that are easy to program and that deliver high performance without extraordinary programming efforts by users. Recent progress in multiprocessor architecture has led to ways to meet these challenges.

Controller design for a sensorless permanent-magnet synchronous drive system

The paper investigates the design of H2 and H∞ controllers for a permanent-magnet synchronous motor drive system without using shaft-position sensor, and presents the field-weakening control algorithm of the drive system. Robust PI, H2 and H∞ control techniques are applied to design servo controllers. A fully digital control system under the vector control framework is constructed for experimentally verifying controller performance. The theoretical development is validated by experimental work. The paper provides a new approach for designing sensorless AC drives using currently available high performance microprocessors.

ACHIEVING HIGH PERFORMANCE ON THE i860™ MICROPROCESSOR WITH NASPACK SUBROUTINES

The i860™ is a high performance microprocessor used in the Intel Touchstone project. This paper proposes a paradigm for programming the i860™ that is modelled on the vector instructions of the Cray computers. A collection of Fortran callable assembler subroutines (Naspack routines) were written that mimic the concurrent vector instructions of the Cray with cache taking the place of vector registers. Using the Naspack subroutines on an adisolve, we obtained a speedup of 3.9 for a 128 by 128 system over compiled code.

USA report: Next generation high performance American processors

In the field of general purpose, next-generation 32-bit high performance microprocessors, the “hot engines” in America these days are primarily those that are being driven by the systems companies. It's no longer a question of a company like Motorola saying, “we're going to do this new chip and this is how fast it's going to be,” for that idea has come to an end. With the exception of Intel, the company that has had the PC marketplace locked up for some time now, in terms of its name and functionality, the rest of the world is being driven by the systems companies, especially the workstation people.

Multilevel optimization in the design of a high-performance GaAs microcomputer

Multilevel optimization in the design of an instruction cache for a high-performance GaAs microprocessor is discussed. The performance of the system is maximized by concurrently considering the interrelationships of (1) the time of flight of signals across the multichip module on which the processor and cache chips are mounted, (2) the clocking scheme that synchronizes these signals, and (3) the size of the cache. These three design issues are normally considered independently because they arise in different abstraction levels. Design automation tools developed to facilitate this multilevel optimization are described. This process, applied to various subsystems, has been used to gain substantial performance improvement in the GaAs microcomputer.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Implementing a cache for a high-performance GaAs microprocessor

Implementing a cache for a high-performance GaAs microprocessor

Paradigm: a highly scalable shared-memory multicomputer architecture

Paradigm (parallel distributed global memory), a shared-memory multicomputer architecture that is being developed to show that one can build a large-scale machine using high-performance microprocessors, is discussed. The Paradigm architecture allows a parallel application program to execute any of its tasks on any processor in the machine, with all the tasks in a single address space. The focus is on novel design techniques that support scalability. The key performance issues are identified, and some results to date from this work and experience with the VMP architecture design on which it is based are summarized.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>