The limits of semiconductor technology and oncoming challenges in computer micro architectures and architectures

Abstract

In the last three decades the world of computers and especially that of microprocessors has been advanced at exponential rates in both productivity and performance. The integrated circuit industry has followed a steady path of constantly shrinking devices geometries and increased functionality that larger chips provide. The technology that enabled this exponential growth is a combination of advancements in process technology, micro architecture architecture and design and development tools. Together, these performances and functionality improvements have resulted in a history of new technology generations every two to three years, commonly referred to as-Moore Law. Each new generation has approximately doubled logic circuit density and increased performance by about 40%. This paper overviews some of the micro architectural techniques that are typical for contemporary high-performance microprocessors. The techniques are classified into those that increase the concurrency in instruction processing, while maintaining the appearance of sequential processing (pipelining, super-scalar execution out-of-order execution, etc), and those that exploit program behavior (memories hierarchies, branch predictors, trace caches, etc). In addition the paper also discusses micro architectural techniques likely to be used in the near future such as micro architectures with multiple sequencers and thread-level speculation, and micro architectural techniques intended for minimization of power consumption.