High-performance Digital Systems Research Articles

A high-performance digital system for electrical capacitance tomography

This paper describes a recently developed digital-based data acquisition system for electrical capacitance tomography (ECT). The system consists of high-capacity field-programmable gate arrays (FPGA) and fast data conversion circuits together with a specific signal processing method. In this system, digital phase-sensitive demodulation is implemented. A specific data acquisition scheme is employed to deal with residual charges in each measurement, resulting in a high signal-to-noise ratio (SNR) at high excitation frequency. A high-speed USB interface is employed between the FPGA and a host PC. Software in Visual C++ has been developed to accomplish operational functions. Various tests were performed to evaluate the system, e.g. frame rate, SNR, noise level, linearity, and static and dynamic imaging. The SNR is 60.3 dB at 1542 frames s−1 for a 12-electrode sensor. The mean absolute error between the measured capacitance and the linear fit value is 1.6 fF. The standard deviation of the measurements is in the order of 0.1 fF. The dynamic imaging test demonstrates the advantages of high temporal resolution of the system. The experimental results indicate that the digital signal processing devices can be used to construct a high-performance ECT system.

Formal Analysis of Hybrid Prefix/Carry-Select Arithmetic Systems

Arithmetic circuits play an important role in high-performance digital systems. The paper considers a generic architecture of hybrid prefix/carry-select arithmetic systems. A novel proof methodology is proposed to model and verify hybrid addition systems. Algebraic structures and first-order recursive equations are harnessed in proof derivations. Case studies on several typical classes of hybrid prefix/carry-select adders and special cases with pseudo-carries such as Ling's carry demonstrate the effectiveness of the proposed approach.

I/Q Imbalance Compensation Using a Nonlinear Modeling Approach

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In-phase/quadrature (I/Q) imbalance is one of the main sources of distortion in RF modulators. In this paper, a dual-input nonlinear model based on a real-valued Volterra series is proposed for compensation of the nonlinear frequency-dependent I/Q imbalance. First, different sources of distortion are identified from experimental measurements, then a dual-input nonlinear I/Q imbalance model is developed. Further, the inverse model is used for I/Q imbalance compensation. Finally, the performance of the I/Q imbalance compensator is evaluated with both simulations and experiments. In comparison with previously published results, the proposed I/Q imbalance compensator shows significantly improved performance. Thus, we prove that a complete nonlinear I/Q imbalance compensation can minimize the effects of the RF modulator in high-performance digital communication systems. </para>

Time Management for Low-Power Design of Digital Systems

The implementation of complex functionality in low-power (LP) nano-CMOS technologies must be carried out in the presence of enhanced susceptibility to PVT (Process, power supply Voltage and Temperature) variations. VT variations are environmental or operation-dependent parametric disturbances. Power constraints (in normal and test mode) are critical, especially for high-performance digital systems. Both dynamic and leakage power induce variable (in time and space) thermal maps across the chip. PVT variations lead to timing variations. These should be accommodated without losing performance. Dynamic, on-line time management becomes necessary. The purpose of this paper is to present a VT-aware time management methodology which leads to improved PVT tolerance, without compromising performance or testability. First, the methodology is presented, highlighting its characteristics and limitations. Its underlying principle is to introduce additional tolerance to VT variations, by time borrowing, dynamically controlling the time of the clock edge trigger driving specific memory cells (referred to as critical memory cells, CME). VT variations are locally sensed, and dynamic delay insertion in the clock signal driving CME is performed, using Dynamic Delay Buffer (DDB) cells. Then, methodology automation, using the proprietary DyDA tool, is explained. The methodology is proved to be efficient, even in the presence of process variations. Finally, it is shown that VT tolerance insertion does not necessarily reduce delay fault detection, as multi-V DD or multi-frequency self-test can be used to recover detection capability.

A mesochronous pipelining scheme for high-performance digital systems

A novel mesochronous pipelining scheme is described in this paper. In this scheme, data and clock travel together. At any given time a pipeline stage could be operating on more than one data wave. The clock period in the proposed pipeline scheme is determined by the pipeline stage with largest difference between its minimum and maximum delays. This is a significant performance gain compared to conventional pipeline scheme where clock period is determined by the stage with the largest delay. A detailed analysis of the clock period constraints is provided to show the performance gains and Speedup of mesochronous pipelining over other pipelining schemes. Also, the number of pipeline stages and pipeline registers is small. The clock distribution scheme is simple in the mesochronous pipeline architecture. An 8 /spl times/ 8-bit carry-save adder multiplier has been implemented in mesochronous pipeline architecture using modest TSMC 180-nm (drawn length 200 nm) CMOS technology. The multiplier architecture and simulation results are described in detail in this paper. The pipelined multiplier is able to operate on a clock period of 350 ps (2.86 GHz). This is a Speedup of 1.7 times over conventional pipeline scheme, with fewer pipeline stages and pipeline registers.

A 2-Gb/s Optical Transceiver With Accelerated Bit-Error-Ratio Test Capability

Accelerated bit-error-ratio (BER) measurement techniques using specialized test equipment are widely used for rapidly verifying the low BER (<10/sup -12/) of high-performance optical links. However, once these links are deployed in the field, it takes days to weeks to complete such BER measurements using a conventional testing method. This paper describes an optical transceiver architecture with on-chip accelerated BER measurement mechanics that reduces "in the field" BER testing time to minutes. The approach described in this paper uses an integrated interference generator to degrade receiver performance and raise the BER to a range that allows a substantially reduced measurement time. Values of BER versus the amount of interference are then extrapolated to the point of zero artificial degradation for actual BER. A 0.5-/spl mu/m complementary metal-oxide-semiconductor, 2-Gb/s, four-channel optical transceiver chip was designed, fabricated, and tested to serve as a vehicle for verifying the concept. The experimental results show excellent agreement between the extrapolated and actual BER values. The architecture described here points to a practical built-in self-test capability for optical links within high-performance digital systems, specifically in board- and backplane-level interconnections.

Two's complement computation sharing multiplier and its applications to high performance DFE

We present a novel computation sharing multiplier architecture for two's complement numbers that leads to high performance digital signal processing systems with low power consumption. The computation sharing multiplier targets the reduction of power consumption by removing redundant computations within system by computation reuse. Use of computation sharing multiplier leads to high-performance finite impulse response (FIR) filtering operation by reusing optimal precomputations. The proposed computation sharing multiplier can be applicable to adaptive and nonadaptive FIR filter implementation. A decision feedback equalizer (DFE) was implemented based on the computation sharing multiplier in a 0.25-/spl mu/ technology as an example of an adaptive filter. The performance and power consumption of the DFE using a computation sharing multiplier is compared with that of DFEs using a Wallace-tree and a Booth-encoded multiplier. The DFE implemented with the computation sharing multiplier shows improvement in performance over the DFE using a Wallace-tree multiplier, reducing the power consumption significantly.

High-performance digital control system for scanning tunnelling microscopy

This paper describes a flexible, completely digital, scanning tunnelling microscopedeveloped around a fixed-point (TMS320C542) digital signal processor. Duringthe development special attention has been paid to the cost of the instrument,without limiting its performance, and in some regards enhancing it. Theinstrument has been developed and tested in the air, at room temperature, andatomic resolution has been achieved. Its software provides a maximum ofsupport to the user. The tip approach is completely automated. The controlparameters can be adjusted based on an on-line identification and off-line (insimulation) optimization. This technique is completely integrated to the controlsoftware. It greatly simplifies the parameter optimization, and completelyeliminates the risk of collision between the tip and the sample during theoptimization. The scanning of the image and control of the tunnellingcurrent are implemented in software by the DSP. This allows the preciseidentification and real-time compensation of the capacitive coupling between thescan tube electrodes and the current detector. The image analysis andprocessing software allows slope compensation, as well as the presentation ofdifferential image, two-dimensional FFT and three-dimensional image.

A New Joint Coding and Modulation Scheme for Channels with Clipping

Clarkson, I. V. L., and Collings, I. B., A New Joint Coding and Modulation Scheme for Channels with Clipping, Digital Signal Processing 12 (2002) 223–241 A major limitation in any high-performance digital communication system is the linearity region of the transmitting amplifier. Nonlinearities typically lead to signal clipping. Efficient communication in such conditions requires maintaining a low peak-to-average power ratio (PAR) in the transmitted signal while achieving a high throughput of data. Excessive PAR leads either to frequent clipping or to inadequate resolution in the analog-to-digital or digital-to-analog converters. Currently proposed signaling schemes for future generation wireless communications suffer from a high PAR. This paper presents a new signaling scheme for channels with clipping which achieves a PAR as low as 3. For a given linear range in the transmitter's digital-to-analog converter, this scheme achieves a lower bit-error rate than existing multicarrier schemes, owing to increased separation between constellation points. We present the theoretical basis for this new scheme, approximations for the expected bit-error rate, and simulation results.

Approaches to low-power implementations of DSP systems

Reduction of power consumption is significantly important for all high-performance digital VLSI systems. This paper reviews several approaches for low-power implementations of building blocks for digital subscriber line (DSL) systems. Low-power implementations of Reed-Solomon (RS) coders, fast Fourier transforms (FFTs), FIR filters, and equalizers, and reduction of power consumption by use of dual supply voltages are addressed. It is shown that use of separate Galois field functional units for multiply-accumulate and degree reduction can reduce the energy consumption of RS coders dramatically. A hybrid feedforward and feedback commutator scheme-based FFT is shown to require less area and full hardware utilization efficiency. Reduction of switching activity at one or both inputs of the multipliers is a key to reduction of power consumption in FIR filters and equalizers. The switching activity can be reduced by use of transpose structure and by time-multiplexing of an unfolded filter. A well established retiming approach can be generalized to find those noncritical gates which can be operated with lower supply voltages to reduce the overall system power consumption.

RF interconnect for multi-gbit/s board-level clock distribution

With clock distribution of over 1 GHz, problems associated with clock skew, power consumption, and timing jitter are becoming critical for determining the processing speed of high-performance digital systems, especially for multi-processor systems. Conventional digital clock distribution interconnection has a severe power consumption problem for GHz clock distribution because of the transmission line losses, as well as exhibiting difficult signal integrity problems due to clock skew, clerk jitter and signal reflection. To overcome conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, the optical clock distribution is found to be bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. In this paper, a multi-Gbit/s clock distribution scheme to minimize power consumption, skew, and jitter, based on RF interconnect technology, especially for the medium clock frequency region from 200 MHz to 10 GHz, and interconnection line lengths of from 10 cm to 3 m, is proposed. A quantitative comparison is made between the guided optical, the free-space optical, the conventional digital, and the proposed RF interconnections for board-level clock distribution relative to power consumption and speed. The proposed board-level clock distribution with 32-fan-outs has successfully demonstrated less than 22-ps skew and less than 3-ps jitter at 2 GHz. The estimated power consumption of the clock link for the proposed clock distribution has been shown to be about 320 mW. Furthermore, the proposed clock receiver using the RF clock distribution scheme has demonstrated less than 2-ps dead time and 3-ps skew time.

A Current-Mode Logic for Low-Voltage, High-Speed Mixed-Mode VLSI Circuits

A wired-AND current-mode logic (WCML) circuit is designed for high performance mixed analog and digital system designs on a common silicon substrate, using standard CMOS process. Current is used for digital information carrier in order to be able to reduce supply voltage, power consumption, digital switching noise and to increase operating frequency. The WCML circuit uses current-steering technique. It is composed of a simple current mirror with a current injector. Wired-AND connections cause the logic circuit to operate as a NAND logic gate which provides to implement any boolean function. High-speed is achieved by varying the injection current level even at low-voltage supply (<1.5 V) with low-power consumption.

A high-performance digital control system for TCV

The TCV hybrid analogue-digital plasma control system has been superseded by a high performance Digital Plasma Control System, DPCS, made possible by recent advances in off the shelf technology. We discuss the basic requirements for such a control system and present the design and specifications which were laid down. The nominal and final performances are presented and the complete design is given in detail. The integration of the new system into the current operation of the TCV tokamak is described. The procurement of this system has required close collaboration between the end-users and two commercial suppliers with one of the latter taking full responsibility for the system integration. The impact of this approach on the design and commissioning costs for the TCV project is presented. New possibilities offered by this new system are discussed, including possible work relevant to ITER plasma control development.

Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems

In this paper, a new high-speed circuit technique called differential cascode voltage switch with pass-gate (DCVSPG) logic tree is presented. The circuit technique is designed using a pass-gate logic tree in DCVSPG instead of the nMOS logic tree in the conventional DCVS circuit, which eliminates the floating node problem. By eliminating the floating node problem, the DCVSPG becomes a new type of ratioless circuit, and it also provides superior performance with less power dissipation and better silicon area tradeoff. The basic DCVSPG design technique, the methodology for optimization, and synthesis of the pass-gate logic tree are described. The standard cell library development taking advantage of the dual-rail outputs of DCVSPG gates is also discussed. The performance comparisons with other existing pass-gate circuit techniques [complimentary pass-transistor logic (CPL), double pass-transistor logic (DPL), and swing restored pass-transistor logic (SRPL)] are presented. For more robust design, the DCVSPG with inverter buffers is also the best choice. A Viterbi macro design using the DCVSPG circuit technique is demonstrated. The process that the design is based upon is a 0.5-/spl mu/m CMOS technology with 0.25-/spl mu/m effective channel length and five layers of metal. This macro can run up to 500 MHz at the nominal process condition. In comparison with other existing dynamic circuit techniques, the results also clearly show that the dynamic DCVSPG has the superior power-delay performance.

Stability of Synchronized States in One Dimensional Networks of Second Order PLLS

Synchronous distributed timing clocks are the basic building blocks in digital communication systems. Conventional systems mainly employ a tree-like network of cascaded timing clocks for synchronous clocking. On the other hand, decentralized synchronous networks of timing clocks, which have been proposed from a very early stage of the digital communication, are gaining attention in the consumer communication networks and also recently in large, high-performance digital systems (such as multiprocessors) clocking. In this paper, we present a theoretical study of synchronous networks of timing clocks consisting of locally connected second order phase-locked loops (PLLs). We find a close connection between the stability properties of the first and second order networks. The particular examples of one way and two way nearest neighbor coupling, with a lag-lead filter and a triangular phase detector (PD) are analyzed in detail. Both the synchronized in-phase solution and the wave-like "mode-lock" solution are examined. A criterion is found for the stability of the one-way coupled network while the two-way coupled network is found to be always stable.

155 Mb/s operation of a FET-SEED free-space switching network

The interconnection problems present in many high-performance digital systems may be alleviated through the use of surface normal optical interconnections using optoelectronic smart pixels. We present recent results of high-speed operation of a five-stage experimental free-space switching network using embedded control techniques for network control. The smart pixels consist of buffered GaAs FET logic with MQW SEED detectors and modulators. The system also incorporates external cavity lasers, bulk, micro, and diffractive optics, two-dimensional fiber bundles, and novel optomechanics. At 155 Mb/s, 77 of the 80 total pixels in the system and 31 of the 32 input fibers were functional. Two of the network paths have carried digital video at 105 Mb/s for over four months without readjustment. Error rate measurements on these paths have shown a short-term BER of 10/sup -10/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An Application of Digital Filtering in Electron Holography at Atomic Resolution

To reconstruct a wave from an off-axis image hologram by an ordinary method using the Fourier transform, the carrier fringes should be less than one third of the required resolution. We have proposed a new method which can be applied to crystal specimens even when the carrier frequency does not satisfy the above condition. Therefore, we are able to use a higher quality hologram taken at a lower magnification to reconstruct a wave. The proposed method is applied to a high resolution hologram of a magnesium oxide crystal by using a high performance digital image processing system based on a personal computer

A digital control system for scanning tunnelling microscopy and atomic force microscopy

The authors present a flexible, high performance digital feedback and scanning system for the control of both scanning tunnelling microscopy (STM) and atomic force microscopy (AFM) which they have shown is capable of taking atomically resolved images. The system is based on an AT&T DSP32C digital signal processor (DSP) which functions as a 'front-end' controller independently of the AT compatible host computer. A 'pseudo 18-bit' system is employed for the feedback loop which can control the Z-movement of the tip down to 0.003 nm whilst allowing a total excursion of up to 800 nm. The system samples at 60 kHz; this is equivalent to an analogue system with a bandwidth of about 20 kHz. Apart from the feedback algorithm, the hardware and software for both the STM and AFM operation are identical. An 'open architecture' philosophy allows the system to be reconfigured for different instruments.

Optical interconnections for digital systems

The replacement of electrical lines and connectors by free space or guided-wave optics in high-performance digital systems is discussed. Components for such systems are considered, and prototype systems are described. Optical interconnections with only a laser, two lenses, and a detector are possible and such a free-space board-to-board interconnection has been demonstrated at 1 Gb/s with an average power dissipation of only about 40 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

ANALYSIS AND MODELING OF INTERCONNECTS FOR HIGH-SPEED DIGITAL APPLICATIONS

Abstract The electromagnetic modeling of packages and interconnects plays a very important role in the design of high-speed digital circuits, and is most efficiently performed by using computer-aided design algorithms. In the past two decades, researchers in the electromagnetic and microwave areas have strived to extend the knowledge of interconnection properties. Their efforts have resulted in models and analytical methods without which the development of reliable design tools would be impossible. Packaging and interconnects nowadays represent a critical area for the design of high-performance digital systems, and the work of these contributors is invaluable. This paper exposes the state-of-the-art in packaging technology and reviews the important steps in the development of analytical models, numerical methods and simulation techniques for the design of high-speed interconnections.