High-performance Chip Research Articles

Optimization and Benefit Analysis of Intelligent Networked Vehicle Supply Chain Based on Stackelberg Algorithms

With the rapid development of intelligent technology, the construction of smart cities with the goal of creating a harmonious human life has become a new hot spot in the world. A new round of information technology revolution, represented by the Internet, big data, cloud computing, artificial intelligence (AI), and fifth-generation mobile communications (5G), is driving profound changes in the automotive industry. Smart vehicles (also known as intelligent connected vehicles) that integrate many high-tech technologies to provide safer, more convenient, and low-carbon comprehensive travel solutions have become an inevitable form of future vehicles. This paper constructs a three-level supply chain consisting of high-performance chip suppliers, smart car manufacturers, and retailers. On the basis of considering the level of product innovation and sales effort, Stackelberg game method is used to study the influence of each player in the supply chain on each parameter and the profit of each player under three scenarios: centralized decision making, nonsharing of innovation cost, and sharing of innovation cost. The results show that: when the level of sales effort has nothing to do with the level of innovation, the level of product innovation and the total profit of the supply chain increase with the improvement of the retailer’s sales ability; when the level of sales effort is related to the level of innovation, the level of product innovation under the cost-sharing decision model is greater than the case of no cost sharing, but the total profit of the supply chain is less than the case of no cost sharing.

PolyWorm: Leveraging Polymorphic Behavior to Implant Hardware Trojans

Owing to the various challenges looming over the integrated circuit (IC) supply chain for the sub-nm technology nodes, researchers are looking into emerging devices to design the next generation of high performance and low-power chips. The magnetoelectric spin-orbit (MESO) switch, developed by Intel™, is a front-runner in this search and is currently in a state of advanced experimental research. To ensure faster time-to-market and reap the existing supply chain’s benefits, it is envisioned that the upcoming MESO devices will be coupled and hybridized with the existing complementary metal-oxide-semiconductor (CMOS) industrial framework. However, adopting the existing CMOS framework and incorporating it’s outsourced supply chain increases exposure to various security threats such as design intellectual property (IP) piracy, overproduction of ICs, and insertion of hardware Trojans (HT) to leak information or cause denial-of-service. This article proposes and investigates a stealthy HT insertion technique, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PolyWorm</i> , leveraging the polymorphic capabilities of MESO gates in hybrid MESO-CMOS architectures. We evaluate the efficacy of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PolyWorm</i> on ITC-99 benchmarks and demonstrate two use-case scenarios, viz., corrupting the intended design functionality and leaking the secret key from a cryptographic core. We also present a low-footprint domain wall-based trigger for our polymorphic Trojan to evade structural and power-based testing.

Classical and quantum photonic sources based upon a nonlinear GaP/Si-superlattice micro-ring resonator

We present a theoretical investigation, based on the tight-binding Hamiltonian, of efficient second- and third-order nonlinear optical processes in the lattice-matched undoped (GaP)N/(Si2)M short-period superlattice that is waveguide-integrated in a microring resonator on an opto-electronic chip. The nonlinear superlattice structures are situated on the optically pumped input area of a heterogeneous “XOI” chip based on silicon. The spectra of χzzz(2)(2ω,ω,ω), χxzx(2)(2ω,ω,ω), χxxxx(3)(3ω,ω,ω,ω) and the Kerr refractive index (n2), have been simulated as a function of the number of the atomic monolayers for “non-relaxed” heterointerfaces; These nonlinearities are induced by transitions between valence and conduction bands. The large obtained values make the (GaP)N/(Si2)M short-period superlattice a good candidate for future high-performance XOI photonic integrated chips that may include Si3N4 or SiC or AlGaAs or Si. Near or at the 810-nm and 1550-nm wavelengths, we have made detailed calculations of the efficiency of second- and third-harmonic generation as well as the performances of entangled photon-pair quantum sources that are based upon spontaneous parametric down conversion and spontaneous four-wave mixing. The results indicate that the (GaP)N/(Si2)M short-period superlattice is competitive with present technologies and is practical for classical and quantum applications.

PACKAGE-ON-PACKAGE (POP) UNDERFILL PROCESS USING A MATERIAL DAM METHOD

Recent developments in the electronics industry have introduced a multi-stack ball grid array (BGA) to meet the growing consumer demand for both high-performance and smaller-sized chip packages. This study focused on the preliminary study of the Package-on-Package (PoP) underfill process using a material dam method. High viscosity type of underfill material is considered for the underfill process. In the current experimental work, L path-dispensing method was chosen due to its advantages, as reported in the previous work. The material dam method was used to prevent underfill from moving backwards and flowing out from the dispensing region. The material dam was built surrounding the PoP package. The effectiveness of the underfill process was analyzed based on the cycle time and lateral lapping, which are significant factors in material selection. The experimental results revealed that slow underfill flow may cause the quickly harden of material while the dispensing process is still running. This situation restricts the underfill flow and creates voids in the PoP package. The material dam method successfully enhanced the underfilling process for layers 3 and 4 stacked-package. This study is expected to provide the preliminary underfill process of stacking the PoP package and is useful as a reference for the engineer in the microelectronics industry.

On-Chip Waveguide Amplifiers for Multi-Band Optical Communications: A Review and Challenge

Erbium (Er)-doped fiber amplifier (EDFA) has achieved great success in modern optical communications for decades due to its outstanding gain performance in C-band. Nowadays, people are making efforts to make it monolithic integration due to the imperious demands from the advancement of high-performance and multi-function optoelectronic devices and chips. Except for the Er-doped waveguide amplifier, the other ion-doped on-chip waveguide amplifiers have also attracted much attention for multi-band optical communications, since they have own advantages in gain, bandwidth, selectivity of host materials, and integrability. Herein, we review the transmission characteristics of ion-doped on-chip waveguide amplifiers including gain and bandwidth, combining with the emission mechanisms and fabrication processes in applications of long-haul and short-reach optical communications. To facilitate the practical progress of the integrated waveguide amplifiers, from the perspective of gain medium, we also discuss the challenges and potential solutions for future technology roadmap. We expect that the bismuth (Bi)-doped waveguide amplifier would present impressive advantages in multi-band optical communications.

The micro-fabrication and performance analysis of non-magnetic heating chip for miniaturized SERF atomic magnetometer

The elevated temperature field is one of the fundamental conditions for the spin-exchange relaxation-free (SERF) regime, which can be accomplished by electric heating chip without introducing stray field. Therefore, a non-magnetic heating chip composed of double identical ring-structure layers with a silicon oxide insulating layer between them is carefully designed and fabricated with the material of nichrome alloy on a borosilicate glass substrate by Micro Electro-Mechanical Systems (MEMS) technology. What’s more, the influence of annealing treatment process on the microstructure of the heating chip is characterized and explicated utilizing modern surface science technique, including four-probe meter, X-ray diffraction (XRD) and atomic force microscope (AFM). Then, the integrated miniature single-beam SERF atomic magnetometer is developed based on the microfabricated heating chip. The temperature stability of heating chip is tested with the value less than ± 10 mK at 120 °C by the proportional integral derivative (PID) control program, and the magnetic current coefficient is determined of only 0.506 nT/mA by the spin resonance response of the SERF atomic magnetometer near the zero field. Finally, the developed SERF atomic magnetometer achieves a high measuring sensitivity of 70 fT/Hz1/2. These experimental results provide a new avenue for the wafer-level microfabrication of the high-performance non-magnetic heating chip. More importantly, the presented work paves the way towards chip-scale atomic magnetometers with high sensitivity and mm-scale spatial resolution in the applications of magnetic source imaging and magnetic anomaly detection.

Підвищення продуктивності фрезерування профільних пазів за рахунок удосконалення системи видалення стружки

Among the effective, but insufficiently used at this time, reserves for improving the system of forced chip removal include the significant energy potential of the lubricating and cooling technological agent, which is fed into the cutting zone to lubricate and cool the cutting tool. A reason for this situation is the lack of a coherent concept for improving the chip removal system, as well as the practical lack of knowledge of the laws of their working processes when exercising a forced effect on the separated chips precisely when processing profile grooves. The foregoing testifies to the relevance and importance for the mechanical engineering of Ukraine of the task of creating high-performance forced chip removal systems for profile slot milling operations based on the development of a theory of their functioning. Because of the research performed, an important task has been solved, which is to increase the productivity of milling profile slots by using a forced chip removal system with rational parameters. Developed technical solutions for the chip removal system, which provides an increase in the productivity of profile slot milling. A systematic representation of the process of forced chip removal during profile slot milling has been developed, which made it possible to identify the required number of mathematical models. Particular and integral mathematical models of the functioning of the main subsystems and modules of the forced chip removal system have been developed. A simulation of the process of forced removal of chips is carried out. Based on modeling, a technique has been developed for determining the rational parameters of the forced chip removal system when milling profile slots. Experimental studies have been conducted aimed at determining the effectiveness of the proposed technical solutions and confirming the adequacy of the developed mathematical models. The created chip removal system provides an increase in the productivity of milling profile slots by approximately 2 times while maintaining the quality of surfaces and increasing the durability of the cutting tool by at least 3 times due to the use of a forced chip removal system with rational parameters.

Design and test of shape memory alloy fins for self-adaptive liquid cooling device

• Self-adaptive cooling fins based on Shape Memory Alloys (SMA). • The set of conditions for proper operation are defined analytically. • The impact of an array of SMA fins on thermal resistance is experimentally studied. • Nearly constant wall temperature is achieved for varying heat flux scenarios. Thermal management complexity increases in high-performance chips, where the heat loads vary spatially and temporally, while liquid cooling systems are usually designed for most stringent stationary conditions. Several works developed heat transfer enhancement techniques to increase the cooling capacity of liquid cooled heat sinks, but pumping power is increased in a permanent way due to the addition of elements within the channels. Here, a liquid cooling self-adaptive heat sink that can efficiently adapt the distribution of its heat extraction capacity to time dependent and non-uniform heat load scenarios is proposed. Numerical design of the mesoscale cooling device with bimorph metal/SMA fins, definition of the fabrication and training procedure of the SMA fins to reach the desired behavior and experimental assessment is presented. The capacity of the self-adaptive fins to locally boost the heat transfer is numerically and experimentally demonstrated. Results obtained show that the self-adaptive fins can improve the temperature uniformity by 63% with respect to plain channel. The reduction in thermal resistance using bimorph metal/SMA fins sample allows the surface maximum temperature gradient to remain almost constant although heat flux increases. Energy savings are maximized in applications where partial load intervals contributes significantly to the overall operating period.

High-precision time synchronization chip design for industrial sensor and actuator network

Mission-critical (MC) sensor and actuator networks (SANs) are being applied widely for multiaxis motion control of robotic manipulators , particularly for performing MC tasks in smart manufacturing. One of the most challenging tasks in MC-SANs is the development of a precision time synchronization (PTS) protocol. A conventional precision time system uses the IEEE 1588 v2 standard [1] ; however, in MC-SANs, many factors need to be considered when designing an IoT computing system, such as robustness, cost-effectiveness, interoperability and scalability. This study proposes a high-precision time synchronization protocol based on Modbus sensors and actuator networks for an industrial fieldbus network. The PTS protocol design and hardware synthesis are conducted with a consistent and systematic design methodology. GRAFCET is used to model the individual functional modules and hierarchical behavior of the system. The behavior of each module is represented as a sequential–concurrent hybrid discrete event system . We apply high-level synthesis rules to design PTS hardware for a complex PTS system based on the VHSIC hardware description language (VHDL). The PTS hardware module has an embedded PTS algorithm with a proportional error correction model, and the time synchronization accuracy of the precision time protocol (PTP) chip is up to 42 ns. Experimental results demonstrate that our high-performance PTS controller chip can satisfy the requirements of multiaxis motion control and that it is more efficient than other protocols and products designed for similar industrial manufacturing applications.

Atomistic simulation toward real-scale microprocessor circuits

A highly efficient and novel atomistic simulation framework is first established for the thermal and mechanical behaviors of a whole microprocessor chip or its constituent functional modules, important for the performance and reliability of high-end microprocessor circuits. The largest simulated module contains about 55.3 thousand nano-transistors with around 107 billion atoms. Traditionally, the macroscopic continuous methods are difficult to treat nanoscale factors such as doping, thin dielectric layer, surface and interface in the nano-transistor devices, while the microscopic quantum mechanics method can only calculate one or several nano-transistors. This proposed simulation method realizes the integrated treatment of the above nanoscale factors and complex gate layout by coupling multiple interatomic potential models for different materials and designing efficient parallel algorithms, and bridges the mesoscale simulation gap between the aforementioned macroscopic and microscopic methods. The development provides the first atomic-scale simulation framework for predicting and modulating the thermal behavior of a microprocessor circuit or its functional module, which paves an exciting way to the atomic-resolution design of novel high-performance microprocessor chips in the post-Moore era.

Numerical study on hot spots thermal management in low pressure gradient distribution narrow microchannel embedded with pin fins

With the rapid development of high-performance electronic chips, chip hot spot management has become a prominent problem. Aimed at investigating the hot spots thermal management of gradient distribution narrow microchannel embedded with pin fins (MPFC), the effects of hot spot location, Reynolds number, hot spot area and heat flux on the chip surface were numerically studied. The maximum surface temperature on the chip does not change significantly with the change of hot spot location. However, with a Reynolds number of 281–844, the average temperature of MPFC-BP48, MPFC-BP2244, MPFC-BP264 at Hotspot 1 decreases by 4.6–10.8 K compared with that of MPFC-BP, but they show a significantly decrement of 7.7–19.6 K at Hotspot 2, indicating that the three improved gradient distribution microchannel embedded with pin fins exhibit better temperature uniformity and heat transfer capacity. In addition, an increase in hot spot area brings a temperature increment at hot spot, especially in MPFC-BP which has exceed the maximum temperature of 358 K, it is found that the embedded with pin fins is beneficial to enhanced the local heat transfer capacity. Furthermore, under different heat flux, MPFC-BP has exceeded the maximum temperature with the hot spot heat flux of 800 W/cm2, while MPFC-BP48, MPFC-BP2244, MPFC-BP264 can be kept below 358 K with the hot spot heat flux of 1000 W/cm2. This study optimizes the heat sink structure and has great significance for hot spot thermal management of chips.

Design and Implementation of Secure Cryptographic System on Chip for Internet of Things

Due to the 4th industrial revolution and the strength of the 5 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> Generation (5G) era, the Internet of Things (IoT) industry is growing significantly. As a result, the number of IoT devices in various industries, such as smart cars, smart homes, and smart healthcare, and the importance of security for these devices are increasing. This study proposes a design method for a secure cryptographic system on a chip (SecSoC) that can be used in the IoT industry and presents the results of the performance and security evaluations of the implemented chipset. The experimental results demonstrated that the SecSoC is a low-power high-performance cryptographic chip that is safe from external attacks. Compared to conventional smart card integrated circuits, the proposed design includes intrusion detection circuits that can respond to external attacks. At the same time, it supports a physical unclonable function for hiding secret data and cryptographic logic for maintaining integrity and confidentiality. The SecSoC ensured a fast transfer rate up to 110 Mbps and consumed only 95.8 mW when operating at maximum frequency.

Design and Optimization of an Immersion Liquid Cooling System in Internet Datacenter

With the development of high-performance chips, the heat flux of Internet datacenter (IDC) is on the rise, and heat dissipation becomes a major bottleneck of IDC development. The cooling needs of the IDC room can hardly be met by the traditional method of air cooling. In recent years, immersion liquid cooling has attracted a growing attention, due to its excellent performance. This paper designs and optimizes an immersion liquid cooling system for IDC. Multiple numerical simulations were carried out to analyze the influence of the system parameters on heat dissipation, and improve the system efficiency using a dielectric coolant. Specifically, 20 graphics processing units (GPUs) and 2 central processing units (CPUs) were set up in each machine of the liquid cooling server. Then, the GPU and CPU temperature was examined under different opening positions on the server top plate, inlet coolant temperatures, and coolant flow speeds. The results show that a 30mm-wide, 430mm-long opening should be set at the upper part of the GPU array, 20mm away from the top plate. The cooling effect can be optimized at the inlet temperature of 30℃, and the coolant flow speed of 3m3/h.

Oil/Water Microreactor with a Core–Shell Wetting State on a SOB/OL-SHB/HL Multilevel Patterned Surface

Droplet-based microfluidics, which manipulate mini-discrete droplets on surfaces to accomplish various chromogenic/fluorescence reaction-based detections, are promising for microminiaturization of analysis systems. However, rapid droplet evaporation in unsaturated surroundings is a complex problem. In this study, we proposed an ingenious concept of generating an oil/water microreactor on a superoleophobic/oleophilic-superhydrophobic/hydrophilic (SOB/OL-SHB/HL) multilevel patterned surface. A dual droplet with a nonvolatile liquid packing layer and a volatile droplet core was formed on the surface, achieving overt evaporation attenuation of the droplet core. The wettabilities of the SOB/OL-SHB/HL surface were first investigated. In addition, due to their outstanding configurability, oil/water microreactors with different pattern shapes, diverse compositions, and scale-up array configurations were obtained in a simple way. Due to the overt evaporation attenuation, the storage times of the reactants and products were markedly prolonged. Finally, as proofs of concept, oil/water microreactors were successfully applied to detect the target ion and to construct a droplet-based pH detector. The proposed oil/water microreactor on the SOB/OL-SHB/HL surface with distinct precision, flexibility, and high throughput is important to the development of high-performance microfluidic chips used in diagnosis, environment monitoring, chemical analysis, and particle synthesis.

Carbon Nanotube-Based Field-Effect Transistor-Type Sensor with a Sensing Gate for Ppb-Level Formaldehyde Detection.

The detection of harmful trace gases, such as formaldehyde (HCHO), is a technical challenge in the current gas sensor field. The weak electrical signal caused by trace amounts of gases is difficult to be detected and susceptible to other gases. Based on the amplification effect of a field-effect transistor (FET), a carbon-based FET-type gas sensor with a gas-sensing gate is proposed for HCHO detection at the ppb level. Semiconducting carbon nanotubes (s-CNTs) and a catalytic metal are chosen as channel and gate materials, respectively, for the FET-type gas sensor, which makes full use of the respective advantages of the channel transport layer and the sensitive gate layer. The as-prepared carbon-based FET-type gas sensor exhibits a low detection limit toward HCHO up to 20 ppb under room temperature (RT), which can be improved to 10 ppb by a further heating strategy. It also exhibits a remarkable elevated recovery rate from 80 to 97% with almost no baseline drift (2%) compared to the RT condition, revealing excellent reproducibility, stability, and recovery. The role of sensitive function in the FET-type gas sensor is performed by means of an independent gas-sensing gate, that is, the independence of the sensitive gate and the electron transmission channel is the main reason for its high sensitivity detection. We hope our work can provide an instructive approach for designing high-performance formaldehyde sensor chips with on-chip integration potential.

High-performance surface-enhanced Raman spectroscopy chip integrated with a micro-optical system for the rapid detection of creatinine in serum.

To improve the sensitivity of disease biomarker detection, we proposed a high-performance surface-enhanced Raman spectroscopy (SERS) chip integrated with a micro-optical system (MOS). The MOS, which is based on the micro-reflecting cavity and the micro-lens, optimizes the optical matching characteristics of the SERS substrate and the Raman detection system, and greatly improves the SERS detection sensitivity by improving the collection efficiency of the Raman scattering signal. A uniform single layer of silver nanoparticles on a gold film was prepared as the SERS substrate using a liquid-liquid interface self-assembly method. The micro-reflecting cavity and micro-lens were prepared using micro-processing technology. The SERS chip was constructed based on the MOS and the Au film-based SERS substrate, and experimental results showed an EF of 1.46×108, which is about 22.4 times higher than that of the Si-based SERS substrate. The chip was used for the detection of creatinine and the detection limit of creatinine in aqueous solution was 1 µM while the detection limit in serum was 5 µM. In addition, SERS testing was conducted on serum samples from normal people and patients with chronic renal impairment. Principal component analysis and linear discriminant analysis were used for modeling and identification, and the results showed a 90% accuracy of blind sample detection. These results demonstrate the value of this SERS chip for both research and practical applications in the fields of disease diagnosis and screening.

The Application Progress and Prospect of Miniature Spectrometer in Precision Agriculture

Miniature spectrometers are widely used in various fields such as industry and agriculture thanks to their advantages of easy portability, non-destructive testing, online testing, and high efficiency. By surveying massive research results at home and abroad, this paper summarizes the current development status of miniature near-infrared spectrometers at home and abroad, emphatically introduces the application research progress of miniature spectrometers in precision agriculture. Finally, it outlooks the development prospects of miniature spectrometers. While improving specificity, miniature spectrometers are developing towards high performance, new principles, and single chip.

Design and technical verification of a new type of subscriber identity module card for internet of vehicles

The Internet of Vehicles communication security aims to solve the V2X communication security problems under several scenarios, including direct communication and communication based on cellular network, and provides guaranteed communication security for the achievement of business goals such as vehicle-road information collaboration and road safety. Currently, V2X communication security mostly adopts digital certificate technical proposal based on public key infrastructure and is implemented through the HSM security module. However, this solution requires to preset security data such as digital certificate in the HSM module of the vehicle terminal, which has high demands on the production line of the enterprise, the difficulty is predictable. This paper designs a new type of SIM card for Internet of Vehicles based on high performance chip, which can implement the writing and updating operation of security parameters (certificates, keys, etc.) online, which can reduce the requirements for the transformation of the production line of car companies and at the same time, the security of data management is also improved. The validation result indicates that the new SIM card can realize functions such as login authentication, certificate download, signature verification, etc., and its performance meets the requirements of V2X secure communication.

Surface coupling of oligo-functionalized dendrimers to detect DNA mutations after blocked isothermal amplification

This study presents a useful strategy for the bioconjugation of probes for developing high-performance versatile chips applied to fast-response, low-cost DNA biosensing. We herein demonstrate that the high-density immobilization of dendrimer-oligonucleotide hybrids promotes the reliable sensitive sensing of single-nucleotide variants despite their low concentration.Carboxyl-terminated poly(amidoamine) dendrimers directly coupled to amine-derivatized oligonucleotides were anchored to the activated surfaces of thermoplastics (polycarbonate and cycloolefin polymer). Surface characterization techniques and hybridization assays reported that the multiple functional sites of the oligo-functionalized dendrimer facilitated the efficient immobilization of probes and the sensitive capture of DNA targets (5 pM detection limit). Array performance was better than that of the surfaces functionalized with linear crosslinkers, such as vinyltriethoxysilane or 3-(triethoxysilyl)propyl isocyanate, as well films with unconjugated dendrimer molecules.Based on oligo-dendrimers hybrids, disposable DNA-based biosensing platforms were developed for point-of-care diagnostics. A selective high-sensitive hybridization assay was performed that included amplification products of blocked PCR and recombinase polymerase amplification (RPA) as an isothermal reaction. The chip results indicated that the single-nucleotide mutant variant of the BRAF oncogene was correctly discriminated in colorectal tissues from cancer patients.

Design of M-tree Adder using majority logic for removal of artifacts in bio signal

This research's motivation has focused on signal processing in VLSI design for improving the system throughput in terms of high performance, energy-efficient, high speed, and small chip area. Very Large Scale Integrated circuit plays a vital role in modern technologies. The technology improvements happened because a general digital system design's processing device faces ethical challenges for intricate circuit design. In the recent era, the VLSI has the most compact and powerful IC fabrication technique to improve an individual processor's efficiency. This chapter stretches the design of digital circuits such as binary adders, multipliers, and implementation of FIR in signal processing, which is associated with a novel algorithm for the removal of power line interference in the bio-signal application. Also, deal with the current trends to identify the various pipeline architecture design and algorithms to bring out an optimized solution using a modern analytical method to improve the processor speed and accuracy. The proposed adder has achieved 96% efficiency in terms of gate count, delay, and power compared with existing analysis. Digital system design produces 83.5% efficiency in an existing system and it required the maximum number of gate count and an increasing number of delays when compared with recent research. The design summary is analyzed by using XILINX 14.7 ISE synthesis and the implementation process is highly reached with the help of MATLAB 2018a. IC fabrication is the most important design process in today's VLSI manufacturing industry. Application of SOC is used to fabricate more chips with the help of silicon resonator, to accomplish the circuit complexity by using silicon resonator which is more suitable for the fabrication process and reducing manufacturing cost.