High Output Impedance Research Articles

Design of Cascode Current Mirror Using CMOS Technology for Low Power Application

Background: Many applications, including biological applications, require a very high output impedance current mirror because they run at very low voltages. The circuit known as the current mirror applies the idea that two identical MOS transistors with the same gate-source voltage will have equal channel currents flowing through them. Objective: The objective of this study is to optimize the design to minimize power consumption while maintaining accurate current mirroring, which is crucial for low-power and energy-efficient electronic systems. Methods: This study is performed in Cadence Virtuoso using the gdpk45 technology node to construct a cascode current mirror, comparing simulation findings to other contemporary mirrors. Results: A significant improvement in power usage is shown compared to other current mirrors, and a small signal model analysis of the circuit, the design, and its mathematical model is investigated. Conclusion: Compared to the circuits that were previously designed, the output resistance values are substantially greater. The cascode current mirror that is suggested in this paper uses 48 μW of electricity, while the other cascode current mirror uses 74.186 μW.

0.5 V, Low-Power Bulk-Driven Current Differencing Transconductance Amplifier.

This paper presents a novel low-power low-voltage current differencing transconductance amplifier (CDTA). To achieve a low-voltage low-power CDTA, the BD-MOST (bulk-driven MOS transistor) technique operating in a subthreshold region is used. The proposed CDTA is designed in 0.18 µm CMOS technology, can operate with a supply voltage of 0.5 V, and consumes 1.05 μW of power. The proposed CDTA is used to realize a current-mode universal filter. The filter can realize five standard transfer functions of low-pass, band-pass, high-pass and band-stop, and all-pass from the same circuit. Neither component-matching conditions nor input signals of the inverse type are required to realize these filter functions. The current-mode filter offers low-input and high-output impedance and uses grounded capacitors. The natural frequency and quality factor of the filters can be orthogonally controlled. The proposed CDTA and its applications are simulated using SPICE to confirm the feasibility and functionality of the new circuits.

Voltage Differencing Buffered Amplifier Realisation Using 32 nm FinFET Technology and Universal Filter Applications

This paper presents high-frequency universal filter applications based on a voltage differential buffered amplifier (VDBA) using 32 nm fin field effect transistor (FinFET) technology. FinFET technology is a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology to avoid the problems caused by the decrease in transistor size as the technology evolves. In addition to the manufacturing process being similar to CMOS technology, FinFET technology offers many advantages, such as reduced short channel effects, higher drain current, reduced static leakage current, faster switching time, lower supply voltage, lower power consumption, and higher efficiency. The VDBA active circuit block, which has high input impedance and low output impedance, is preferred for high-frequency and high-bandwidth applications. It is advantageous to design active filter circuits using VDBA because of its superior features, such as lower power consumption, higher bandwidth, wider range linearity, and the ability to implement the proposed circuits without external resistors. In this study, FinFET-based VDBA and filter application are simulated with the Spice simulation programme using 32 nm PTM technology parameters. Simulation results using 32 nm FinFET technology are compared with those using 0.18 µm TSMC technology. It is concluded that 32 nm FinFET technology reduces power consumption by 98.8 % and increases bandwidth by 145 times. The successful results show that FinFET technology is superior to CMOS technology in analogue circuit design. FinFET-based VDBA circuits and filters will be more advantageous in the design of signal processing and biomedical applications.

Electret mechano-sensor array integrated with tribopotential-modulated thin film transistors for precise spatiotemporal pressure perception

Spatiotemporal pressure perception is a key function of electronic skins. Electret mechano-sensors, as active sensors for E-skins, have garnered significant interest, with outstanding sensing performance in dynamic pressure measurement. However, their high output impedance poses a challenge in accurately and simply measuring low-frequency or static pressure distribution. Herein, we proposed an electret mechano-sensor array, in which each sensing cell is based on an electret sensor integrated with an IGZO TFT. The high input impedance of the TFT facilitates the sensor signal readout and enables the measurement of static pressure. The super-linear amplification feature of the TFTs improves the sensitivity and linearity of the sensors. An IGZO TFT layer with the lower electrodes of the electret sensor was fabricated through microfabrication process and assembled with a pre-charged electret film to achieve a mechano-sensor array with a high density. The fabricated TFT-integrated electret mechano-sensor array has achieved pattern detection and spatial tactile perception. Moreover, the sensor array can record spatiotemporal static pressure and arterial pulse waves simultaneously, exhibiting high resolution in detecting subtle changes and potentially offering various physiological information regarding the cardiovascular system. This work demonstrated that the proposed mechano-sensor array has capabilities for broad-scale pressure distribution detection in healthcare monitoring and human-computer interaction.

Single EX-CCCII-Based First-Order Versatile Active Filter

This paper presents a new current-mode first-order versatile active filter employing one extra-x second-generation current controlled current conveyor (EX-CCCII) and one grounded capacitor. The proposed filter can realize first-order filtering functions of a low-pass filter (LPF), high-pass filter (HPF), and all-pass filter (APF) within the same topology with low-input and high-output impedances required for current-mode circuits. This multiple-output EX-CCCII-based filter can provide six transfer functions as both non-inverting and inverting filtering functions of the LPF, HPF, and APF are obtained. The filter also offers electronic control of the pole frequency of all filtering. The proposed current-mode filter can be applied to work as a mixed-mode active filter, namely in the transadmittance-mode (TAM), transimpedance-mode (TIM), and voltage-mode (VM). Each operation mode can provide six transfer functions. The proposed filter was simulated and designed using SPICE and 0.18 µm CMOS technology. Experimental results using the commercially available integrated circuit AD844 were used to confirm the functionality of the new circuits.

Influence of the Electrical Test Setup on the Voltage Gain Measurement of an Unloaded Rosen-Type Piezoelectric Transformer Vibrating in the First Three Modes

Abstract In recent years, Piezoelectric Transformers (PTs) have become a great success due to their excellent properties, especially in applications requiring high voltage. The Rosen-type PT is well known for this performance, as its voltage gain at the resonant frequency can reach few thousands. However, the high output impedance of this device can make an accurate electrical measurement of the output voltage difficult, hence the need to ensure good impedance matching along the measuring electrical test setup. For this purpose, two high impedance oscilloscope probes were successively added to the secondary side to further emulate the measurement chain and match the experiments as closely as possible with the developed 1D model. Accordingly, for an unloaded Rosen type piezoelectric transformer, made of hard ceramic (pz26) with corresponding dimensions 2L×w×t =25 mm×3 mm×2 mm and operating in the first three modes, the corresponding input impedances Zin were evaluated at 665 Ω - 225 Ω and 1974 Ω, while the output impedances Zout were evaluated at 19.2 MΩ - 15.4 MΩ, and 1.8 MΩ. A voltage gain of 164, 179 and 23 at frequencies of 69.4 kHz, 136 kHz and 204.6 kHz, respectively was successfully measured, with a precision of less than 5%. In addition, a detailed equivalent circuit of the transformer was built and all its lumped RLC components were experimentally identified using the Nyquist diagram showing, on the whole, a well-accepted agreement with the expected results.

A Low Mismatch Current Charge Pump Applied to Phase-Locked Loops.

This paper presents a charge pump circuit with a wide output range and low current mismatch applied to phase-locked loops. In this designed structure, T-shaped analog switches are adopted to suppress the non-ideal effects of clock feedthrough, switching time mismatch, and charge injection. A source follower and current splitting circuits are proposed to improve the matching accuracy of the charging and discharging currents and reduce the current mismatch rate. A rail-to-rail high-gain amplifier with a negative feedback connection is introduced to suppress the charge-sharing effect of the charge pump. A cascode current mirror with a high output impedance is used to provide the charge and discharge currents for the charge pump, which not only improves the current accuracy of the charge pump but also increases the output voltage range. The proposed charge pump is designed and simulated based on a 65 nm CMOS process. The results show that when the power supply voltage is 1.2 V, the output current of the charge pump is 100 μA, the output voltage is in the range of 0.2~1 V, and the maximum current mismatch rate and current variation rate are only 0.21% and 1.4%, respectively.

A voltage-mode fully cascadable biquad with three CFOAs and grounded capacitors

In this paper, a new voltage-mode second-order multifunction filter with three current feedback operational amplifiers is developed. This circuit generates low-pass filter, band-pass filter (BPF), inverting-type BPF, notch filter, and all-pass filter (APF) responses with all gains. It has high input and low output impedances for all the filter responses. It also has the advantage of grounded two capacitors, which is essential for integrated circuit technology. It has orthogonally controllable features for all the filter responses except the APF one. However, one passive element matching condition is needed to obtain an APF response. Many simulations are carried out via the SPICE program, where 0.13 µm technology parameters are utilized. Furthermore, a few experiments are performed using the AD844s to see the performance of the developed filter in practice.

Updates on Impact Ionisation Triggering of Thyristors

High voltage (HV) generators are used in multiple industrial and scientific facilities. Recent publications have demonstrated that triggering industrial thyristors (relatively slow switching devices) in overvoltage mode, also called impact ionization mode, significantly enhances their dU/dt and dI/dt characteristics. This novel triggering methodology necessitates the application of substantial overvoltage between the thyristor’s anode and cathode, delivered with a swift slew rate exceeding 1 kV/ns. The adoption of compact pulse generators constructed from commercially available off-the-shelf components (COTS) opens up avenues for deploying this technology across various domains, including the implementation of high-speed kicker generators in particle accelerators. In our methodology, we employed commercially available high-voltage SiC MOSFETs along with a custom-designed fast gate driver. This driver was conceptualized based on the recent development of gate boosting techniques, featuring a driving voltage exceeding 600 V. The gate driver for these MOSFETs comprises three key components: a level-shifter with NMOS and PMOS transistors, a compact Marx generator with two avalanche transistors, and a GaN HEMT in a high input and low output impedance configuration. The proposed gate-boosting driver achieves a slew rate exceeding 1 kV/ns for the driving pulse. Furthermore, we demonstrate that with this driver, a 1.7 kV rated SiC MOSFET can produce an output pulse of 1.45 kV and a maximum slew rate of ≈2.5 kV/ns. This gate-boosting driver aims to minimize commutation times, achieves a slew rate of over 1 kV/ns, and handle higher loads, making it ideal for impact ionization triggering of industrial thyristors.

An improved CMOS second‐generation current controlled conveyor with enhanced tunable range of RX and its applications

SummaryThis paper presents a new CMOS‐based second‐generation current controlled conveyor (CCCII), based on a mixed translinear cell composed of CMOS‐based translinear elements, which offers a wide tunable range of four decades for the X‐terminal input resistance RX. The current‐controlled grounded and floating tunable resistors and multifunction filter with tunable cut‐off frequency have been realized to show the practical utility of the proposed CCCII architecture. Various performance evaluations have been carried out through simulations conducted on Cadence Virtuoso software using 0.18 μm gpdk CMOS technology at a supply voltage of ±1.5 V. Simulation results show the effectiveness of the proposed CCCII in attaining a wide tunable Rx ranging from 130 MΩ to 13 kΩ, offering good linearity, nearly unity voltage and current transfer gains, high input impedance at port Y varying from 3.7 GΩ to 1.18 MΩ, high output impedance at port Z varying from 67.63 GΩ to 13.19 MΩ, with the power consumption in the range of 3.68 μW to 18.78 μW for variation in bias current (Io) from 100 pA to 1 μA.

LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology

Although Moore’s Law reaches its limits, it has never applied to analog and RF circuits. For example, due to the short channel effect (SCE), drain-induced barrier lowering (DIBL), and sub-threshold slope (SS)…, longer transistors are required to implement analog cells. From 22 nm CMOS technology and beyond, for reasons of variability, the channel of the transistors has no longer been doped. Two technologies then emerged: FinFET transistors for digital applications and UTBB FDSOI transistors, suitable for analog and mixed applications. In a previous paper, a new topology was proposed utilizing some advantages of the FDSOI technology. Thanks to this technology, a novel cross-coupled back-gate (BG) technique was implemented to improve analog and mixed signal cells in order to reduce the surface of the integrated circuit. This technique was applied to a current mirror to reduce the small channel effect and to provide high-output impedance. It was demonstrated that it is possible to overcompensate the SCE and DIBL effects and to create a negative output resistor. This paper presents a new LC tank oscillator based on this current mirror functioning as a negative resistor.

Design and simulation of a new current mirror circuit with low power consumption and high performance and output impedance

Design and simulation of a new current mirror circuit with low power consumption and high performance and output impedance

Current-Mode Shadow Filter with Single-Input Multiple-Output Using Current-Controlled Current Conveyors with Controlled Current Gain.

In this paper, a novel current-mode shadow filter employing current-controlled current conveyors (CCCIIs) with controlled current gains is presented. The CCCII-based current-mode shadow filters are resistorless and can offer a number of advantages such as circuit simplicity and electronic tuning capability. The proposed shadow filters offer five filtering functions, i.e., low-pass, high-pass, band-pass, band-stop, and all-pass functions, in the same topology. Furthermore, no component matching condition is required to realize all the transfer functions. The natural frequency and quality factor adjustment is possible by using the CCCII current gains without the need to use external amplifiers, all capacitors are grounded, and the filter terminals offer low-input and high-output impedance. To verify the functionality and feasibility of the new topologies, the proposed circuits were simulated using SPICE and the transistor model process parameters NR100N (NPN) and PR100N (PNP) from AT&T's bipolar arrays ALA400-CBIC-R. The simulation results are consistent with the theory. The CCCII experimental setup was designed using commercially available 2N3904 (NPN) and 2N3906 (PNP) transistors with a supply voltage of ±2.5 V. The measurement results confirm the performance of the designed filters.

Switched CMOS current source compared to enhanced Howland circuit for bio-impedance applications.

Bio-impedance Spectroscopy (BIS) is a technique that allows tissue analysis to diagnose a variety of diseases, such as medical imaging, cancer diagnosis, muscle fatigue detection, glucose measurement, and others under research. The development of CMOS integrated circuit front-ends for bioimpedance analysis is required by the increasing use of wearable devices in the healthcare field, as they offer key features for battery-powered wearable devices. These features include high miniaturization, low power consumption, and low voltage power supply. A key circuit in BIS systems is the current source, and one of the most common topology is the Enhanced Howland Current Source (EHCS). EHCS is also used when the current driver is driven by a pseudo-random signal like discrete interval binary sequences (DIBS), which, due to its broadband nature, requires high performance operational amplifiers. These facts lead to the need for a current source more compatible with DIBS signals, ultra-low power supply, standard CMOS integrated circuit, output current amplitude independent of input voltage amplitude, high output impedance, high load capability, high output voltage swing, and the possibility of tetra-polar BIS analysis, that is a pseudotetra-polar in the case of EHCS. The objective of this work is to evaluate the performance of the Switching CMOS Current Source (SCMOSCS) over EHCS using a Cole-skin model as a load using SPICE simulations (DC and AC sweeps and transient analysis). The SCMOSCS demonstrated an output impedance of more than 20 MΩ, a ± 2.5 V output voltage swing from a +3.3 V supply, a 275 μA current consumption, and a 10 kΩ load capacity. These results contrast with the + 1.5 V output voltage swing, the 3 kΩ load capacity, and the 4.9 mA current of the EHCS case.

0.5-V 281-nW Versatile Mixed-Mode Filter Using Multiple-Input/Output Differential Difference Transconductance Amplifiers.

This paper presents a new low-voltage versatile mixed-mode filter which uses a multiple-input/output differential difference transconductance amplifier (MIMO-DDTA). The multiple-input of the DDTA is realized using a multiple-input bulk-driven MOS transistor (MI-BD-MOST) technique to maintain a single differential pair, thereby achieving simple structure with minimal power consumption. In a single topology, the proposed filter can provide five standard filtering functions (low-pass, high-pass, band-pass, band-stop, and all-pass) in four modes: voltage (VM), current (CM), transadmittance (TAM), and transimpedance (TIM). This provides the full capability of a mixed-mode filter (i.e., twenty filter functions). Moreover, the VM filter offers high-input and low-output impedances and the CM filter offers high-output impedance; therefore, no buffer circuit is needed. The natural frequency of all filtering functions can be electronically controlled by a setting current. The voltage supply is 0.5 V and for a 4 nA setting current, the power consumption of the filter was 281 nW. The filter is suitable for low-frequency biomedical and sensor applications that require extremely low supply voltages and nano-watt power consumption. For the VM low-pass filter, the dynamic range was 58.23 dB @ 1% total harmonic distortion. The proposed filter was designed and simulated in the Cadence Virtuoso System Design Platform using the 0.18 µm TSMC CMOS technology.

New Current-Mode Precision Full-Wave Rectifier Employing Single Inverted Z-Copy Current Differencing Buffered Amplifier

This paper aims to introduce a new current-mode precision full-wave rectifier configuration using a single inverted Z-copy current differencing buffered amplifier (IZC-CDBA) and two nMOSFETs. The unique feature of the proposed configuration is that it can simultaneously produce both the inverting and non-inverting rectified outputs without changing its architecture. Only active components make the configuration more suited for IC implementation. Moreover, it features low input impedance and high output impedance, making it fully cascadable. In addition, the new design enjoys extremely high-frequency operations. The effects of non-ideal transfer gain and parasitic impedances on the designed circuit are also explored. PSPICE simulations test the functionality of the proposed circuit for two distinct types of IZC-CDBA realization. The CMOS-based realization is checked through TSMC 0.18 μm level-7 technology parameters. The average DC current output, input dynamic range (± 450 μA), power consumption, temperature, total harmonic distortion, noise, and Monte-Carlo studies are performed to judge the efficiency level. The findings of the simulations match up nicely with the theoretical analysis. RMS and average value computation for a sinusoidal signal are also provided as an application of the suggested full-wave rectifier.

Passive power management for triboelectric nanogenerators in sub-microwatt applications

Triboelectric nanogenerators (TENGs) have been regarded as a promising enabling technology for self-powered applications. However, their inherent characteristics, such as high internal impedance and high output voltage, not only make them unsuitable to be used as a direct power source but also create substantial challenges in power management for low-power applications. To date, effective power management systems have not been available for sub-microwatt applications. In this study, we propose a passive power management system for such extremely low-power scenarios. The system can effectively condition the electricity generated by a TENG into a form compatible with standard electronic devices, which can then be stored on an energy storage device. We demonstrate that for TENGs using a liquid metal drop, the power management system can transfer up to 85% of the electricity generated to the storage when the power output of the TENG is below 1 μW. For TENGs using a water drop, the energy transfer efficiency can reach a remarkably high level of 80% when the TENG harvests as low as 38 nJ of energy per cycle.

Gate-readout and a 3D rectification effect for giant responsivity enhancement of asymmetric dual-grating-gate plasmonic terahertz detectors.

We experimentally investigated the asymmetric dual-grating-gate plasmonic terahertz (THz) detector based on an InGaAs-channel high-electron-mobility transistor (HEMT) in the gate-readout configuration. Throughout the THz pulse detection measurement on the fabricated device, we discovered a new detection mechanism called the "3D rectification effect" at the positive gate bias application, which is a cooperative effect of the plasmonic nonlinearities in the channel with the diode nonlinearity in the heterobarrier between the InGaAs channel layer and the InAlAs spacer/carrier-supply/barrier layers, resulting in a giant enhancement of the detector responsivity. We also found that an undesired long-tail waveform observed on the temporal pulse photoresponse of the device is due to trapping of carriers to the donor levels in the silicon δ-doped carrier-supply layer when they tunnel through the barrier to the gate and can be eliminated completely by introducing the so-called inverted-HEMT structure. The internal current responsivity and noise-equivalent power are estimated to be 0.49 A/W (with the equivalent voltage responsivity of 4.9 kV/W with a high output impedance of 10 kΩ) and 196 pW/√Hz at 0.8 THz. These results pave the way towards the application of the plasmonic THz detectors to beyond-5G THz wireless communication systems.

Ultra‐High DC and Low Impedance Output for Free‐Standing Triboelectric Nanogenerator

AbstractThe free‐standing triboelectric nanogenerator (F‐S TENG) is demonstrated to be an efficient energy conversion device. However, limited by the inherent features of high‐voltage, low alternating current and high output impedance, TENGs suffer from inefficient energy utilization and difficulties in practical applications. Therefore, the efficient harvest of mechanical energy and optimization of output are currently critical issues for TENGs. Here, a strategy is proposed for optimizing the inherent features by coupling F‐S TENG to a capacitor auto‐conversion circuit (CAC). For the first time, a specific idea is proposed explicitly to reduce the output impedance by the management circuit. Eventually, a high current density of 32 A m−2 and a charge density of 1.75 mC m−2 are achieved, which is 8.78 times higher than previous works. The power density and energy density reach to 124 W m−2 and 252 mJ m−2 under 470 and 150 Ω respectively. Then, 5000 LEDs and two lamps rated at 220 V and 50 W are manually illuminated. The resulting pulse output is utilized as a trigger source for the thyristor, enabling DC contactless switching. This work provides a novel approach to realize high‐performance DC output of TENGs and effectively reduce external load impedance.

Realization of a new PMOS transistors based first-order delay equalizer suitable for communication networks

In this paper, a novel first-order delay equalizer based on a PMOS transistor is proposed which is highly suitable for the communication systems and networks. The core circuit consists of three unity-gain PMOS inverting amplifiers, one resistor and one capacitor. The newly proposed delay equalizer has ability to provide both inverting all pass and non-inverting all pass responses simultaneously from the same structure without restriction of any matching of passive elements to achieve desired performance. High input and low output impedances enable cascadability in the proposed circuit. The circuit's behaviour under loading effects and the effect of parasitic components are also examined in detail. To assess the applicability of the proposed structure, nth-order delay equalizer is also presented. The performance of the proposed work is validated through PSPICE simulations utilizing TSMC 0.18 μm level-7 CMOS technology process parameters, with voltage levels set at ±0.9 V. Furthermore, real-time post-layout verification is being carried out to ensure the confirmed performance.