High Off-currents Research Articles

Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor

In this paper, a novel Triple metal double gate germanium on insulator vertical TFET is proposed and investigated by using SILVACO ATLAS TCAD tool. Gate metal work-function engineering is used to overcome the problem of low ON-current, high OFF-current, high average subthreshold swing and low ION/IOFF ratio which are present in single material double gate TFET. By modulating the values of metal gate work-functions, the performance of the device is improved. The low band-gap material and vertical tunneling concept also increase the steepness of subthreshold slope as well as ON-current of the device. Further the effects of channel length and gate to source overlap thickness on the device are also analysed to get optimum device dimensions for obtaining the improved performance results. The vertical stacking of source, channel and drain also consumes less space as compared to the conventional TFETs. So, the considerable good performance of this proposed device makes it suitable as an attractive choice for ultra-low power applications.

Enhanced Electro-Optical Performance of Inorganic Perovskite/a-InGaZnO Phototransistors Enabled by Sn-Pb Binary Incorporation with a Selective Photonic Deactivation.

Optoelectronic applications using perovskites have emerged as one of the most promising platforms such as phototransistors, photovoltaics, and photodetectors. However, high-performance and reliable perovskite photonic devices are often hindered by the limited spectral ranges of the perovskite system along with the lack of appropriate processing technologies for the implementation of reliable device architectures. Here, we explore a hybrid phototransistor with a heterojunction of a Sn-Pb binary mixed halide perovskite (CsSn0.6Pb0.4I2.6Br0.4) light absorber and an amorphous-In-Ga-Zn-O (a-IGZO) charge carrying layer. By incorporating Sn-Pb binary components with an all-inorganic base, broadening of light-absorbing spectral ranges with enhanced stability has been achieved, indicating inevitable highly increased conductivity, which triggers a high off-current of the devices. Accordingly, the selectively ultraviolet (UV)-irradiated electrical deactivation (SUED) process is carried out to suppress the high off-current with a reliable device structure. Particularly, it is noted that the selective UV irradiation can facilitate oxidation and distortion of the chemical structure in specific perovskite regions, providing enhanced gate bias modulation of the phototransistor with an increased on/off-current ratio from ∼103 to ∼106. Finally, the SUED-processed phototransistor exhibits an improvement in the photosensitivity by more than 3 orders of magnitude up to 8.0 × 104 and detects in the spectral range from visible to near-infrared (NIR) light (∼860 nm) with good on/off switching behaviors.

Investigation of Recessed Junctionless Double Gate MOSFET for Radio Frequency Applications

Junctionless Metal Oxide Semiconductor Field-Effect Transistor (JL MOSFET) is one of the promising candidate to replace the junction based MOSFET for upcoming technology nodes. Semiconductor industries are continuously urging for large ON current with the low OFF current and low specific on resistance. However, high ON current is achieved in Conventional (Conv.) JL DG MOSFET by using high doping concentration at the cost of high OFF current which leads depletion mode operation. Moreover, low doping, narrow channel thickness and high work function gate materials are using to operate Conv. JL DG MOSFET in enhancement mode (Vth > 0 V for N-JL DG MOSFET, Vth < 0 V for P-JL DG MOSFET) but ON current is reduced in all above mentioned solutions. To overcome the above mentioned problems, a new architecture is developed called Recessed JL DG MOSFET. In Recessed JL DG MOSFET silicon region is recessed under the gate region and some gate portion is extended towards source and drain region. Recessed JL DG MOSFET shows the same ON current as achieved in Conv. JL DG MOSFET with very low OFF current (leakage current) by considering high doping concentration. Surface potential, electron density, energy band distribution, drain current have been investigated to proof the enhancement mode operation of Recessed JL DG MOSFET. Figure of Merits (FOMs) for RF performance such as Trans-conductance, capacitance and intrinsic power gain (S21), Trans-conductance frequency product (TFP), Gain frequency product (GFP) and Gain trans-conductance frequency product (GTFP) have also investigated of Recessed JL DG MOSFET.

Off-current reduction in p-type SnO thin film transistors

SnO is one of the few candidates for p-type oxide thin film transistors (TFTs) because it retains a reasonable high hole mobility in a nanocrystalline film. However, the high off-current of SnO TFT limits its usefulness. In this work, SnO TFTs were fabricated using thermal evaporation under ultra-high vacuum. In order to decrease the off-current in p-type SnO thin film transistors (TFTs), we used yttrium to reduce n-type minority charges in the channel. The on/off ratio of the TFT increases from 102 to 5 × 104 and the mobility of the TFT in the saturated regime reduces from 1.6 to 1.4 cm2/V s when the SnO channel is doped with 1 wt. % of Y. Grazing incidence X-ray diffraction and X-ray photoelectron spectroscopy reveal that the reduction of SnO2 in the Y-doped SnO TFT channel is the main reason for the improvement in the TFT characteristics.

Nanocarbon-Based Field-Effect Transistor Biosensors (bioFETs) for Real-Time Detection of DNA Sequences

Field-effect transistor devices based on functionalized nanocarbon materials (2-D graphene thin layers and 1-D carbon nanotubes) are a promising technology for biomolecular sensing applications. In particular, this type of devices allows for label-free detection of DNA hybridization with the advantage of an easy and direct electrical readout in comparison with most routine techniques. In this work, we report on the design and fabrication of nanocarbon-based bioFETs for DNA hybridization detection. Employing a combination of microfluidics and real-time electrical measurements, we investigated the response of bioFETs to single-stranded DNA (ssDNA) probe tethering and hybridization with complementary target ssDNA in saline buffer solution. The bioFETs were assembled from individual carbon nanotubes or graphene nanoribbons connected by pairs of metallic electrodes using photolithography techniques. Transfer curves of bioFETs in saline buffer were measured using an immersed pseudo-reference electrode. We obtained transfer curves showing current modulation with high OFF-current at the charge-neutrality point. Probe and target ssDNA were chosen as 22-nucleotide-long complementary sequences. Probe tethering on nanocarbon was obtained using diazonium chemistry followed by EDC/NHS coupling of an amine moiety placed at the extremity of the DNA probe [1]. Transfer characteristics were measured before/after probe and target injection. Moreover, to further characterize the bioFETs response, probe immobilization and probe-target hybridization were recorded in real-time using electrical readout. The development of highly selective and ultra-sensitive sensors for DNA will open novel technological avenues to improve the detection of genetic biomarkers for various diseases. [1] Bouilly, D. et al. Nano Letters 16, 4679–4685 (2016)

A Two-Step Sensing Circuit for the Hysteresis Loop Selector-Based Resistive Non-Volatile Memory Arrays

A high selectivity semiconductor selector is the key component in the ultra-high density and low power 3-D resistive non-volatile memory array. The state-of-art selectors suffer from various issues including low selectivity, high OFF current, and low ON current, which significantly limit the array size and performance. Recently, a hysteresis loop (HL) selector with the high selectivity, moderate ON voltage and large HL window was developed to address the high leakage current issue. In this brief, a two-step sensing scheme is proposed to minimize the read disturbance and sensing power. The proposed two-step sensing circuit could achieve 25-ns fast sensing speed with 3.92-uW low sensing power.

Schottky Tunneling Effects in a Tunnel FET

Tunnel FETs (TFETs) have attracted a great deal of attention due to their steep subthreshold swing (SS) of less than 60 mV/dec, which overcomes the theoretical constraint imposed by the thermal limit in a conventional inversion-mode (IM) FET. Based on its advantages as a short-channel device with low stand-by power consumption, TFETs shows promise to replace IM-FETs. As the channel length is shortened to minimize the total gate pitch; however, the gate sidewall spacer is miniaturized as well. In this paper, the influence of junction extension length ( $L_{\mathrm {ext}})$ on TFET behavior is discussed where the length of the gate spacer is assumed to be the gap between the source and drain (S/D) electrodes and the gate edge. It was found that, when $L_{\mathrm {ext}}$ is aggressively scaled down, having S/D electrodes (silicide or metal) with identical work functions (WFs) leads to a severely high OFF-current ( $I_{ \mathrm{\scriptscriptstyle OFF}})$ and high SS. By adopting separate asymmetric WFs for the p-type and n-type S/D electrodes, the on/off characteristics were improved with suppressed $I_{ \mathrm{\scriptscriptstyle OFF}}$ and steeper slopes. It was also shown that the device performance of a TFET with higher source-side doping concentrations ( $\sim 5\times 10^{20}$ cm−3) can be further improved even at the aggressively scaled-down $L_{\mathrm {ext}}$ by boosting the on-current.

High performance photolithographically-patterned polymer thin-film transistors gated with an ionic liquid/poly(ionic liquid) blend ion gel

We demonstrate the fabrication of polymer thin-film transistors gated with an ion gel electrolyte made of the blend of an ionic liquid and a polymerised ionic liquid. The ion gel exhibits a high stability and ionic conductivity, combined with facile processing by simple drop-casting from solution. In order to avoid parasitic effects such as high hysteresis, high off-currents, and slow switching, a fluorinated photoresist is employed in order to enable high-resolution orthogonal patterning of the polymer semiconductor over an area that precisely defines the transistor channel. The resulting devices exhibit excellent characteristics, with an on/off ratio of 106, low hysteresis, and a very large transconductance of 3 mS. We show that this high transconductance value is mostly the result of ions penetrating the polymer film and doping the entire volume of the semiconductor, yielding an effective capacitance per unit area of about 200 μF cm−2, one order of magnitude higher than the double layer capacitance of the ion gel. This results in channel currents larger than 1 mA at an applied gate bias of only –1 V. We also investigate the dynamic performance of the devices and obtain a switching time of 20 ms, which is mostly limited by the overlap capacitance between the ion gel and the source and drain contacts.

Improvement of a Vertical Thin Film Transistor Based on Low-Temperature Polycrystalline Silicon Technology by Introduction of an Oxide Barrier between Drain and Source Layers

After the demonstration of feasibility of a new vertical thin film transistor (VTFT) based on low-temperature (T≤600°C) polycrystalline silicon (poly-Si) technology, some improvements were performed. The first fabrications gave evidence of some remaining drawbacks due to the relatively large area of common coverage between drain and source. As a result, relatively high offcurrent was observed that decreased the Ion/Ioff ratio. A way to significantly decrease the Ioff current consists in inserting a thin insulating layer between source and drain. Fabrication and electrical characterization of this new device confirmed the good approach that can be extended to other vertical architectures that are on progress.

Quasi-vertical multi-tooth thin film transistors based on low-temperature technology (T ⩽ 600 °C)

A new concept of vertical thin film transistor (TFT), called thin film transistor comb (TFTC), is proposed based on polycrystalline silicon (polysilicon) deposited at low temperature (T⩽600°C). This structure, compatible with glass substrates, is designed to have up to 4 teeth and enables to get a high channel width W with a short channel length L. The channels of TFTC are made of a non-intentionally doped (NID) polysilicon layer between two in situ heavily-doped polysilicon layers; all these three layers are deposited by low pressure chemical vapor deposition (LPCVD) method. Electrical characteristics of TFTC show relatively high on-currents (ION) correlated with the geometric parameters. However, high off-currents (IOFF) are also observed due to the large overlapping area between drain and source regions.

P‐6: A New Integrated Scan Driver using Oxide TFTs with Negative Threshold Voltage

AbstractA new integrated scan driver composed of oxide TFTs with a negative threshold voltage is proposed for LCDs and AMOLED displays. By introducing a new circuit, which consists of two clock sets, SCLKs and PCLKs, with different low voltage levels and two DC voltage sources, VH and VL, the effect of a high off‐current of oxide TFTs at VGS = 0V was minimized and thus the scan driver showed stable operation by the negative threshold voltage of −2V. Furthermore, the proposed driver requires only two capacitors; therefore, it can be compactly implemented on a panel without additional increase of area. The operation of the proposed scan driver was fully verified by SPICE simulations.

Effect of doping of zinc oxide on the hole mobility of poly(3-hexylthiophene) in hybrid transistors

Hybrid field effect transistors based on the organic polymer poly(3-hexylthiophene) (P3HT) and inorganic zinc oxide were investigated. In this report we present one of the first studies on hybrid transistors employing one polymeric transport layer. The sol–gel processed ZnO was modified via Al doping between 0.8 and 10 at.%, which allows a systematic variation of the zinc oxide properties, i.e. electron mobility and morphology. With increasing doping level we observe on the one hand a decrease of the electron mobilities by two orders of magnitude, on the other hand doping enforces a morphological change of the zinc oxide layer which enables the infiltration of P3HT into the inorganic matrix. X-ray reflectivity (XRR) measurements confirm this significant change in the interface morphology for the various doping levels. We demonstrate that doping of ZnO is a tool to adjust the charge transport in ZnO/P3HT hybrids, using one single injecting metal (Au bottom contact) on a SiO 2 dielectric. We observe an influence of the zinc oxide layer on the hole mobility in P3HT which we can modify via Al doping of ZnO. Hence, maximum hole mobility of 5 · 10 - 4 cm 2 V - 1 s - 1 in the hybrid system with 2% Al doping. 5 at.% Al doping leads to a balanced mobility in the organic/inorganic hybrid system but also to a small on/off ratio due to high off-currents.

Orthogonal Patterning of PEDOT:PSS for Organic Electronics using Hydrofluoroether Solvents

2009 WILEY-VCH Verlag Gmb Organic electronics is an emerging technology opening new opportunities in the field of large-area electronics. It has received enormous attention as a technology platform that enables flexible, large-scale devices by exploiting the unique properties of organic materials. In addition, organic electronics offer the possibility of affordable manufacture of devices through solution processing of active materials. Before this vision is realized, several challenges must be overcome, in particular the issues of patterning. Patterning of electronic materials enables microscale device structures to be defined for organic light-emitting diode (OLED) displays and organic thin-film transistors (OTFTs). In addition, patterning enhances the device performance by preventing cross-talk, increases transconductance, and prevents high off-currents in transistor arrays or drivers. The patterning of organic materials has been demonstrated by many different methods, including ink-jet printing, vapor deposition through shadow masks, soft and hard imprint lithography, and photolithography. Ink-jet printing boasts continuous roll-to-roll process capabilities and is the patterning technique of choice for polymeric materials. However, the resolution is limited to approximately 10–20mm. Shadow mask deposition is the dominant technique for small-molecule patterning, but also has notable resolution limitations. A shadow mask feature resolution is typically 25–30mm, although special masks have shown resolution down to 5mm. Shadow-mask deposition also requires a high-vacuum environment, which can introduce further limitations. Imprint lithography has demonstrated promising results, showing feature resolution down to 10 nm. However, this technique has shown only limited applicability with respect to materials and device architectures. Furthermore, in all of the aforementioned methods, registration is an issue that renders fabrication of multilayer devices exceptionally challenging. Multilayered device architecture will be essential to achieve fully integrated circuits. Photolithography, in contrast, is a widely applicable patterning method that consistently achieves both high-resolution and registration. Photolithography has the added advantage of being the most developed patterning technology and the patterning method of choice for the current semiconductor industry. In spite of the proven technical advantages, conventional photolithography has not been recognized as a suitable technique for patterning organic electronic materials. It is presently hindered by concerns of chemical deterioration of active organic materials upon exposure to process solvents for lithography. By introducing a new set of benign processes that involve new specially tailored photopolymers, we show that this problem can be circumvented. Recently, we identified hydrofluoroethers (HFEs), a family of nontoxic and environmentally friendly solvents, as being chemically benign to nonfluorinated organic electronic materials. Not only are they benign, but HFEs are orthogonal solvents to many organic compounds, that is, the organic compounds are insoluble and are not swollen in HFEs. This is a particularly useful property in the fabrication of multilevel devices, since new layers can be added without damage to existing ones. Our challenge was, therefore, to develop compatible lithographic materials for these new process solvents. By employing a fluorinated photoresist compatible with HFEs, we demonstrate sub-micrometer photolithographic patterning of organic electronic materials. Poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) is a mechanically flexible, transparent, and highly conductive polymer blend, which has found various applications in organic electronics including serving as the electrode material for plastic substrates, because of its low-temperature processing requirements, and as charge-injection/-extraction layers in OLEDs and photovoltaic devices. However, photolithographic patterning of PEDOT:PSS for device components is not straightforward, because i) PEDOT:PSS films are damaged by aqueous solutions, which are standard developers in conventional photolithography, and ii) acid-sensitive photoresists are adversely affected by the acidic PEDOT:PSS. In this communication,wepresent a unique acid-stable imaging material for PEDOT:PSS and organic electronic materials in general. We report on the sub-micrometer patterning of PEDOT:PSS films and their subsequent application to the fabrication of a field-effect transistor, in which an organic semiconductor material, pentacene, is patterned by the same protocol. In designing a HFE-compatible photoresist, it was most important that the photoresist be soluble in fluorous solvents. In general, fluorous solvents dissolve highly fluorinated materials. The copolymer 3, derived from the highly fluorinated monomer 1 and photolabile monomer 2, was expected to yield a material that exhibits a solubility switch following UV irradiation

Suppression of Metallic Conductivity of Single-Walled Carbon Nanotubes by Cycloaddition Reactions

The high carrier mobility of films of semiconducting single-walled carbon nanotubes (SWNTs) is attractive for electronics applications, but the presence of metallic SWNTs leads to high off-currents in transistor applications. The method presented here, cycloaddition of fluorinated olefins, represents an effective approach toward converting the "as grown" commercial SWNT mats into high-mobility semiconducting tubes with high yield and without further need for carbon nanotube separation. Thin-film transistors, fabricated from percolating arrays of functionalized carbon nanotubes, exhibit mobilities >100 square centimeters per volt-second and on-off ratios of 100,000. This method should allow for the use of semiconducting carbon nanotubes in commercial electronic devices and provide a low-cost route to the fabrication of electronic inks.

Electrostatic engineering of nanotube transistors for improved performance

With decreasing device dimensions, the performance of carbon nanotube field-effect transistors (CNFETs) is limited by high OFF currents except at low drain voltages. Introducing an asymmetry between source and drain electrostatics can improve the performance, reducing OFF currents and extending the usable range of drain voltage. The improvement is most dramatic for ambipolar Schottky-barrier CNFETs. Moreover, this approach allows a single device to exhibit equally good performance as an n- or p-type transistor, by changing only the sign of the drain voltage. Even for CNFETs having ohmic contacts, an asymmetric design can greatly improve the performance for small-bandgap nanotubes.