Schottky Tunneling Effects in a Tunnel FET

Abstract

Tunnel FETs (TFETs) have attracted a great deal of attention due to their steep subthreshold swing (SS) of less than 60 mV/dec, which overcomes the theoretical constraint imposed by the thermal limit in a conventional inversion-mode (IM) FET. Based on its advantages as a short-channel device with low stand-by power consumption, TFETs shows promise to replace IM-FETs. As the channel length is shortened to minimize the total gate pitch; however, the gate sidewall spacer is miniaturized as well. In this paper, the influence of junction extension length ( $L_{\mathrm {ext}})$ on TFET behavior is discussed where the length of the gate spacer is assumed to be the gap between the source and drain (S/D) electrodes and the gate edge. It was found that, when $L_{\mathrm {ext}}$ is aggressively scaled down, having S/D electrodes (silicide or metal) with identical work functions (WFs) leads to a severely high OFF-current ( $I_{ \mathrm{\scriptscriptstyle OFF}})$ and high SS. By adopting separate asymmetric WFs for the p-type and n-type S/D electrodes, the on/off characteristics were improved with suppressed $I_{ \mathrm{\scriptscriptstyle OFF}}$ and steeper slopes. It was also shown that the device performance of a TFET with higher source-side doping concentrations ( $\sim 5\times 10^{20}$ cm−3) can be further improved even at the aggressively scaled-down $L_{\mathrm {ext}}$ by boosting the on-current.