Electrostatic engineering of nanotube transistors for improved performance

Abstract

With decreasing device dimensions, the performance of carbon nanotube field-effect transistors (CNFETs) is limited by high OFF currents except at low drain voltages. Introducing an asymmetry between source and drain electrostatics can improve the performance, reducing OFF currents and extending the usable range of drain voltage. The improvement is most dramatic for ambipolar Schottky-barrier CNFETs. Moreover, this approach allows a single device to exhibit equally good performance as an n- or p-type transistor, by changing only the sign of the drain voltage. Even for CNFETs having ohmic contacts, an asymmetric design can greatly improve the performance for small-bandgap nanotubes.