High Noise Margin Research Articles

Quantum Enhanced Josephson Junction Field-Effect Transistors for Logic Applications

The need of data centers for cloud and network computing has dramatically increased power consumption. In 2014, data centers in the U.S. consumed an estimated 70 billion kWh, representing about 1.8% of total U.S. electricity consumption [“United States Data Center Energy Usage Report," published in June 2016 and supported by the Federal Energy Management Program of the U.S. Department of Energy]. Worldwide, the International Energy Agency estimates that currently about 1% of all global electricity is used by data centers. It is expected that by 2030 the electricity use of information and communications technology may exceed 20% of all global electricity. The microelectronics industry has been focusing on aggressively shrinking the size of logic and memory devices to reduce power consumption. However, this scaling is going to eventually stop as we approach the fundamental materials limit. Moreover, the power dissipation due to the increased number of transistors is also expected to be a limiting factor for processor performance.Superconducting computing has been suggested as a promising approach for low-energy, power-efficient circuit applications. Moreover, using superconducting interconnects can further reduce power consumption. Josephson junction field-effect transistors (JJFET, Fig. a) have recently emerged as a promising candidate for superconducting computing. JJFETs are particularly useful for low power consumption applications as they are operated with, in the superconducting regime, zero voltage drop across its source and drain. Feasibility of using JJFETs for logic operations has been explored [1]. Moreover, high noise margin has been demonstrated for the logic inputs [2]. Compared to single flux quantum approach, JJFET circuits can use designs similar to conventional silicon MOSFETs [1].For JJFETs to perform logic operations, the gain-factor (αR) value must be larger than 1. Here αR = dIc/d(Vg–Vt) x πΔ/Ic, Δ is the superconducting gap, Vg the gate bias voltage, Vt the threshold voltage. Ic ∝ exp(-L/ξc) is the critical supercurrent, where L is the channel length and ξc the carrier coherence length [3]. In a conventional JJFET, ξc ∝ (Vg–Vt)0.5 (Fig. b), and thus dIc/d(Vg–Vt) is small (Fig. c). This translates to a requirement of superconducting transition temperature of ~ 400K for αR larger than 1, far exceeding any recorded critical temperatures. As such, it is impossible to use conventional JJFETs for logic operations.Here, we propose a novel type of JJFET based on quantum phase transition, such as the excitonic insulator (EI) transition in a type-II InAs/GaSb heterostructure [4,5], for low-energy, power-efficient logic applications. The nature of the collective phenomenon in the EI quantum phase transition can provide a sharp transition of the supercurrent states (e.g., ξc ∝ (Vg–Vt)5 and dIc/d(Vg–Vt) very large, as shown in Figs. b and c, respectively) which will enable αR larger than 1 with an easy-to-achieve superconducting transition temperature of ~ 40K. In this talk, we will present some preliminary results demonstrating that indeed the gain factor in these quantum enhanced JJFETs can be greatly improved, thus making them a promising candidate for logic applications.Sandia National Laboratories is a multimission laboratory managed and operated by NTESS LLC, a wholly owned subsidiary of Honeywell International Inc. for the U.S. DOE’s NNSA under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. DOE or the United States Government.

Flexible Complementary Metal‐Oxide‐Semiconductor Inverter Based on 2D p‐type WSe2 and n‐type MoS2

Transition metal dichalcogenides (TMDCs) are a promising class of two‐dimensional (2D) materials for flexible electronic applications due to their low integration temperature, good electronic properties, and excellent mechanical flexibility. Moreover, TMDCs offer the possibility of co‐integrating both n‐ and p‐type transistors on the same substrate, enabling the realization of complementary metal‐oxide‐semiconductor (CMOS) circuits. In this study, n‐type MoS2 field‐effect transistors (FETs), and p‐type WSe2‐FETs integrated on a flexible foil substrate fabricated by standard thin‐film technology are presented. These devices exhibit high stability in their electronic operation under strain and repeated bending cycles. A CMOS inverter based on these transistors is also successfully demonstrated, which shows excellent switching behaviour with high gain (up to 100), high noise margin (0.87 · VDD), and low average static power consumption (40 pW).

Negative capacitance FET based dual-split control 6T-SRAM cell design for energy efficient and robust computing-in memory architectures

A Negative Capacitance Field effet transistor (NCFET) based Dual split control (DSC) 6T-SRAM cell has been designed and explored with Computing-in memory (CiM) architecture for energy efficient demonstration of Deep neural networks (DNN) basic operation such as Input-Weight (Dot) Product. The impact of ferro electric layer thickness (Tfe) on the SRAM cell perfomance metrics such as read noise margin (RNM), write noise margin (WNM) and energy efficiency for read and write operations have been analyzed at supply voltages of 0.3 V and 0.5 V. It has been observed that due to the steep slope characteristics, the NCFET based DSC 6T-SRAM cell design exhibits better RM, WM, and energy efficiency as compared to the baseline CMOS DSC SRAM cell design at VDD = 0.3 V and 0.5 V respectively (with Tfe range of 1 nm to 3 nm). Further, NCFET dual split control scheme for 6T-SRAM cell demonstrate improved read stability and write ability when compared with NCFET 6 T-SRAM cell design along with improved energy efficiency. NCFET based DSC 6T-SRAM CiM cell design has ∼22.77× and 12.41× lower energy consumption compared to the équivalent baseline 40 nm CMOS/baseline SRAM CiM design and ∼ 25.80× and 22.76× lower energy consumption compared to the NCFET based SRAM CiM at VDD = 0.3 V and 0.5 V respectively. NCFETs have improved steep subthreshold slope characteristics at an optimal Tfe value and NCFET SRAM based CiM circuits are expected to have higher noise margins and lower energy consumption compared to the baseline CMOS designs and are effective for NCFET based computing in-memory architectures with reduced read disturb issues in combination with DSC concept.

Design and Evaluation of High-Speed Overcurrent and Short-Circuit Detection Circuits With High Noise Margin for WBG Power Semiconductor Devices

Design and Evaluation of High-Speed Overcurrent and Short-Circuit Detection Circuits With High Noise Margin for WBG Power Semiconductor Devices

Ditch incorporated organic thin film transistor based organic all-p inverter: a novel approach

This paper demonstrates the static and dynamic characteristics of all-p organic inverter employing a bottom gate bottom contact organic thin film transistor with a ditch incorporated into the OSC and additional p+ doping done to its S/D nearing area. Various configurations of OTFT have been experimented with and it is found that as compared to an OTFT without extra p+ doping, the devices having additional doping show better responses. Where, for SG OTFT, ID is derived to be 18 μs, yet the one with extra doping illustrates a swooping 16.67% increased output current of 21 μs. To enhance the performance of the device further, a ditch of 30 nm, embedded 10 nm into the OSC is incorporated, further augmenting the performance of the device by 55.5% as compared to the conventional BGBC. Besides, the proposed inverter presents a considerably elevated performance in terms of robustness and low and high noise margins. This paper further compares the inverter using Diode Load Logic and Zero Vgs Load Logic topologies, wherein it was found that DLL shows an exceptional 211% less propagation delay τ p of 27 μs, as compared to 84 μs delay experienced by ZVLL. But comparing the two topologies in terms of the static response, ZVLL are way better and preferred over the counterparts since ZVLL configuration displays 20.5% augmented Noise Margin, improved gain, and overall robustness. Owing to the performance parameters achieved, such organic inverters may be incorporated into integrated circuits rendering trustworthiness to digital operations in electronic circuits and numerous cascading applications. Since the organic inverters made using the proposed OTFT exhibit a decent gain hence have an apparent prospective of driving myriad-stage logic like ring oscillators and memory blocks. Moreover, these may be employed in the areas of biosensors and wearable electronics as well wherever.

DC and AC characteristics of Si/SiGe based vertically stacked complementary-tunneling FETs

In this paper, electrical characteristics of a complementary tunneling field effect transistor (CTFET) is studied computationally for the first time. The design of CTFET is carried with 3D vertically stacked channels (multiple) of n-TFET on top of the p-TFET with gate-all-around (GAA) nanosheet SiGe options. The CTFET technology (using CFETs) is examined for emerging technology nodes as a potential alternative to conventional TFETs. Here, the device level design of CTFET is strictly monitored with DC characteristic behavior under the influence of process variability conditions (traps and temperature). The performance analysis is extended to analyze the scalability of CTFET under critical dimensions (n- to p-TFET separation, nanosheet pitch, and so on), and find that it is highly scalable. The circuit analysis of CTFET-inverter show high-noise margin (NM) and voltage gains compared to the conventional strained-Si GAA-TFETs at the supply range (V D D) from 0.7 ≥ V D D ≥ 0.2 V. In addition, the CTFET-inverter circuit performance is analyzed with miller capacitance, power delay product, and intrinsic delay, respectively. Improved circuit performance, followed by 12.5% and 21.5% improvements in low and high NMs (NML and NMH) are seen in CTFETs compared to conventional TFETs.

Highly Stable Ladder‐Type Conjugated Polymer Based Organic Electrochemical Transistors for Low Power and Signal Processing‐Free Surface Electromyogram Triggered Robotic Hand Control

AbstractOrganic electrochemical transistors (OECTs) based complementary inverters have been considered as promising candidates in electrophysiological amplification, owing to their low power consumption, and high gain. To create complementary inverters, it is important to use highly stable p‐type and n‐type polymers with well‐balanced current. In this study, the electrochemical stability of p‐type ladder‐conjugated polymer‐based OECT is improved through an annealing process that maintains its doped‐state drain current from 76% to 105% after 4,500 cycles in ambient environment. Next an OECT‐based complementary inverter made from p‐type and n‐type ladder‐conjugated polymers (PBBTL and BBL) that possess ultra‐low power consumption (≈170 nW), high gain (67 V/V), and high noise margin (92%) with full rail‐to‐rail swing, is presented. Furthermore, its potential for amplifying the envelope of surface electromyography (EMG) for robotic hand control is demonstrated. The high variation in the output (0.35 V) allows the amplified EMG signals to be directly captured by a commercial analog‐to‐digital converter, which in turn controls the robot hand to grasp different objects with low delay and low noise. These results demonstrate the capability of OECT inverter‐based amplifier in future signal processing‐free human‐machine interface, particularly useful for prosthetic control and gesture control applications.

A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors

A new type of heterojunction non-volatile memory transistor (H-MTR) has been developed, in which the negative transconductance (NTC) characteristics can be controlled systematically by a drain-aligned floating gate. In the H-MTR, a reliable transition between N-shaped transfer curves with distinct NTC and monolithically current-increasing transfer curves without apparent NTC can be accomplished through programming operation. Based on the H-MTR, a binary/ternary reconfigurable logic inverter (R-inverter) has been successfully implemented, which showed an unprecedentedly high static noise margin of 85% for binary logic operation and 59% for ternary logic operation, as well as long-term stability and outstanding cycle endurance. Furthermore, a ternary/binary dynamic logic conversion-in-memory has been demonstrated using a serially-connected R-inverter chain. The ternary/binary dynamic logic conversion-in-memory could generate three different output logic sequences for the same input signal in three logic levels, which is a new logic computing method that has never been presented before.

Active loaded source-coupled logic: Applications and performance comparison

In this paper, we provide an extensive analysis of the newly introduced Active Loaded Source-Coupled Logic (ALSCL) family, which is a single-ended type of logic gate family with source-coupled circuit working principles. The proposed source-coupled logic family has analog-friendly behavior similar to previous source-coupled logic circuits, however, the proposed circuit structure has a simpler design methodology with high noise margins and robust characteristics to the device sizing, process variations, and temperature. Circuit design principles of the proposed ALSCL circuits are described, and performance analysis of various implementations is evaluated. The proposed logic circuit structure performance is tested using 0.18 µm technology with extensive simulations. The proposed logic family has simpler routing requirements compared to classical source-coupled circuits. The proposed circuit structure is functional without fine adjustment of the device sizing and the performance can be tuned by the bias current of the circuits, providing a wide range of performance characteristics with the trade-off for power consumption.

Design of SEU and DNU‐resistant SRAM cells based on polarity reinforcement feature

SummaryAs the scale of the integrated circuit increases, the distance between transistors decreases, a trend that reduces the critical charge of the sensitive nodes of the memory cell. Consequently, Static Random Access Memory cells in high radiation environments are very prone to soft errors. A novel radiation‐hardened memory cell, the Polarity Reinforcement Feature (PRF)‐18T, is proposed in this paper, which uses the polarity reinforcement feature to reduce the number of sensitive nodes in the memory cell and can entirely and effectively tolerate single event upset and double node upset. A comparison is made in this paper with DICE‐12T, Quatro‐10T, SEA‐14T, RHBD‐14T, NASA‐13T, and SCCS‐18T memory cells in a simulation environment with Semiconductor Manufacturing International Corporation 55 nm process, the supply voltage of 1.2 V, and temperature of 25°C. In comparison, the PRF‐18T proposed in this paper has the highest critical charge value, improving by more than 15× and 3.1× compared to the DICE‐12T and RHBD‐14T, respectively, and by more than 79% and 17.6% compared to the Quatro‐10T and SEA‐14T, respectively. In the high hold static noise margin comparison, the improvement over the SEA‐14T, DICE‐12T, RHBD‐14T, and Quatro‐10T is 26.7%, 3.8×, 1.5×, and 1.2×, respectively. In the write static noise margin comparison, the results were similar to the Quatro‐10T, DICE‐12T, and SEA‐14T, with a 68.5% improvement compared to the RHBD‐14T. Finally, the robustness of the proposed cell to process, voltage, and temperature variations is verified by temperature change experiments and 2000 Monte Carlo model simulations.

Integrated Low‐Dimensional Semiconductors for Scalable Low‐power CMOS Logic

AbstractScalable nanoelectronics with energy‐efficient logic technology is crucial for next‐generation edge devices. Low‐dimensional semiconductors, such as transition metal dichalcogenides and single‐walled carbon nanotubes (SWCNTs), have tunable properties with reduced short‐channel effects. The unique properties of each material can be utilized owing to the heterogeneous integration of multiple semiconducting channels to form complementary metal‐oxide‐semiconductor (CMOS) logic. However, the integration remains challenging. This study reveals the realization of low static power hetero‐CMOS inverters by the integration of n‐type monolayer MoS2 and p‐type SWCNT networks. The balanced inverter exhibits a large peak gain of ≈67 at a supply voltage of 2 V with the customized design of the wafer‐scale synthetic process and channel integration. An ultralow standby power consumption of ≈5 pW and a practical peak gain of ≈7 at a reduced supply voltage of 0.25 V are achieved. A high noise margin (>70%) validates the circuit's tolerance to external noises and the dynamic analysis of the inverting amplifier in push–pull configuration exhibits a large AC gain. This work paves the way toward the wafer‐scale integration of low‐dimensional materials for low‐power nanoelectronics.

Fully solution-processed carbon nanotubes thin film transistors and PMOS inverters on glass substrate

We report fully solution-processed thin film transistors and PMOS inverters fabricated on glass substrates using single-walled carbon nanotubes (SWCNTs) as active semiconducting material. All the electrodes (gate, source, and drain) were inkjet-printed using silver (Ag) as conductive ink. Spin coated poly-4-vinylphenol dielectric was optimized in terms of thickness and heating conditions for solution-processed SWCNTs thin film transistors to achieve a mobility equal to 0.81 cm2 V−1s−1. We will show that, hole traps at the dielectric-semiconductor interface are responsible for the hysteresis in the transfer curve, and controlled by the different sweep rate of the gate field. Drain-current transients under different bias conditions were studied and the increase in current occurs due to slow polarizations of residual dipolar groups in the dielectric. The adopted technology has been exploited to fabricate a PMOS inverter and studied for high gain and noise margin values at the supply voltage, V DD = −40 V.

Design of highly reliable radiation hardened 10T SRAM cell for low voltage applications

With growing interest in near-threshold voltage regime (NTV) to make energy-efficient circuits, their operation has become less reliable and prone to errors. A soft error is one of the significant reliability concerns in Static random access memories (SRAM) cells, and due to technology scaling, the sensitivity of these SRAM cells to soft errors has increased. The SRAM memories are more susceptible to the radiation effects, mainly Single Event Upsets (SEU). This paper presents a 10T SRAM cell, which gives an energy-efficient operation with high noise margins and is radiation hardened by design. We implement the novel memory cell in an industrial 65-nm CMOS technology and ASAP7 7-nm Fin-FET technology in the NTV regime. The proposed memory cell reduces the area overhead from the QUCCE10T and QUCCE12T cells by 12% and 25% in 65-nm technology. In 65- nm technology, the proposed SRAM cell significantly improves HSNM/RSNM by 24/14% over the recently reported RHPD12T cell with nearly equal WSNM. We also verify the radiation hardness of the proposed memory cell in 32- nm CMOS technology using TCAD simulations. In 32-nm technology, the proposed SRAM cell provides radiation hardness up to the value of LET = 35 MeV cm2/mg.

Design of High Stability and Low Power 7T SRAM Cell in 32-NM CNTFET Technology

A novel 7T carbon nanotube field effect transistor (CNTFET)-based static random-access memory (SRAM) cell is proposed in this paper. Power and noise margin performances of the proposed SRAM cell is observed for write, hold and read operations. The power consumption and noise margin of the proposed SRAM cell is compared with the conventional 6T and 8T CNTFET-based SRAM cells. From the simulation, it is noted that the proposed 7T SRAM cell consumes lesser power and offers high static noise margin (SNM) compared to that of conventional 6T and 8T SRAM cells. The introduction of diode-based transistor structure improves the power and noise performance of the proposed SRAM cell. The effect of variation of parameters such as gate oxide thickness, dielectric constant, pitch, temperature, number of carbon nanotubes (CNT) and supply voltage on power and noise performance of proposed 7T SRAM cell is studied. Simulations were carried out with HSPICE simulation tool using Stanford University 32-nm CNTFET model.

Drain-Engineered Reconfigurable Transistor Exhibiting Complementary Operation

In this paper, we propose and simulate a multifunctional transistor that exhibits device reconfigurability and realizes both nFET and pFET electrical characteristics when adequately biased. The use of this device will significantly reduce the transistor count in realizing sequential and combinational circuits and will result in highly compact design. The device uses a dual fin structure having a single mid-gap workfunction gate (\(\sim \)4.65 eV) alongside dual metal (metal-silicide) drain regions. It employs n+/p+-i junctions at the source-channel interface along with the Schottky junctions at the channel-drain interface. In practice, metal-silicides such as erbium/ytterbium silicide (ErSix/YbSix) for the n-drain and platinum silicide (PtSi) for the p-drain can be used as they provide smallest electron and hole Schottky-barrier heights (SBHs). Simulations carried out using calibrated parameters show better drive current (≈ 10− 2 − 10− 3A/μ m) compared to the quantum tunneling current in simulated state-of-the-art multifunctional devices (≈ 10− 4 − 10− 5A/μ m). In addition, butterfly curves show symmetric high (NMH) and low (NML) noise margins of 0.43V and 0.29V for zero and finite SBHs, respectively. The switching characteristics is shown to have an overshoot of \(\sim \)0.15 V for realistic SBHs which is then eliminated for the case of zero SBHs. In the last section, it is also demonstrated that a simplified structure having single mid-gap workfunction (\(\sim \)4.65 eV) drain of Nickel silicide (NiSi) does not hamper the reconfigurability of the device.

Schmitt Trigger Designs Using Domino Logic Style

The advancements in the VLSI regime at lower technology node necessitate robust circuit design. Schmitt trigger design using domino logic style exhibit better hysteresis, higher noise margin, and reduced power consumption while compared to static CMOS Schmitt trigger design. This paper proposes three different Schmitt trigger designs based on domino logic style which produces a stable output with increased robustness against noise. The evaluation of dynamic logic-based Schmitt trigger using only NMOS transistors makes high speed operation feasible with reduced power consumption and increased hysteresis. The design, simulation, and analysis of the circuits are performed using Cadence Virtuoso using GPDK 180 nm technology library.

A Novel STT–SOT MTJ-Based Nonvolatile SRAM for Power Gating Applications

This article proposes novel nonvolatile (NV) static random access memory (SRAM) circuits based on spin transfer torque (STT) and spin orbit torque (SOT) operated magnetic tunnel junction (MTJ) device for energy-efficient power gating circuits. In which, two different designs of 9T-2MTJs and 10T-2MTJ-based NV SRAM circuits are proposed for low power, high noise margin, and faster switching speed with less area overhead. The proposed architecture uses a smaller number of transistor combinations to accommodate low-power operation with compact cell size when compared with available pieces of literature. Also, the combination of nMOS and pMOS transistors in the proposed architecture enhances the driving capability of the circuit for both low and high input operations. Here, the electrical characteristics of the proposed designs have been compared and contrasted with the available 11T-2MTJ and 7T-2D-2MTJ non volatile static random access memory (NVSRAM) and 6T SRAM circuits using a UMC-40 nm design kit and physics-based STT–SOT MTJ Verilog-A Model. The proposed 9T-2MTJ-based NVSRAM was found to be a better alternative and offers improved performance in terms of higher restore noise margin and lower power consumption than other circuits reported at this node. Moreover, the studied 10T-2MTJ exhibits an improved write and hold noise margin than the proposed/available 9T/7T-2D/11T-2MTJ circuits.

Digital Circuit Performance Evaluation of Parallel Gated Junctionless Field Effect Transistor

This paper reports the modeling and performance enhancement of complementary metal-oxide-semiconductor (CMOS) inverters using parallel-gated junctionless field-effect transistors (PGJLFET). A mathematical model for different parameters, namely, low and high input voltage, low and high output voltage, noise margin, rise time, fall time, propagation delay, and power dissipation of the inverter circuit was established. To establish the model for various parameters, potential models at the source-channel boundary and the potential at the drain-channel boundary are considered. The variations in the voltage transfer characteristics of the output current with respect to the input voltage and the power dissipation with respect to the input voltage for steady-state conditions and transient states were investigated for different gate dielectrics, gap lengths, and gate oxide thicknesses. The models were validated by comparing them with technology computer-aided design (TCAD) simulation results. The noise margin, rise time, fall time, and propagation delay of the PGJLFET-based inverter are estimated and compared with those of a conventional junctionless transistor. It has been observed that the PGJLFET exhibits an improvement in the noise margin and propagation delay compared with conventional junctionless transistors.

High-performance multivalued logic circuits based on optically tunable antiambipolar transistors

A high-performance organic ternary logic circuit is developed. High carrier mobilities of the organic semiconductors and their contrasting photoresponse achieved a full-swing operation, optical controllability and high noise margin in the devices.

Systematic Control of Negative Transconductance in Organic Heterojunction Transistor for High-Performance, Low-Power Flexible Ternary Logic Circuits.

Organic multi-valued logic (MVL) circuits can substantially improve the data processing efficiency in highly advanced wearable electronics. Organic ternary logic circuits can be implemented by utilizing the negative transconductance (NTC) of heterojunction transistors (H-TRs). To achieve high-performance organic ternary logic circuits, the range of NTC in H-TRs must be optimized in advance to ensure the well-defined intermediate logic state in ternary logic inverters (T-inverters). Herein, a simple and efficient strategy, which enables the systematic control of the range and position of NTC in H-TRs is presented. Each thickness of p-/n-type semiconductor in H-TRs is adjusted to control the channel conductivity. Furthermore, asymmetric source/drain (S/D) electrode structure is newly developed for H-TRs, which can adjust the amount of hole and electron injection, independently. Based on the semiconductor thickness variation and asymmetric S/D electrodes, the T-inverter exhibits full-swing operation with three distinguishable logic states, resulting in unprecedentedly high static noise margin (≈48% of the ideal value). Moreover, a flexible T-inverter with an ultrathin polymer dielectric is demonstrated, whose operating voltage is less than 8V. The proposed strategy is fully compatible with the conventional integrated circuit design, which is highly desirable for broad applicability and scalability for various types of T-inverter production.