High Mobility Channel Materials Research Articles

Bi-directional threshold voltage shift of amorphous InGaZnO thin film transistors under alternating bias stress

Amorphous InGaZnO (a-IGZO) has attracted a lot of attention as a high-mobility channel material for thin film transistors (TFTs). However, the instability mechanism involving threshold voltage and subthreshold swing (SS) in a-IGZO TFTs still requires further investigation. In this study, we investigated the electrical instability of amorphous InGaZnO TFTs subjected to alternating positive and negative bias stresses. Based on the respective mechanisms under positive and negative bias stresses, including ionization and spatial movement of oxygen vacancies, bi-directional threshold voltage shifts were observed under alternating bias stress. The SS values vary with the bias stress polarity, reflecting the presence and distribution of oxygen vacancies. Our findings reveal a complementary mechanism based on oxygen vacancies, elucidating the behavior under complex bias stress schemes and extending our understanding of instability mechanisms beyond monotonous bias stress.

(Invited) Stacking High Mobility Channels

Beyond 3 nm node, the transistor architecture of stacked channel gate-all-around (GAA) FETs can replace FinFETs for advanced technology node due to the improvement of power, performance, and area by the enhanced short channel control, design flexibility, and drive current per footprint. High ION and small parasitic RC are the keys to extend nanosheet technologies for N+1 and N+2 nodes. To extend nanosheets to next nodes, we have demonstrated additional enabling knobs such as high mobility channels, high-k gate dielectrics, and highly stacked channels to effectively increase the ION for high performance. Beyond stacked nanosheets, new transistor architectures such as TreeFET (a combination of FinFET and stacked nanosheets) and CFET (3D stacked n and p FETs) can further enable cell height scaling. CFETs and atomic channels have potentials to be used in A5 and A2 nodes according to the transistor roadmap by IMEC [1], respectively. Note that ultrathin body as thin as 1 nm can be considered as atomic channels for nearly ideal SS and high ION/IOFF for low power application.First of all, high mobility channel material is the key factor to improve performance CV/I. As a result, Ge/GeSi and GeSn are the target high mobility channels for nFETs and pFETs, respectively. For nFETs, Ge is an attractive option for high mobility channel to boost the ION thanks to its higher electron mobility than Si [2]. For pFETs, strained GeSn has higher hole mobility than Ge to improve the ION for pFETs due to the hole effective mass reduction under compressive strain [3]. For a fixed footprint, the vertically highly stacked GAA channels can provide large ION to achieve high performance and area scaling for advanced technology node.In addition to high mobility channel, the performance of GAAFET can be improved by scaling down gate oxide thickness. However, the gate leakage problem increases with scaling down the gate oxide thickness. As a result, high-k materials were proposed as gate oxide for gate leakage reduction and performance enhancement in GAAFETs. Plasma-enhanced atomic layer deposition (PEALD) HfxZryO2 was reported to achieve high-k value by optimizing the Hf and Zr content [4], respectively. In this work, a high k value of 47 is achieved in Hf0.2Zr0.8O2 alloy. Furthermore, the high-k gate dielectrics is integrated into stacked GAAFETs successfully.However, the challenge of Ge-based channel is the large IOFF due to the small bandgap [5-7]. Ultrathin body device can effectively reduce the IOFF, but the mobility degradation is observed as the channel thickness decreases below 5nm due to surface roughness scattering. Moreover, the high mobility GeSn can afford some mobility loss due to the ultrathin body [8]. Furthermore, the ION can be further improved by channel stacking with the suppression of IOFF by the ultrathin body.For Si nanosheets, the mismatch between hole mobility and electron mobility in nanosheets [9] might lead to potential design challenges of CMOS. As a result, the TreeFET transistor architecture combining with FinFETs and stacked nanosheets is proposed [10] and experimentally demonstrated [11] as a candidate beyond nanosheets. TreeFETs with {100} surfaces can enhance the electron mobility of Si, while {110} sidewalls are beneficial to hole mobility for both Si and Ge. TreeFETs with additional fin interbridges (IB) between nanosheets can increase Weff and enhance ION per footprint for high-performance devices beyond FinFETs and stacked nanosheets.3D transistor stacking can enable further cell height scaling and extend Moore's law scaling. The pFET and nFET are able to fold on each other to reduce 50% of inverter cell area ideally in CFET [12, 13], as a promising transistor architecture beyond stacked nanosheets. As compared to the sequential 3D process, no wafer bonding or layer transfer is required in the monolithic 3D process. Moreover, monolithic 3D by epitaxy can reduce the FEOL cost and the parasitic RC as compared to sequential 3D. The high mobility channel material of GeSi is used for CFET demonstration in this work [14]. Heavily doped sacrificial layers are beneficial for S/D resistance reduction by thermal annealing during the device fabrication. Reportedly, dielectric layers in S/D regions are used for the electrical isolation between n/p FETs in CFET structure [15], but the complicated S/D recess and dual S/D selective epi regrowth are required. In this work, a simple process without S/D selective epi regrowth can achieve self-aligned CFETs with multiple P/N junction isolation to effectively reduce the leakage current. Acknowledgements- This work is supported by National Science and Technology Council (111-2218-E-002-040-MBK, 111-2634-F-A49-008-, and 111-2622-8-002-001-), Ministry of Education (NTU-CC-112L890901), and Taiwan Semiconductor Research Institute (TSRI), Taiwan. Figure 1

Vertical GeSn nanowire MOSFETs for CMOS beyond silicon

The continued downscaling of silicon CMOS technology presents challenges for achieving the required low power consumption. While high mobility channel materials hold promise for improved device performance at low power levels, a material system which enables both high mobility n-FETs and p-FETs, that is compatible with Si technology and can be readily integrated into existing fabrication lines is required. Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET transconductance is increased to 850 µS/µm by exploiting the small band gap of GeSn as source yielding high injection velocities, the mobility in n-FETs is increased 2.5-fold compared to a Ge reference device, by using GeSn as channel material. The potential of the material system for a future beyond Si CMOS logic and quantum computing applications is demonstrated via a GeSn inverter and steep switching at cryogenic temperatures, respectively.

(Invited) Electrical Performance Improvement in 300mm Ge-Based Devices

As device feature size continues to scale, new device architecture and dielectric materials with engineered properties are becoming essential in overcoming the issues in scaled CMOS devices such as short channel effects. Some of the recent innovations device makers are exploring for better electrostatic control and improved performance are the introduction of new device architecture such as gate all around devices (nanowires/nanosheets), and channel engineering such as high mobility channel materials (Ge and III-V). Ge is particularly attractive for use as a channel material for P-type MOSFETs due to its high hole mobility and Si VLSI high volume manufacturing (HVM) compatibility. However, there are couple significant remaining challenges to integrating Ge into 300mm Si VLSI HVM which are a stable gate-stack formation and integration of Ge on Si (1-5). In this talk, advances in Ge gate stack engineering will be discussed. Using Si compatible technologies we have demonstrated scaled EOT by engineering both the interface and high-k formation. Reference Swaminathan, Y. Oshima, M. Kelly, P.C. McIntyre, Appl. Phys. Lett., 95, 032907 (2009).Zhang, M. Gunji, S. Thombare, P.C. McIntyre, IEEE Electr. Device. L., 34, 736 (2013).H Lee, T. Nishimura, C. Lu, S. Kabuyanagi, A. Toriumi, IEDM, 32.5.1 (2014).S. Goley, M. K. Hudait, Materials, 2301 (2014).Xie, S. Deng, M. Shaekers, D. Lin, M. Caymax, A. Delabie, X-P Qu, Y-L. Jiang, D. Dedytsche, C. Detavernier, Semicond. Sci. Technol. 074012 (2012)

(Invited) Interface Treatment Related Defects During Ge Gate Stack Formation

Germanium as a high mobility channel material is currently of considerable interest since Ge has both higher electron and hole mobility as compared to silicon (1). The deposition of high-k dielectrics on Ge has been a significant challenge because of high interface defects density, Dit (2). By considering the interface reaction kinetics, thermal budget various atomic layer deposition (ALD) schemes and interface treatments can be identified to get a stable dielectric with a robust interface. However, understanding of the interface kinetics and defect distribution into gate stack and/or Ge is still limited.In this work, we report the impact of different interface treatments on the p type Ge prior to any high-k layer deposition on defect generation. Ge surface was oxidized by a controlled chemical oxidation, slot-plane-antenna plasma oxidation and oxidation through vapor O3 treatment before ALD deposition of 1nm Al2O3/3.5nm ZrO2 for gate stack formation. These devices were characterized to evaluate the interface and possible bulk defects by deep level transient spectroscopy (DLTS), capacitance spectroscopy, conductance method in addition to standard I-V and C-V measurements. DLTS has the advantage to have the spectrum comparison among the interface treatments. Signature of these spectra can reveal the difference, which is more accurate than the defects estimated by Conductance method. DLTS also provides the signature of slow traps (~1ms) (Fig. 1) originating from the bulk or interface depending on the type of GeOx formation.Furthermore, we evaluate the defect distribution when the gate stack was subjected to a slot-plane antenna plasma oxidation prior to metal deposition. A TiN/Hf1-xZrxO2/Al2O3/Ge gate stack with six different Zr content was investigated (Fig. 2). Al2O3 was used to impede the Ge diffusion into the gate stack. Interface state density (Dit) and C-V hysteresis show that the mid-gap Dit tend to increase with decrease in EOT, possibly due to the undesirable native oxide formation on Ge.The author would like to thank Drs. Y.M. Ding (Western Digital Corporation, Shanghai, China), M.N. Bhuyian (Globalfoundries, Malta, NY, USA), K.L. Ganapathi (Indian Institute of Technology Madras, India), N. Bhat, (Indian Institute of Science, Bangalore, India) and K. Tapily, R. D. Clark, S. Consiglio, C. S. Wajda, G. Nakamura, and G. J. Leusink of TEL Technology Center, America, Albany, NY, for their help in this work. References Arimura et al, IEDM Technical Digest, (2020)N. Bhuyian et al, ECS Journal of Solid-St. Sci. and Tech., vol. 7(2), N1-N6, (2018)G. Kolla et al, J. Vac. Sci. Technol. B, 36(2), 021201 (2018)Ding et al, IEEE Trans. on Dev. and Materials Reliability, 17(2), 349-354, (2017)Ding, et al, J. of Vac. Sci. and Technol. B, 34(2), 021203, 2016. Figure 1

(Invited) Defect Engineering for Monolithic Integration of III-V Semiconductors on Silicon Substrates

Implementation of high-mobility channel materials enables to increase the device performance due to the higher carrier mobility compared to silicon devices. III-V based materials such as GaAs and ternary systems (e.g. InxGa1-xAs alloys) are achieving high performing n-channel transistors. The strong progress in hetero-epitaxy using nano ridge engineering [1] leading to monolithic heterogeneous integration of III-V materials on silicon substrates resulted in state-of-the-art FinFETs, gate-all-around (GAA) and horizontal or vertical stacked nanowires (NW) on 300 mm Si wafers [2,3]. Very promising results have also been reported for GaN on Si triggering their use for high power and RF applications [4].One of the main challenges remains a good defect control in order not to degrade the electrical performance of devices and circuits [5]. The nucleation of extended defects is directly related to the hetero-epitaxial growth of layers with a lattice mismatch and their concentration depends on the composition of the layers such as e.g. the In content in InxGa1-xAs and the Al content in AlxGa1-xN. The defects have a direct impact on the generation and recombination lifetime and the leakage current [5], while also the low frequency noise (LFN) performance is influenced [6]. The identification of the defects (energy level ET, capture cross section and concentration) can be determined using Deep Level Transient Spectroscopy (DLTS) and low frequency noise spectroscopy by measuring LFN as a function of temperature.The goal of this work is to review the knowledge about defect engineering and to analyze the electrical activity of extended defects in III-V semiconductors on silicon substrates. Different case studies will be used to illustrate both the defect identification and the electrical activity of the defects. The impact of the used processing schemes to fabricate the devices is also discussed. It will e.g. be shown that defects in GaN/AlGaN MOSHEMTs increase the low frequency noise due to generation-recombination centers in the GaN depletion layer [7]. These traps can lead to a distortion of the current-voltage characteristics of short channel devices. DLTS studies are a powerful tool to identify traps and to investigate their impact on the leakage current of III-V on Si devices. Double correlation DLTS investigations on GaAs/InGaP/GaAs diodes pointed out that traps associated with sidewall interface states can dominate the peripheral diode leakage current. The focus of the presentation will be on the current understanding of defect engineering associated with the monolithic integration of III-V materials on Si and a discussion of recent results concerning the electrical activity of the defects and the defect modeling.[1] M. Baryshnikova et al., Crystals, 10, 330 (2020).[2] X. Sun et al., Digest VLSI Technology, T3-4 (2017).[3] A.P. Milemin et al., Microelectron. Eng., 192, 14 (2019).[4] L. Li et al., IEEE Electron Device Lett., 41, 689 (2020).[5] C. Claeys et al., ECS Solid State Electronics, 9, 03301 (2020).[6] C. Claeys et al., J. Phys. Cond. Ser., 1190, 012001 (2019).[7] K. Takakura et al., IEEE Trans. Electron Dev., 67, 3062 (2020).

A Comprehensive Benchmarking Method for the Net Combination of Mobility Enhancement and Density-of-States Bottleneck

In this letter, we propose a comprehensive benchmarking method to simultaneously address mobility enhancement and density-of-states bottleneck in advanced field-effect-transistors (FETs) with novel high-mobility (high-μ) channel materials, where we focused on conventional covalent bonding semiconductors with pure and partially ionic character. This method relies only on the measured extrinsic transconductance of a long-channel FET in the saturation regime together with the source resistance, yielding the product of the effective mobility ( μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) and effective gate capacitance ( C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_eff</sub> ). We tested this method in In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> As quantum-well high-electron-mobility transistors (HEMTs) with various indium mole fractions, such as 0.53, 0.7, 0.8 and 1, as well as in Si n-FETs. We found that the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> As HEMTs with μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> over 10,000 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s at 300 K provided more than 20 times greater μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ×C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_eff</sub> than Si n-FETs. More specifically, the product initially improved as x increased, then showed a peak value of 10,300 μF·V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ·s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> at x of around 0.8, and degraded slightly beyond that composition. To verify the validness of the proposed method, we separately measured and analyzed C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_eff</sub> and μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> using the split-CV technique, showing excellent agreement with the ones from the proposed method.

Mobility enhancement techniques for Ge and GeSn MOSFETs

The performance enhancement of conventional Si MOSFETs through device scaling is becoming increasingly difficult. The application of high mobility channel materials is one of the most promising solutions to overcome the bottleneck. The Ge and GeSn channels attract a lot of interest as the alternative channel materials, not only because of the high carrier mobility but also the superior compatibility with typical Si CMOS technology. In this paper, the recent progress of high mobility Ge and GeSn MOSFETs has been investigated, providing feasible approaches to improve the performance of Ge and GeSn devices for future CMOS technologies.

Formation and Evaluation of Al2O3 Layer By Direct ALD on Epitaxial SiGe

In recent years, SiGe and Ge have drawn considerable attention as a high mobility channel material toward next-generation complementary metal-oxide-semiconductor (CMOS) circuits. In particular, by inducing strain into Ge using Ge/SiGe hetero-structure, highly enhanced mobility which greatly exceed the bulk mobility have been reported [1]. In order to obtain high mobility, it is necessary to generate larger strain. As one of the methods, strained SiGe on Ge-on-Si is expected. In addition, in order to realize a high mobility SiGe channel MOSFET, it is necessary to form the high-quality gate stacks and interfaces between a gate insulator film and a SiGe surface. In fact, the use of atomic layer deposition (ALD) or plasma oxidation has provided a high quality interface between Ge and the insulator film [2, 3]. However, unlike Si, wet cleaning of Ge or hydrofluoric acid treatment does not provide a high-quality hydrogen-terminated surface, and there is concern about surface oxidation and impurity adsorption. Therefore, we have attempted direct ALD on epitaxially grown Ge and reported that the Ge/Al2O3 interface properties are improved [4]. In the case of SiGe, a high-quality hydrogen-terminated surface cannot be obtained by wet cleaning or hydrofluoric acid treatment. For this reason, oxidation or impurity adsorption on the SiGe surface is feared. In this study, for the application to strained SiGe channel MOSFET, an Al2O3 film was formed using ALD on epitaxially grown SiGe as a gate stack structure on SiGe, and the interface structure was evaluated.Two types of samples were prepared by two methods. An n-type Ge (100) substrate was used in this study. The Ge substrate was chemically cleaned with NH4OH solution and followed by a HF dip and de-ionized water rinse. The wet-cleaned Ge substrate was loaded into an MBE chamber and subjected to thermal cleaning at 600 °C for 10 min. Subsequently, a 50 nm thick SiGe layer (called epi-SiGe hereafter) was hetero-epitaxially grown on the Ge substrate at 300 °C. The as-grown sample was subsequently transferred to the vacuum-connected ALD chamber and an Al2O3 film was deposited by ALD (Sample (A)). For comparison, after the epitaxial growth of the SiGe, the sample was once taken out from the chamber and exposed to the atmosphere for 5 min. The sample was then reloaded into the ALD chamber and an Al2O3 film was deposited (sample (B)). ALD of Al2O3 films was carried out for 20 cycles with precursors of TMA and H2O at a substrate temperature of 300 °C. Chemical bonding states were examined by x-ray photoelectron spectroscopy (XPS) using an ESCA-300 manufactured by Scienta Instruments AB.According to figs.1 (a) and (b), it was confirmed that the GeOx peak of the sample (A) transferred in a vacuum was significantly smaller than that of the sample (B) once exposed to the atmosphere. In particular, almost no Ge4+ peak [5] arising from Ge in GeO2 was observed, indicating that oxidation of Ge was suppressed by transport in vacuum. It is considered that the GeOx peak in the sample (A) is derived from the interface between Al2O3 and SiGe. According to figs.1 (c) and (d), no Si4+ component (binding energy range 102eV to 104eV) is found in the Si 2p 3/2 spectrum of the sample (A) transferred in a vacuum. In summary, XPS analyses reveal that formation of GeO2 and SiO2 by natural oxidation can be almost avoided by ALD on the epitaxial SiGe, and it is indicated that the Al2O3/SiGe interface created does not contain the interfacial GeO2 layer which is present for the sample exposed to the air before ALD. These results clearly indicate that the direct ALD on epitaxial SiGe is very promising way to highly improve the SiGe MOSFET performances.AcknowledgmentsThis work was partly supported by the MEXT Supported Program for the Strategic Research Foundation at Private Universities 2015–2019, a Grant-in-Aid for Scientific Research from MEXT and Interdisciplinary Research Center for Nano Science and Technology in Tokyo City University.

(Invited) Epitaxial Growth of Ge/III-V Films and Hetero-Layer Lift-off for Ultra-Thin GeOI Fabrication

Monolithic 3D (M3D) integration has been thought of as an attractive idea to realize multi-functional heterogeneous integration devices. M3D integration enables us to combine logic devices with different functional devices such as memory, sensor, or optics to create extremely compact and efficient system-on-chips. Ge and III-V compound semiconductors are expected to be implemented as high mobility channel materials and optical components which cannot be realized with Si. The layer transfer technique with low processing temperature has great potential for stacking non-lattice-matched crystalline materials for M3D ICs. Here, we discuss the layer transfer technology utilizing high quality epitaxial growth, low-temperature direct bonding and advanced epitaxial lift-off (ELO) process, which reveals the applicability of transferred layers for heterogeneous integration.The low temperature ELO process is essential for realizing reliable layer transfer with different materials because the process is almost free from the issues of thermal expansion mismatch. Process flow of GaAs or Ge layer transfer with ELO process is described in Fig. 1. First of all, a lattice-matched single crystal GaAs or Ge layer is epitaxially grown on GaAs substrate with an AlAs release layer by MOCVD. Subsequently, Al2O3 layer is deposited on the epitaxial layer by atomic layer deposition (ALD). ALD Al2O3 layer serves as the buried oxide (BOX) and the passivation layer for Ge or GaAs surface. Then, Ge or GaAs layer is patterned using photolithography. The patterned GaAs or Ge/AlAs/GaAs donor wafer is then bonded on host substrate by direct bonding technique with wet activation process. Finally, the epitaxial GaAs or Ge layer is transferred on host substrates by splitting GaAs donor wafer from AlAs layer with HCl side etching thanks to extremely high etching selectivity. Note that the fabrication of patterned transfer layer is effective in shortening the required time of ELO process. In this ELO process, the thickness of a transferred layer can be control by epitaxial layer thickness. After the layer transfer process, the released donor GaAs wafer can be reclaimed and reused for the subsequent re-epitaxial growth to reduce the process cost.Figs. 2 (a) and (b) show cross-sectional SEM and TEM images of fabricated GeOI substrate with different BOX structures. Ge pattern edge shows no peeling from SiO2(100nm)/Si substrate, indicating strong bonding strength at the pattern edge. In Fig. 2 (b), the bonding interface is clearly observed at Al2O3(5nm)/SiO2(50nm) interface formed by the wet activation process. The bonding interface exhibits very smooth and no defect. There is no observable defect in transferred Ge layer, suggesting dislocation density is below TEM detection limit. Compared to Smart-CutTM technique, ELO process has significant advantages in terms of crystal quality, thickness control and the surface flatness thanks to totally low temperature processing.To reduce wafer-scale thickness variation, etching stopper (ES) technique with high etching selectivity is quite useful. As a donor wafer, we prepare Ge active layer (20nm)/SiGe ES layer (5nm)/Ge buffer layer/AlAs/GaAs structures. Here, the SiGe layer serves as ES against the etching of Ge buffer layer to control the final GeOI thickness and attain the wafer-scale thickness uniformity. In addition, Si passivation on Ge surface was performed during initial epitaxial growth of donor wafer since Si passivation was proved to be effective in reducing interfacial trap density (D it) between Ge and oxide. After ELO process, Ge buffer layer /SiGe ES layer/Ge active layer / Al2O3 /SiO2/Si heterostructure was obtained. Then, the top Ge buffer layer was removed in HCl/H2O2 solution. We found the etching selectivity was more than 30 between Ge and SiGe layer, which is high enough to yield very smooth SiGe surface. Finally, SiGe layer was removed by TMAH preferentially.Further conformal thinning of Ge active layer was performed by the cyclic dry oxidation/wet digital etching (DE) at room temperature. In addition to thickness control with the etching rate of about 0.8 nm/cycle, it is found that dozens digital etching (DDE) process is effective for reducing Ge surface roughness. Finally, UTB GeOI substrates with high crystal quality down to 3 nm have been successfully fabricated through SiGe ES and DDE processes. Ultra-smooth GeOI surface with reduced thickness fluctuation was confirmed after DDE by TEM cross-sectional images, resulting in significant improvement of device performances. Figure 1

(G03 Best Paper Award Winner) Si-Passivated Ge Gate Sacks with Low Interface State and Oxide Trap Densities Using Thulium Silicate

Germanium is considered as a high mobility channel material for its potential to be introduced in future CMOS technology nodes. Ge surface passivation with a thin silicon layer (Si-cap) has been shown to be efficient for pFETs because of a sufficient valence band offset between Ge and Si-cap, which confines the holes in the Ge layer. Strained Ge pFinFETs outperforming Si pFinFETs due to four times higher mobility have been demonstrated using Si-cap process [1]. Interfacial defects can be further passivated with a high-pressure anneal in H2 resulting in reduced sub-threshold swing and increased mobility in Ge nanowires [2]. Moreover, by using a Si-cap, Negative-bias temperature instability reliability is improved compared to GeOx passivation because of the energy decoupling between holes and defects in SiO2/HfO2 gate stack [3]. However, a Si-cap process poses gate stack scalability issues because in order to achieve sufficient surface passivation, the Si-cap thickness cannot be scaled. An introduction of a high-k interfacial layer instead of a chemical oxide SiO2 could potentially help to scale down equivalent oxide thickness. Integrating thulium silicate (TmSiO) as a replacement of the SiO2 interfacial layer has been demonstrated on silicon, and a hole and electron mobility enhancement compared to SiO2/HfO2 gate stacks has been achieved for an equivalent oxide thickness (EOT) < 1 nm [4]. Moreover, we have previously displayed the compatibility of Tm2O3 with Ge by demonstrating GeOx/Tm2O3 gate stacks with interface state density Dit < 5·1011 eV-1cm-2 [5]. In this work, we integrate TmSiO with a Si-cap process to achieve Dit comparable to GeO2 passivation.In order to evaluate Ge/Si/TmSiO interfaces, MOS capacitors (MOSCAPs) were fabricated on n-type Ge strain relaxed buffers epitaxially grown on n-type Si wafers in a two-step process using GeH4 precursor [6]. Si-caps of different thicknesses were grown at 400 °C using Si2H6. Si growth was confirmed by ellipsometry spectroscopy and testing that the surface is hydrophobic. While trying to keep the Si-cap exposure to air to a minimum, 400 nm PECVD SiO2 was deposited and active areas were defined. After removing the remaining SiO2 from the active areas with 1 % HF, Tm2O3 was deposited by atomic layer deposition (ALD) at 225 °C. Rapid thermal anneal at 550 °C for 60 s in N2 was then employed to form TmSiO layer. High-k HfO2 was deposited by ALD at 350 °C followed by a post deposition anneal in O3 for 10 min. TiN gate metal was deposited at 425 °C by ALD and 500 nm Al was deposited by sputtering for probing purposes. After patterning, the samples were subjected to a forming gas anneal of 10% H2 in N2 at 400 °C for 30 min. Reference MOSCAPs with Ge/GeOx/Tm2O3/HfO2 gate stacks were also fabricated as described in [5] with addition of ALD HfO2.Interface state density in the midgap of Ge/Si/TmSiO/Tm2O3/HfO2 gate stacks was evaluated by CV measurements where measured CV characteristics where compared to calculated ones assuming a parabolic Dit distribution. Dit highly depends on Si-cap thickness, as displayed in Fig. 1. An optimal Si-cap thickness corresponding to 40-50 min deposition time provides Dit at midgap ~5·1011 cm-2eV-1 at CET of 4 nm. Reference MOSCAPs with Ge/GeOx/Tm2O3/HfO2 gates exhibit similar Dit of 4-5·1011 cm-2eV-1. Interface state density distribution within the band gap of Ge/Si/TmSiO interface with 40 min Si-cap deposition time was evaluated using the conductance method at different temperatures and is displayed in Fig. 2. Dit in the midgap is in agreement with the results obtained from CV measurements, and increases towards the valence and conduction band edges. The oxide trapped charge Qox of 2.5·1010 cm-2 (40 times lower than in the Ge reference devices without Si-cap) was determined from CV measurements and corresponds to only 5 mV hysteresis showing the potential of superior reliability.A Si-cap process with high-k TmSiO interface has been demonstrated on Ge MOS devices. A low Dit comparable to GeOx passivation has been shown. In addition, devices with TmSiO potentially have a superior reliability vs GeOx devices due to low oxide trapped charge density.

(Invited) Si-Cap-Free Low-DIT SiGe Gate Stack for High-Performance pFETs

As the continuous physical device scaling is facing increasing challenges in today’s CMOS technology, introduction of high mobility channel material has further increased its potential value as performance booster. Low-Ge-content SiGe is the leading candidate for p-channel devices, as it is process-compatible with state-of-the-art Si CMOS fabrication platform and requires no strain relaxed buffer layer. In order to benefit from the high intrinsic carrier mobility at a low VDD operation, an efficient SiGe channel passivation with low interface state densities (Dit) needs to be developped. However, the presence of GeO is known to increase Dit [1]. One of the effective passivation schemes for SiGe-based channel surface uses an epitaxially-grown ultrathin Si cap [2]. It suppresses the formation of GeO and enables to fabricate a high-k/SiO2 gate stack equivalent to the one in Si devices. The outstanding improvement achieved with this approach was previously highlighted on pure Ge channel devices, where the formation of GeO is inevitable without the use of Si-cap [3]. On the other hand, it poses some concerns such as EOT penalty and process controllability, making the Si-cap-free route the desired option as long as the interface and oxide bulk trap densities can be kept under control. In this contribution, we will review our recent studies towards the realization of a low-Dit Si-cap-free SiGe gate stack [4]. Selective GeO scavenging from Si1-xGexOy interface layer was previously reported as the key process to reduce Dit of SiGe gate stack [1]. Wostyn et al., demonstrated on Si0.75Ge0.25 that the annealing of chemical oxide in inert ambient (i.e. H2) reduces GeO in Si1-xGexOy IL thanks to the conversion of the thermally-unstable GeO into SiO [5]. A MOS capacitor experiment confirmed a clear Dit reduction by H2 anneal, although at an increased EOT. Additional NH3 anneal on IL was found to further reduce the Dit down to 5×1011 cm-2eV-1 while cancelling out the H2-anneal-induced EOT increase (EOT=10.1 Å). We also found that the metal gate deposition process has a strong impact on Dit even for the same metal. While the PVD W/TiN led to low Dit and EOT, both of them increased as the PVD was changed to ALD (or ALD followed by CVD) process. This can be explained by the PVD-TiN-induced additional GeO scavenging from IL [6] and/or oxygen diffusion from ALD-based metal to IL through HfO2 inducing GeO formation. A nitridation of HfO2 was found to suppress the negative impact from ALD-based metal electrode. XPS confirmed that the significant Dit reduction coincides with the nitridation of HfO2. By replacing the HfO2 with other dielectrics in which lower oxygen diffusivity is expected such as SiO2, the Dit of SiGe gate stack became insensitive to the metal deposition process and nitridation, indicating that the high oxygen diffusivity of the HfO2 layer was, together with the GeO formation, the root cause of the process-sensitive Dit. These results emphasize the importance of the oxygen depth profile control for the realization of a low-Dit SiGe gate stack.

(Invited) Electrical Performance Improvement in 300mm Ge-Based Devices

As device feature size continues to scale, new device architecture and dielectric materials with engineered properties are becoming essential in overcoming the issues in scaled CMOS devices such as short channel effects. Some of the recent innovations device makers are exploring for better electrostatic control and improved performance are the introduction of new device architecture such as gate all around devices (nanowires/nanosheets), and channel engineering such as high mobility channel materials (Ge and III-V). Ge is particularly attractive for use as a channel material for P-type MOSFETs due to its high hole mobility and Si VLSI high volume manufacturing (HVM) compatibility. However, there are couple significant remaining challenges to integrating Ge into 300mm Si VLSI HVM which are a stable gate-stack formation and integration of Ge on Si (1-5). In this talk, advances in Ge gate stack engineering will be discussed. Using Si compatible technologies we have demonstrated scaled EOT by engineering both the interface and high-k formation.Reference 1. S. Swaminathan, Y. Oshima, M. Kelly, P.C. McIntyre, Appl. Phys. Lett., 95, 032907 (2009).2. L. Zhang, M. Gunji, S. Thombare, P.C. McIntyre, IEEE Electr. Device. L., 34, 736 (2013).3. C.H Lee, T. Nishimura, C. Lu, S. Kabuyanagi, A. Toriumi, IEDM, 32.5.1 (2014).4. P. S. Goley, M. K. Hudait, Materials, 2301 (2014).5. Q. Xie, S. Deng, M. Shaekers, D. Lin, M. Caymax, A. Delabie, X-P Qu, Y-L. Jiang, D. Dedytsche, C. Detavernier, Semicond. Sci. Technol. 074012 (2012)

Single-crystalline GePb alloys formed by rapid thermal annealing-induced epitaxy

Single-crystalline GePb alloys have been successfully achieved by implanting Pb into Ge, followed by rapid thermal annealing under N2 atmosphere. The high crystallinity and the thickness of around 20 nm of the GePb alloys was determined by high-resolution x-ray diffraction and high-resolution transmission electron microscopy. The root-mean-square value of the as-implanted GePb sample is evaluated to be 1.25 nm in the 5 × 5 um scan area, which indicates a rather smooth surface. After being annealed at 400 °C, the result of a selected area electron diffraction pattern suggested that a single-crystalline alloy film was formed for the first time. The Pb composition of this sample is approximately 0.23% according to the x-ray photoelectron spectroscopy results. This value corresponds with the measurement result of the secondary ion mass spectroscopy. In addition, mobility enhancement in GePb/Ge samples has been identified by temperature-dependent Hall measurement, which indicates GePb alloys have great potential to be a promising high-mobility channel material for future monolithic optoelectronics integration application.

Diffusion mechanism of fluorine in plasma processing of III–V semiconductor compounds

III–V semiconductors have attracted attention as high mobility channel materials in advanced metal oxide semiconductors. However, there is a possibility that their characteristics deteriorate owing to the damage caused by dry etching when processing the channel material. We focus on dry etching damage to InP and investigate the diffusion and injection of various elements. Secondary ion mass spectrometry (SIMS) shows that a fluorine atom can easily diffuse into the III–V semiconductor. Furthermore, we investigate the diffusion depths of other elements to determine the activation energies by using first-principles calculations. The SIMS results show the diffusion distance in the bulk InP is strongly correlated with the activation energy. Additionally, radicals containing F can easily diffuse into InP. Therefore, the number of radicals present in the gas phase of the plasma is important. An increase in the adsorption probability of the surface, owing to ion bombardment and knock-on phenomenon, is assumed.

Germanium-Tin Junctionless p-Finfets: Effects of Channel Doping Concentration and Fin Width

High-mobility channel materials are important to extend the CMOS technology to beyond 3-nm node. GeSn p-MOSFETs with a record-high hole mobility of 845 cm2/V-s and a high drive current of > 1850 A/m were demonstrated [1, 2]. While the high-performance GeSn p-FETs were demonstrated, the required complicated fabrication steps remain challenging. A junctionless (JL) FinFET device was proposed to suppress the short-channel effects with easier fabrication steps [3]. Furthermore, for the JL devices, there are no additional ion implantation or annealing steps for the S/D formation, which can prevent Sn segregation or strain relaxation. While the device performance of JL FinFETs can be enhanced by increasing the channel doping concentration, the electrostatic control over the bulk channel in a JL FinFET becomes worse. In this work, we address the effects of the fin width and doping concentration on the device performance of GeSn JL FinFETs. GeSn JL p-FinFETs with fin widths of 10–50 nm are fabricated (Fig. 1 (a)). High-quality p-GeSn films were epitaxially grown on silicon-on-insulator substrates by in-situ doping chemical vapor deposition (CVD) and . HR-XRD results showed that the Ge0.92Sn0.08 layer was fully strained to the underlying relaxed Ge layer with clear Pendellösung fringes around the GeSn peak. Excellent crystallinity and defect-free GeSn/Ge interface can be observed in TEM images. The carrier density and mobility were characterized by Hall measurements. Boron dopants were fully activated up to the level of 1.3 × 1019 cm-3. The device fabrication steps were carried out at temperatures below 400 ◦C to prevent the Sn segregation. After a post-metal annealing step, the drive current was boosted by a factor of 1.5 due to the reduction of the contact resistance by the NiGeSn formation (Fig. 1 (b)). Furthermore, the SS was also improved after the PMA step. To improve the device performance of JL FinFETs, the doping concentration in the GeSn channel was increased by in-situ CVD. The drive current increases with the doping concentration due to the larger channel conductivity (Fig. 1 (c)). Benefiting from the low-temperature processes, JL structure, and the narrow fin width, the best SS is 88 mV/dec and extremely high Ion/Ioff ratios of 105 and 107 were achieved for the overdrive voltages of 0.7 V and 2 V, respectively (Fig. 1 (d)). Last, TCAD simulations were performed to investigate the effects of the channel doping concentration, the fin width, and the defect density at the oxide interface on SS. While for a high performance GeSn JL FinFET, the doping level was increased, the channel cannot be shut off effectively, leading to a higher subthreshold leakage and a poorer SS. To effectively deplete the carriers in the channel, a much reduced fin will be required. While shrinking the devices could improve the SS, the simulation results suggest that reducing the defect density at the high-k/GeSn interface is also crucial for further performance improvements of the GeSn JL FinFETs. [1] M. Liu et al., VLSI Symp. Tech. Dig., Jun. 2014. [2] Y.-S. Huang et al., IEDM Tech. Dig., Dec. 2017. [3] J. Colinge et al., Solid-State Electron., vol. 65, pp. 33–37, Nov. 2011. Figure 1

Regrown source/drain in InGaAs multi-gate MOSFETs

To realize further progress in the field of integrated circuits, a high mobility channel material, such as InGaAs for n-MOSFETs, with a multi-gate structure is desired. To realize high current densities in InGaAs MOSFETs, heavily doped sources/drains obtained using epitaxial growth are required. Here, we report the regrowth of source/drain using MOVPE for fin FET and nanosheet FET structures. A thinner flow liner for higher flow rate of 1.5 m/s was selected as a growth condition to improve the selective growth property and contact characteristics. As a result, a carrier concentration of 2 × 1019 cm−3 and contact resistivity of 8.0 × 10−8 Ωcm2 were obtained simultaneously.We fabricated fin FET and nanosheet structures as multi-gate MOSFETs. In the case of fin FETs, the surrounded growth of the channel and operation of a 16-nm-gate device were confirmed. In the case of nanosheet FETs, we used butt-jointed structures, i.e., we performed regrowth after the channel portion was formed into a mesa shape by etching, and the regrowth interface was a boundary between the channel and source/drain. After the regrowth and removal of the InP layer between the sheets, it was confirmed that the two layers of the nanosheets were supported by the regrown source/drain layers on both sides. In this structure, the operation of the 40-nm-gate device was also confirmed.

Enhanced Operation Characteristics for Charge Trapping Memory with Al2O3/HfO2/Al2O3 High-κ Dielectrics and Sige Substrate

Recent technology advances have moved nonvolatile memory (NVM) to the forefront as key enablers of computing-in-memory for AI chips and nonvolatile logics for IoT devices. Among the family of NVMs, charge trapping memory (CTM) devices has been widely used to realize low power consumption and high speed. In conventional SONOS-type CTM, it becomes hard to improve the program and erase (P/E) speed by optimizing tunneling oxide thickness while still maintaining the retention properties [1]. To confront the challenges faced by SONOS memory, various high-κ dielectrics (Ta2O5, ZrO2, Y2O3, HfO2, etc.) with reduced equivalent oxide thickness (EOT) and improved charge-trapping density are proposed to achieve better memory performance [2-3]. Apart from the adoption of high-κ dielectrics for CTM, the adoption of channel material can also improve memory performance. Recently, some efforts on the utilization of SiGe channel with high electron/hole injection rate have been reported to improve P/E efficiency [4-5]. Electron/hole injection increased because SiGe has a smaller bandgap than silicon. As the electron/hole injection located at tunneling oxide/SiGe channel increases, the number of electrons tunneling through the tunneling oxide is increased and the P/E speed is improved. In this paper, we proposed a novel memory device with high-κ Al2O3/HfO2/Al2O3 nanolaminate, SiGe channel and high work function tungsten metal gate. Finally, a novel charge trapping memory with the structure of [W/TiN]/Al2O3/HfO2/Al2O3/SiGe (named as MAHASG in short) is obtained. MAHASG memory devices with SiGe buried channel, as shown in Fig. 1, were fabricated on p-type Si wafer. Prior to SiGe epitaxial growth, the surface oxide was removed by using a dilute HF 1% solution. Then a 20 nm-thick SiGe epi-layer with 30% Ge content was deposited using reduced pressure chemical vapor deposition (RPCVD). After SiGe epitaxial growth, a 3 nm Al2O3 tunneling layer was deposited by atomic layer deposition (ALD) at a substrate temperature of 300℃. Subsequently, the 7 nm HfO2 film was grown by ALD as the charge trapping layer. Then, another 6-nm thick Al2O3 layer was deposited by ALD in situ as the blocking layer. After that high-κ dielectrics deposition, a post deposition anneal was performed for 15 s at the temperature of 450 °C in N2 atmosphere to improve the material quality of the high-κ dielectrics. Afterwards, TiN/W was deposited as the control gate by ALD and patterned by dry etch, followed by sputtering aluminum as the backside contact. Finally, a metallization process by using forming gas (5% H2, 95% N2) was applied for 30 min and at 400℃. Control samples without HfO2 layer were also fabricated using identical procedure. The resulting structure is shown in Fig 1. It should be noted that the whole process is simple and fully compatible with conventional CMOS technology. The memory characteristics for the MAHASG memory devices were investigated by a Keithley 4200 semiconductor characterization system. In order to study the charge trapping characteristics, bi-directional capacitance-voltage (C-V) curves were obtained by applying different sweeping gate voltages ranging from ±3 V to ±10 V at a frequency of 800 KHz, as shown in Fig. 2. A counterclockwise hysteresis was obtained during voltage sweep from inversion region to accumulation region and then back to inversion region. The memory window is defined as the flat-band voltage shift (ΔVFB) between the forward and backward sweep curves. There is no obvious memory window in the voltage sweep of ±3 V, indicating that charge trapping and de-trapping hardly take place in this voltage sweep range. When the voltage sweep range increases to ±6 V, the memory window is obvious. In a voltage sweep range of ±10 V, a large memory window of about 4 V can be obtained, as indicated in Fig 3. The energy band diagram of the MAHASG memory device is shown in Fig 4. The barrier height for electron injection from the SiGe channel to the HfO2 layer is about 2.74 eV, which is slightly smaller than that of the normal Si-SiO2 system (3.25 eV). This means that a higher charge tunneling probability and program efficiency occurred in this memory structure. In conclusion, this study provides a promising route of future nano-scaled flash memory operation, utilizing high-mobility channel and high-κ materials.

Study on Al2O3/Ge interface formed by ALD directly on epitaxial Ge

Germanium (Ge) has been attracting considerable attention as a high mobility channel material to enhance the performance of CMOS circuits. One of the most important issues for realization of practical Ge-MOSFET devices with superior performances is requirement to improve qualities of gate dielectric/Ge interfaces. In this work, Al2O3/Ge structures are fabricated by direct atomic layer deposition (ALD) on epitaxialy grown Ge. We indicate that ALD incubation time is fully suppressed by the ALD on a completely clean Ge surface created by Ge epitaxy on a Ge substrate. Moreover, x-ray photoelectron spectroscopy analyses reveal that unintentional formation of a GeO2 at the Al2O3/Ge interface can be almost avoided by the ALD on the epitaxial Ge whereas the interfacial GeO2 layer is present for samples exposed to the air before ALD. These results clearly indicate that direct ALD on epitaxial Ge is a very promising method to significantly improve Ge MOSFET performances.

(Invited) Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in Finfet, Stacked Nanowires and Monolithic 3D Integration

Microelectronic devices enable the continuous improvement in mobile data exchange and mobile communication. This exciting technological progress has been achieved by transistor scaling, resulting in an increased performance for lower energy consumption and cost. As CMOS device scaling proceeds, the number of epitaxial growth steps in device fabrication schemes increases. Examples are SiGe or Ge as high mobility channel materials [1-3], SiGe/Si or SiGe/Ge multi-layers to define nanowires in lateral Gate All Around (GAA) devices [3-5], and Source/Drain (S/D) stressor layers which also allow to reduce the S/D contact resistance [3,6-8]. In this contribution we will describe the characteristics of the epitaxial growth schemes as used for Fin and Gate-All-Around (GAA) devices. For Si- and SiGe-channel GAA devices, strained SiGe/Si multi-layers, which are used to define lateral nanowires, can be grown with conventional precursors (SiH4 or SiCl2H2 and GeH4). The compositional gradient is sufficiently steep to allow efficient wire release by selective SiGe or Si removal [2,5,9]. In case of Ge GAA, epitaxial growth of Ge-rich SiGe/Ge on SiGe Strain Relaxed Buffers is more challenging. Extremely low process temperatures are required to avoid strain relaxation. These layers need to be grown with higher order precursors, since conventional precursors become ineffective [4]. The epitaxial growth of ultra-thin Si layers on (strained) Ge fins or lateral nanowires used to passivate Ge surfaces in the high-k gate module has been discussed at the ECS Fall meeting of 2017 [10] and will not be covered in this presentation. A major challenge is to increase the active doping concentration in epitaxial S/D layers. Current scaling of gate and fin pitch reduces contact area and the contact resistance becomes a key contributor to device parasitics [7,11]. In addition, monolithic 3D integration, requires to reduce the thermal budget of the complete epitaxial growth scheme (including pre-epi surface cleaning). For Si:P, we demonstrated that P doping activation can be increased by post-epi anneals (>1e21 cm-3) without major strain loss [8]. Nearly similar active doping concentrations (up to 8e20 cm-3) are obtained by using Si3H8 instead of SiCl2H2 and low growth temperatures without the need for a post epi thermal treatment. For SiGe:B, we obtained similar active boron concentrations using conventional precursors [12,13]. Because of the low boron solubility in Ge, it is more challenging to fabricate S/D Ge pMOS contacts with the right lattice constant (to act as a stressor) and with a sufficiently high active doping concentration. Effort is ongoing to increase the active boron concentration by moving the growth process further away from equilibrium. This is done at low growth temperatures by either using Ge2H6 as high-order precursor or by assessing new materials such as GeSn. On blanket wafers, higher active doping concentrations have been reported but it is extremely challenging to translate this into a selective growth process without Sn precipitation. This triggered the research community to assess alternative dopants. For Ge, the Ga doping solubility is significantly higher than that of B. Epitaxial growth schemes are preferred above ion implantation as the latter one requires an unwanted high thermal budget for doping activation and on patterned wafers it does not allow conformal doping profiles. First Ge:Ga layers with a resistivity below 0.4 mΩ.cm have been grown without any detectable C incorporation. In addition, Ga + B co-doping enables to reduce the resistivity of SiGe:B:Ga, which confirms the potential of Ga as an add-on. Acknowledgements The imec core CMOS program members, European Commission, the TAKEMI5 ECSEL project, local authorities and the imec pilot line are acknowledged for their support. Air Liquide Advanced Materials is acknowledged for providing advanced precursor gases.