High Memory Capacity Research Articles

Design and Evaluation of a Cloud Computing System for Real-Time Measurements in Polarization-Independent Long-Range DAS Based on Coherent Detection.

CloudSim is a versatile simulation framework for modeling cloud infrastructure components that supports customizable and extensible application provisioning strategies, allowing for the simulation of cloud services. On the other hand, Distributed Acoustic Sensing (DAS) is a ubiquitous technique used for measuring vibrations over an extended region. Data handling in DAS remains an open issue, as many applications need continuous monitoring of a volume of samples whose storage and processing in real time require high-capacity memory and computing resources. We employ the CloudSim tool to design and evaluate a cloud computing scheme for long-range, polarization-independent DAS using coherent detection of Rayleigh backscattering signals and uncover valuable insights on the evolution of the processing times for a diverse range of Virtual Machine (VM) capacities as well as sizes of blocks of processed data. Our analysis demonstrates that the choice of VM significantly impacts computational times in real-time measurements in long-range DAS and that achieving polarization independence introduces minimal processing overheads in the system. Additionally, the increase in the block size of processed samples per cycle results in diminishing increments in overall processing times per batch of new samples added, demonstrating the scalability of cloud computing schemes in long-range DAS and its capability to manage larger datasets efficiently.

SMS Spam Detection System Based on Deep Learning Architectures for Turkish and English Messages

Short Message Service (SMS) still continues its existence despite the emergence of different messaging services. It plays a part in our lives as a communication service. Companies use SMS for advertisement purposes due to the fact that e-mail filtering systems have rooted, short message systems are being undersold by the operators, and spam detection and blocking systems used for short messages are ineffective. Individuals falling victim to SMS spam messages sent by malevolent persons incur pecuniary and non-pecuniary losses. The aim of this study is to present a hybrid model proposal with the intention of detecting SMS spam messages. This detection model uses a gated recurrent unit (GRU) and convolutional neural network (CNN) as two deep learning methods. However, the fact that both algorithms require high memory capacities is a limitation. The design for this model was laid out by using two different datasets containing combined text messages written in the Turkish and English languages. The datasets used in the study are TurkishSMSCollection and the SMS Spam dataset from the UCI database. The testing process was performed on the dataset through benchmarking as well as other machine learning algorithms. It was revealed in the study that the hybrid CNN + GRU approach attained an accuracy of 99.07% by demonstrating a better performance compared to the other algorithms.

Mitigation of 1-Row Hammer in BCAT Structures Through Buried Oxide Integration and Investigation of Inter-Cell Disturbances

Dynamic random-access memory (DRAM) is crucial for high-performance computing due to its speed and storage capacity. As the demand for high-capacity memory increases, DRAM has adopted a scaled-down approach for the next generation. However, the reduced distance between cells leads to electrical interference, known as the 1-row Hammer effect, which degrades DRAM performance and poses security risks. Therefore, the 1-row Hammer effect is a critical issue in current DRAM technology. In this study, we investigate the principles and impact of the 1-row Hammer phenomenon on DRAM. The 1-row Hammer effect can cause two types of failures: D0 and D1. We focus on D0 failures, which occur when stored data transition from 0 to 1 due to repeated accesses. This phenomenon involves the capture and diffusion of electrons, influenced by interfacial traps and device structures. To investigate the D0 failure, we simulated the 1-row Hammer effect using a mixed-mode approach to examine its effects on interfacial traps and device structure changes. This study aims to improve our understanding of row Hammer and suggests a mitigation strategy using buried oxide. The proposed structure mitigates the D0 failure by approximately 25%, effectively improving the security and reliability of DRAM.

AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main Memories

With the rising demands for high capacity memory and poor scalability of the existing DRAM-based main memories, the emerging Non-volatile memories captures higher attention due to their high density and low leakage power consumption. However, the possible consideration of such memories as alternatives of DRAM is largely hindered by their intrinsic drawbacks like high write latency, high write energy and low write endurance. In this article, we propose an integrated solution by combining the effect of compression and encoding assisted block placement to improve lifetime of NVMs. We have developed a compression technique called LUT_Comp by exploiting the word-level redundancy present in the words of the incoming cache blocks to NVM. LUT_Comp remains effective in reducing bit-flips in NVMs by offering a balance in compression ratio and coverage (Cov). Additionally, we also propose an encoding based block placement policy that places the compressed blocks in the appropriate half within the memory. The integrated approach of compression and block placement termed AmLuCEP offers a uniform bit-flips distribution while further reducing bit-flips in NVM. Experimental results show that AmLuCEP reduces bit-flips by 54%, 42%, 37%, 21%; energy consumption by 41%, 28%, 24%, 13%; and improves lifetime by 57%, 40%, 38%, 21% over baseline and the existing techniques READ [ 38 ], COEF [ 39 ] and SELEC [ 13 ], respectively.

Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access

The growing memory demands of modern applications have driven the adoption of far memory technologies in data centers to provide cost-effective, high-capacity memory solutions. However, far memory presents new performance challenges because its access latencies are significantly longer and more variable than local DRAM. For applications to achieve acceptable performance on far memory, a high degree of memory-level parallelism (MLP) is needed to tolerate the long access latency. While modern out-of-order processors are capable of exploiting a certain degree of MLP, they are constrained by resource limitations and hardware complexity. The key obstacle is the synchronous memory access semantics of traditional load/store instructions, which occupy critical hardware resources for a long time. The longer far memory latencies exacerbate this limitation. This article proposes a set of Asynchronous Memory Access Instructions (AMI) and its supporting function unit, Asynchronous Memory Access Unit (AMU), inside contemporary Out-of-Order Core. AMI separates memory request issuing from response handling to reduce resource occupation. Additionally, AMU architecture supports up to several hundreds of asynchronous memory requests through re-purposing a portion of L2 Cache as scratchpad memory (SPM) to provide sufficient temporal storage. Together with a coroutine-based programming framework, this scheme can achieve significantly higher MLP for hiding far memory latencies. Evaluation with a cycle-accurate simulation shows AMI achieves 2.42× speedup on average for memory-bound benchmarks with 1μs additional far memory latency. Over 130 outstanding requests are supported with 26.86× speedup for GUPS (random access) with 5 μs latency. These demonstrate how the techniques tackle far memory performance impacts through explicit MLP expression and latency adaptation.

A High-bandwidth High-capacity Hybrid 3D Memory for GPUs

GPUs execute thousands of active threads simultaneously, requiring high memory bandwidth to handle multiple memory requests efficiently. The memory bandwidth in GPUs has always been increasing, but it is still insufficient for the demands of fine-grained threads, necessitating a higher memory bandwidth. Important workloads like deep learning and data analytics demand terabytes of data processing, necessitating high memory capacity and bandwidth to avoid performance overheads. True-3D stacking of non-volatile memory layers on GPUs can provide the required higher bandwidth and capacity, enhancing performance and energy efficiency. We propose a high-bandwidth high-capacity hybrid 3D memory (H3DM) that doubles bandwidth through true-3D integration compared to the baseline GPU architecture and affords 272 GB of total memory capacity by stacking 8 PCM layers (each of 32 GB) and two DRAM layers (each of 8 GB).

Photoelectric synapses based on all-two-dimensional ferroelectric semiconductor heterojunction

Photoelectric synapses are attracting intensive attention due to its low power consumption and adaptive learning. However, traditional ferroelectric field effect transistors are not conducive to the integrated application in artificial intelligence systems. Here, we design the all two-dimensional photoelectric synapse device based on WSe2/MoS2/α-In2Se3 ferroelectric van der Waals heterojunction, which has high memory capacity (memory on/off = 105) and synaptic function. In addition, we simulate an artificial neural network to modify the handwritten digit recognition of the National Institute of Standards and Technology. In particular, the recognition rates are 92.4% and 93.6% for electrical synapse and photoelectric synapse, respectively. This work provides an effective strategy for achieving stable integration of neuromorphic computing.

GAT TransPruning: progressive channel pruning strategy combining graph attention network and transformer.

Recently, large-scale artificial intelligence models with billions of parameters have achieved good results in experiments, but their practical deployment on edge computing platforms is often subject to many constraints because of their resource requirements. These models require powerful computing platforms with a high memory capacity to store and process the numerous parameters and activations, which makes it challenging to deploy these large-scale models directly. Therefore, model compression techniques are crucial role in making these models more practical and accessible. In this article, a progressive channel pruning strategy combining graph attention network and transformer, namely GAT TransPruning, is proposed, which uses the graph attention networks (GAT) and the attention of transformer mechanism to determine the channel-to-channel relationship in large networks. This approach ensures that the network maintains its critical functional connections and optimizes the trade-off between model size and performance. In this study, VGG-16, VGG-19, ResNet-18, ResNet-34, and ResNet-50 are used as large-scale network models with the CIFAR-10 and CIFAR-100 datasets for verification and quantitative analysis of the proposed progressive channel pruning strategy. The experimental results reveal that the accuracy rate only drops by 6.58% when the channel pruning rate is 89% for VGG-19/CIFAR-100. In addition, the lightweight model inference speed is 9.10 times faster than that of the original large model. In comparison with the traditional channel pruning schemes, the proposed progressive channel pruning strategy based on the GAT and Transformer cannot only cut out the insignificant weight channels and effectively reduce the model size, but also ensure that the performance drop rate of its lightweight model is still the smallest even under high pruning ratio.

A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM.

A multi-layer stacked Dynamic Random Access Memory (DRAM) platform is introduced to address the memory wall issue. This platform features high-density vertical interconnects established between DRAM units for high-capacity memory and logic units for computation, utilizing Wafer-on-Wafer (WoW) hybrid bonding and mini Through-Silicon Via (TSV) technologies. This 3DIC architecture includes commercial DRAM, logic, and 3DIC manufacturing processes. Their design documents typically come from different foundries, presenting challenges for signal integrity design and analysis. This paper establishes a lumped circuit based on 3DIC physical structure and calculates all values of the lumped elements in the circuit model with the transmission line model. A Cross-Process Signal Integrity Analysis (CPSIA) method is introduced, which integrates three different manufacturing processes by modeling vertical stacking cells and connecting DRAM and logic netlists in one simulation environment. In combination with the dedicated buffer driving method, the CPSIA method is used to analyze 3DIC impacts. Simulation results show that the timing uncertainty introduced by 3DIC crosstalk ranges from 31 ps to 62 ps. This analysis result explains the stable slight variation in the maximum frequency observed in vertically stacked memory arrays from different DRAM layers in the physical testing results, demonstrating the effectiveness of this CPSIA method.

Photonic time-delayed reservoir computing based on series-coupled microring resonators with high memory capacity.

On-chip microring resonators (MRRs) have been proposed to construct time-delayed reservoir computing (RC) systems, which offer promising configurations available for computation with high scalability, high-density computing, and easy fabrication. A single MRR, however, is inadequate to provide enough memory for the computation task with diverse memory requirements. Large memory requirements are satisfied by the RC system based on the MRR with optical feedback, but at the expense of its ultralong feedback waveguide. In this paper, a time-delayed RC is proposed by utilizing a silicon-based nonlinear MRR in conjunction with an array of linear MRRs. These linear MRRs possess a high quality factor, providing enough memory capacity for the RC system. We quantitatively analyze and assess the proposed RC structure's performance on three classical tasks with diverse memory requirements, i.e., the Narma 10, Mackey-Glass, and Santa Fe chaotic timeseries prediction tasks. The proposed system exhibits comparable performance to the system based on the MRR with optical feedback, when it comes to handling the Narma 10 task, which requires a significant memory capacity. Nevertheless, the dimension of the former is at least 350 times smaller than the latter. The proposed system lays a good foundation for the scalability and seamless integration of photonic RC.

Tuned geometries of hippocampal representations meet the computational demands of social memory

Social memory consists of two processes: the detection of familiar compared with novel conspecifics and the detailed recollection of past social episodes. We investigated the neural bases for these processes using calcium imaging of dorsal CA2 hippocampal pyramidal neurons, known to be important for social memory, during social/spatial encounters with novel conspecifics and familiar littermates. Whereas novel individuals were represented in a low-dimensional geometry that allows for generalization of social identity across different spatial locations and of location across different identities, littermates were represented in a higher-dimensional geometry that supports high-capacity memory storage. Moreover, familiarity was represented in an abstract format, independent of individual identity. The degree to which familiarity increased the dimensionality of CA2 representations for individual mice predicted their performance in a social novelty recognition memory test. Thus, by tuning the geometry of structured neural activity, CA2 is able to meet the demands of distinct social memory processes.

Evaluation of Brain Electrical Activity of Visual Working Memory with Time-Frequency Analysis.

The term visual working memory (VWM) refers to the temporary storage of visual information. In electrophysiological recordings during the change detection task which relates to VWM, contralateral negative slow activity was detected. It was found to occur during the information is kept in memory and it was called contralateral delay activity. In this study, the characteristics of electroencephalogram frequencies of the contralateral and ipsilateral responses in the retention phase of VWM were evaluated by using time-frequency analysis (discrete wavelet transform [DWT]) in the change detection task. Twenty-six volunteers participated in the study. Event-related brain potentials (ERPs) were examined, and then a time-frequency analysis was performed. A statistically significant difference between contralateral and ipsilateral responses was found in the ERP. DWT showed a statistically significant difference between contralateral and ipsilateral responses in the delta and theta frequency bands range. When volunteers were grouped as either high or low VWM capacity the time-frequency analysis between these groups revealed that high memory capacity groups have a significantly higher negative coefficient in alpha and beta frequency bands. This study showed that during the retention phase delta and theta bands may relate to visual memory retention and alpha and beta bands may reflect individual memory capacity.

AB-INITIO CALCULATIONS OF RHOMBOHEDRAL BaTiO<sub>3</sub> (111) SURFACE COMBINED WITH GRAPHENE FILMS

Thin films of ABO3 perovskite ferroelectrics are important for many industrial applications, i.e., high-capacity memory cells, catalysis, optical waveguides, and integrated optics. The use of BaTiO3 for these industries and products is due to the variety of its surface structure and, accordingly, its electronic and chemical properties. Calculations of the surface characteristics of BaTiO3 from the first principles are useful for understanding processes that play a crucial role, such as surface reaction chemistry, surface phenomena, and adsorption surfaces. This study examined theoretical calculations related to the relaxed atomic structures of the surface of BaTiO3 (111).

Limitations on flexible allocation of visual short-term memory resources with multiple levels of goal-directed attentional prioritization.

Studies suggest that visual short-term memory (VSTM) is a continuous resource that can be flexibly allocated using probabilistic cues that indicate test likelihood (i.e., goal-directed attentional priority to those items). Previous studies using simultaneous cues have not examined this flexible allocation beyond two distinct levels of priority. Moreover, previous studies have not examined whether there are individual differences in the ability to flexibly allocate VSTM resources, as well as whether this ability benefits from practice. The current study used a continuous report procedure to examine whether participants can use up to three levels of attentional priority to allocate VSTM resources via simultaneous probabilistic spatial cues. Three experiments were performed with differing priority levels, cues, and cue presentation times. Group level analysis demonstrated flexible allocation of VSTM resources; however, there was limited evidence that participants could use three goal-directed priority levels. A temporal analysis suggested that task fatigue, rather than practice effects, may interact with item priority. A Bayesian individual-differences analysis revealed that a minority of participants were using three levels of attentional priority, demonstrating that, while possible, it is not the predominant pattern of behaviour. Thus, we provided evidence that flexible allocation to three attention levels is possible under simultaneous cuing conditions for a minority of participants. Flexible allocation to three categories may be interpreted as a skill of high-performing participants akin to high memory capacity.

EQNAS: Evolutionary Quantum Neural Architecture Search for Image Classification

Quantum neural network (QNN) is a neural network model based on the principles of quantum mechanics. The advantages of faster computing speed, higher memory capacity, smaller network size and elimination of catastrophic amnesia make it a new idea to solve the problem of training massive data that is difficult for classical neural networks. However, the quantum circuit of QNN are artificially designed with high circuit complexity and low precision in classification tasks. In this paper, a neural architecture search method EQNAS is proposed to improve QNN. First, initializing the quantum population after image quantum encoding. The next step is observing the quantum population and evaluating the fitness. The last is updating the quantum population. Quantum rotation gate update, quantum circuit construction and entirety interference crossover are specific operations. The last two steps need to be carried out iteratively until a satisfactory fitness is achieved. After a lot of experiments on the searched quantum neural networks, the feasibility and effectiveness of the algorithm proposed in this paper are proved, and the searched QNN is obviously better than the original algorithm. The classification accuracy on the mnist dataset and the warship dataset not only increased by 5.31% and 4.52%, respectively, but also reduced the parameters by 21.88% and 31.25% respectively. Code will be available at https://gitee.com/Pcyslist/models/tree/master/research/cv/EQNAS, and https://github.com/Pcyslist/EQNAS.

Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse

Spiking neural networks (SNNs) implemented in neuromorphic computing architectures promise a high degree of bio-plausibility and energy efficiency compared to the artificial neural network (ANN). Thus, SNN-based spiking associative memories are preferred for high capacity, area, and energy-efficient neural associative memories (NAMs). While most previously published works focused on ANN-based NAM, this work implements the full CMOS circuit of memristor crossbar-based spiking NAM for the first time. Instead of using any software-based memristive SPICE model or memristive devices that are yet not available in standard CMOS technology process design kits (PDKs), in our work, the CMOS-based memristive synapse circuit is employed to address practical circuit implementation challenges. The complete on-chip learning of the system is demonstrated using the bio-plausible spike-timing-dependent plasticity (STDP) learning mechanism without employing any external coprocessor, e.g., microprocessor, field-programmable gate array (FPGA). The entire system is implemented at the transistor level using 180-nm standard CMOS technology to demonstrate the pattern recognition application. The robustness of the proposed circuit is also evaluated to demonstrate the tolerance against the CMOS fabrication non-idealities.

A Redox‐Based Ion‐Gating Reservoir, Utilizing Double Reservoir States in Drain and Gate Nonlinear Responses

Herein, physical reservoir computing with a redox‐based ion‐gating reservoir (redox‐IGR) comprising LixWO3 thin film and lithium‐ion conducting glass ceramic (LICGC) is demonstrated. The subject redox‐IGR successfully solves a second‐order nonlinear dynamic equation by utilizing voltage pulse driven ion‐gating in a LixWO3 channel to enable reservoir computing. Under the normal conditions, in which only the drain current (ID) is used for the reservoir states, the lowest prediction error is 8.15 × 10−4. Performance is enhanced by the addition of IG to the reservoir states, resulting in a significant lowering of the prediction error to 5.39 × 10−4, which is noticeably lower than other types of physical reservoirs (memristors and spin torque oscillators) reported to date. A second‐order nonlinear autoregressive moving average (NARMA2) task, a typical benchmark of reservoir computing, is also performed with the IGR and good performance is achieved, with a normalized mean square error (NMSE) of 0.163. A short‐term memory task is performed to investigate an enhancement mechanism resulting from the IG addition. An increase in memory capacity, from 2.35 without IG to 3.57 with IG, is observed in the forgetting curves, indicating that enhancement of both high dimensionality and memory capacity is attributed to the origin of the performance improvement.

Suppressing Structural Relaxation in Nanoscale Antimony to Enable Ultralow-Drift Phase-Change Memory Applications.

Phase-change random-access memory (PCRAM) devices suffer from pronounced resistance drift originating from considerable structural relaxation of phase-change materials (PCMs), which hinders current developments of high-capacity memory and high-parallelism computing that both need reliable multibit programming. This work realizes that compositional simplification and geometrical miniaturization of traditional GeSbTe-like PCMs are feasible routes to suppress relaxation. While to date, the aging mechanisms of the simplest PCM, Sb, at nanoscale, have not yet been unveiled. Here, this work demonstrates that in an optimal thickness of only 4nm, the thin Sb film can enable a precise multilevel programming with ultralow resistance drift coefficients, in a regime of ≈10-4 -10-3 . This advancement is mainly owed to the slightly changed Peierls distortion in Sb and the less-distorted octahedral-like atomic configurations across the Sb/SiO2 interfaces. This work highlights a new indispensable approach, interfacial regulation of nanoscale PCMs, for pursuing ultimately reliable resistance control in aggressively-miniaturized PCRAM devices, to boost the storage and computing efficiencies substantially.

Large tunnel magnetoresistance in magnetic tunnel junctions with magnetic electrodes of metastable body-centered cubic CoMnFe alloys

A magnetic tunnel junction (MTJ) is a key device in spintronics applications, such as magnetoresistive random access memory (MRAM). Current standard magnetic material for MTJs is a body-centered cubic (bcc) FeCo(B), which shows large tunnel magnetoresistance (TMR) and high perpendicular magnetic anisotropy (PMA), both are crucial for high-memory capacities MRAM. It is demanded that magnetic materials showing TMR as well as PMA higher than FeCo(B) for further advance. One of alternative magnetic materials may be bcc Co since past ab-initio studies predict that bcc Co show large TMR effect in MgO-barrier MTJs and large PMA due to magneto-elastic effect for those strained state. However, bcc Co is thermodynamically unstable; thus, it is aimed to explore metastable bcc Co based alloys with high stability. Here, we propose metastable bcc Co based alloy with adding both Mn and Fe as a candidate. We study in-plane magnetized MTJs utilizing metastable bcc CoMnFe films as electrodes and demonstrate large TMR effect of 350% at 300 K and of 1002% at 5 K. This experimental finding will open a route to advanced bcc Co based magnetic material for MRAM applications.

Voltage Reduced Self Refresh (VRSR) for optimized energy savings in DRAM Memories

Modern computing systems demand DRAMs with more capacity and bandwidth to keep pace with the onslaught of new data-intensive applications. Though DRAM scaling offers higher density devices to realize high memory capacity systems, energy consumption has become a key design limiter. This is owing to the fact that the memory sub-system continues to be responsible for a significant fraction of overall system energy. Self-refresh mode is one low power state that consumes the least DRAM energy, and this is an essential operation to avoid data loss. However, self-refresh energy also continues to grow with density scaling. This paper carries out a detailed study of reducing self-refresh energy by reducing the supply voltage. PARSEC benchmarks in Gem5 full-system mode are used to quantify the merit of self-refresh energy savings at reduced voltages for normal, reduced, and extended temperature ranges. The latency impacts of basic operations involved in self-refresh operation are evaluated using the 16 nm SPICE model. Possible limitations in extending the work to real hardware are also discussed. As a potential opportunity to motivate for future implementation, DRAM architectural changes, additional low power states and entry/exit flow to exercise reduced voltage operation in self-refresh mode are proposed. We present this new low power mode as Voltage Reduced Self-Refresh (VRSR) operation. Our simulation results show that there is a maximum of ∼12.4% and an average of ∼4% workload energy savings, with less than 0.7% performance loss across all benchmarks, for an aggressive voltage reduction of 150 mV.