High-level Verification Research Articles

High level verification of the VFAT3 ASIC for CMS GEM detectors

A front-end readout chip VFAT3 was designed for the muon detector gas electron multipliers (GEM). GEMs were installed at the Compact Muon Solenoid (CMS) experiment of the Large Hadron Collider (LHC) at CERN for the high luminosity upgrade. The design of the VFAT3 uses 790 analog and 172 digital blocks which are highly integrated, thus it is crucial to ensure that the different blocks work together and the chip works as a whole. Mixed signal simulation methods were used to verify the high level functionality. Trigger latencies of 125, 150, 175 and 225 ns were found for front-end peaking times of 25, 50, 75 and 100 ns, respectively. The maximum trigger rate for reading out standard data packets was found to be 1.7 MHz. Results of the VFAT3 high level verification are presented and the simulation methods described.

A methodology to take credit for high-level verification during RTL verification

High-level verification and synthesis of SystemC models has become increasingly popular as a means to reduce the high RTL verification cost of today’s complex designs. However, the saving derived from performing verification at a higher level of abstraction is largely negated if the RTL then must be completely reverified. We demonstrate how global (system-level) properties may be verified at a behavioral level in a manner that reduces the required RTL verification. Our methodology entails using high-level control models together with semantic stubs for control and data-path refinements. The consequence is that cover goals met during high-level verification are then “virtually” met (in a semantically sound fashion) for RTL verification, and need not be re-established in the RTL. Moreover, it can be significantly more efficient (in terms of required verification cycles) to meet these cover goals at the higher level. This can lead both to less costly verification and earlier debug, providing a better structured, faster and more reliable path to implementation than is possible through conventional RTL verification.

Functional Verification of Large-integers Circuits using a Cosimulation-based Approach

Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer’s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability.

High-level Synthesis Integrated Verification

It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification. For the very complex contemporary chips, this may prove prohibitive for the IC to arrive at the correct time in the market and therefore, valuable sales share may be lost by the developing industry. This problem is deteriorated by the fact that most of conventional verification flows are highly repetitive and a great proportion of the project time is spent on last-moment simulations. In this paper we present an integrated approach to rapid, high-level verification, exploiting the advantages of a formal High-level Synthesis tool, developed by the author. Verification in this work is supported at 3 levels: high-level program code, RTL simulation and rapid, generated C testbench execution. This paper is supported by strong experimental work with 3-4 popular design synthesis and verification that proves the principles of our methodology.

Automated Planning as an Early Verification Tool for Distributed Control

We present a new modelling formalism which is suitable for capturing high level functional specifications and requirements of reactive control systems. This formalism is a simple extension of the classical planning formalism. We show that if specifications are thus formalized, then it is possible to use existing automated planners and model checkers to find logical faults in them. Our extension to classical planning consists of introducing a separate class of actions, referred as control actions, which have higher priority than regular actions.We present several illustrative examples of high-level modelling and verification of modern automotive features with our proposed formalism. We present several compilation schemes to solve the proposed problem using well-known planners and the model checkers. We present a comparative study of the performance of a number of well-known tools on our problem.We also present some novel optimization techniques which help the solution scale much better with most of the studied tools.

The Status and Challenges of Multi-Processor System-on-Chip’s Formal Verification

With the continuous advancement of processor manufacturing process as well as the exposed limitations of single-core Processors, Multi-Processor System-on-Chip (MPSoC) has become the inevitable outcome of the technological development and practical application needs. It is used to meet the requirements of multitasking, multifunctional and high performance computing. With the improvement of chip complexity, verification module also increases exponentially. Verification of MPSoC is becoming Bottleneck in the process of chip’s design. So this paper first introduces the origin of MPSoC, and analyzes developing tendency of its verification. And then, the theory and main challenges to the formal verification of MPSoC are discussed. This paper will provide support for building the verified theory method and technology that can meet the demand of MPSoC design, and Developing MPSoC high-level architecture design verification technology.

Don't sweat the small stuff

We present an approach for automatically generating provably correct abstractions from C source code that are useful for practical implementation verification. The abstractions are easier for a human verification engineer to reason about than the implementation and increase the productivity of interactive code proof. We guarantee soundness by automatically generating proofs that the abstractions are correct. In particular, we show two key abstractions that are critical for verifying systems-level C code: automatically turning potentially overflowing machine-word arithmetic into ideal integers, and transforming low-level C pointer reasoning into separate abstract heaps. Previous work carrying out such transformations has either done so using unverified translations, or required significant proof engineering effort. We implement these abstractions in an existing proof-producing specification transformation framework named AutoCorres, developed in Isabelle/HOL, and demonstrate its effectiveness in a number of case studies. We show scalability on multiple OS microkernels, and we show how our changes to AutoCorres improve productivity for total correctness by porting an existing high-level verification of the Schorr-Waite algorithm to a low-level C implementation with minimal effort.

Canonical representations of high-level decision diagrams

In this paper we give a short overview of the decision diagrams, and define a special class of high-level decision diagrams (HLDD) for formal representation of digital systems. We show how the HLDDs can be used for high-level verification of digital systems. For this purpose, HLDDs are represented by characteristic polynomials as a canonical form of HLDDs. The polynomials can be used for proving the equivalence between two HLDDs, which have the same functionalities but may have different internal structures. Some possibilities are shown how to cope with the complexity of the verification problem.

A Process Algebraic View of Latency-Insensitive Systems

Latency-insensitive (LI) systems are those which can function correctly in spite of delays along its connecting wires. This delay is assumed to be a multiple of the clock period. The paper presents a single-clock process algebraic model for such systems. It gives the definitions for LI computational blocks and LI connectors. Important properties for these are shown to be satisfied. Composition of such modules can be done by the parallel composition operator of the process algebra. Conditions are given to check for liveness and deadlock freedom of LI systems. Comparison of latency equivalence between streams of events can be done using the model and this leads to a method of proving latency-equivalent modules. The paper is a step toward high-level specification and verification of such systems. The work can be extended to address more complex interconnections by modeling the underlying finite-state machines.

Product, Delivery & Service Differentiation: Case Study on Einfochips

eInfochips is an IP driven Product Development Services Company, based at Ahmedabad and engaged in global IT business activities. The company provides ASIC design and verification services, embedded systems solutions and IP cores. In year 1994, Pratul Shroff founded the company with one design engineer in his residential premises. Pratul Shroff, worked for Intel as a designer & as co-founder in Daisy Systems for 9 years. The company received financial support of $ 400,000 from Gujarat Venture Capital Finance. It grew into 300 plus employees in India & strong global team of 730 professionals with approximately annual revenue of $6.4 million by end of its first decade. The management vision is to make Einfochips, innovative technology company that transforms society by creating leaders and generating stakeholder value. Einfochips attains its vision by differentiating product, delivery & service to the clients. The company’s division includes chip design unit, which has expertise ranged from specification to silicon, encompassing ASIC/SOC design and verification, physical layout and implementation, firmware development, DSP hardware and algorithms and board design. The electronic engineering unit provides complete prototype electronic product. One area where eInfochips has differentiated their is the verification space. As the complexity of chips increases, so does the challenge of verification, which can easily consume 50% of the total design cycle time. The company provides training to its employees in high-level verification languages such as Specman and Vera. eInfochips is a third-party network member and is one of only two TI Certified Software Integrators. The other differentiation is in delivery of the product, by using ‘Unique Amplified Offshoring’ delivery model, which increases the effectiveness of services, that offers combinational advantage of both offshore, on-site modes. eInfochips has two design centers in India & three sales offices in the U.S. where company maintains 30 to 40 engineers in U.S., who serve as the link between the customer and the design team. EInfochips considers these product champions essential to its business, as these engineers bridge the myriad gaps - communication, cultural, temporal and geographic - between the U.S.-based customer and the India-based design team. Major differentiation is in service to the clients & the ability to address the entire spectrum of solutions. To ensure & meet ever-changing demands of technology industry, eInfochips provides special kind of technical & management training known as 'Chipmates' and compulsory year long 'Life Skills' training on teamwork, time management, communication, dealing with cultural gaps and attitude. The case study focuses on innovation brought by eInfochips in offshore business by differentiating product, delivery and service to the clients. The case study is finalist in 2009 Aditya Birla Case Study Initiative, London Business School and full case is available with ecch.

High-Level Verification

The growth in size and heterogeneity of System-on-Chip (SOC) design makes their design process from initial specification to IC implementation complex. System-level design methods seek to combat this complexity by shifting increasing design burden to high-level languages such as SystemC and SystemVerilog. Such languages not only make a design easier to describe using high-level abstractions, but also provide a path for systematic implementation through refinement and elaboration of such descriptions. In principle, this can enable a greater exploration of design alternatives and thus better design optimization than possible using lower level design methods. To achieve these goals, however, verification capabilities that seek to validate designs at higher levels as well their equivalences with lower level implementations are crucially needed. To the extent possible given the large space of design alternatives, such validation must be formal to ensure the design and important properties are provably correct against various implementation choices. In this paper, we present a survey of high-level verification techniques that are used for both verification and validation of high-level designs, that is, designs modeled using high-level programming languages. These techniques include those based on model checking, theorem proving and approaches that integrate a combination of the above methods. The high-level verification approaches address verification of properties as well as equivalence checking with refined implementations. We also focus on techniques that use information from the synthesis process for improved validation. Finally, we conclude with a discussion and future research directions in this area.

High-Level Verification

High-Level Verification

VERIFICATION OF DATAFLOW SCHEDULING

This paper presents the formal verification method for high-level synthesis (HLS) to detect design errors of dataflow algorithms by using Petri Net (PN) and symbolic-model-verifier (SMV) techniques. Formal verification in high-level design means architecture verification, which is different from functional verification in register transfer level (RTL). Generally, dataflow algorithms need algorithmic transformations to achieve optimal goals and also need design scheduling to allocate processor resources before mapping on a silicon. However, algorithmic transformations and design scheduling are error-prone. In order to detect high-level faults, high-level verification is applied to verify the synthesis results in HLS. Instead of applying Boolean algebra in traditional verification, this paper adopts both Petri Net theory and SMV model checker to verify the correctness of the synthesis results of the high-level dataflow designs. In the proposed hybrid verification method, a high-level design or DUV (design-under-verification) is first transformed into a Petri Net model. Then, Petri Net theory is applied to check the correctness of its algorithmic transformations of HLS, and the SMV model checker is used to verify the correctness of the design scheduling. We presented two approaches to realize the proposed verification method and concluded the best one who outperforms the other in terms of processing speed and resource usage.

Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing

This paper addresses the equivalence verification problem of register-transfer level (RTL) descriptions that implement arithmetic computations (such as add, mult) over bit vectors with finite widths. A bit vector of size represents integer values from 0 to 2m-1, implying that the corresponding integer values are reduced modulo 2m(%2m). This suggests that bit-vector arithmetic can be efficiently modeled as algebra over finite integer rings, where the bit-vector size (m) dictates the cardinality of the ring (Z2 m). This paper models the arithmetic datapath verification problem as the equivalence testing of polynomial functions from Z2 n 1timesZ2 n 2times...timesZ2 n drarrZ2 m. We formulate the equivalence problem into that of proving whether f-gequiv0%2m. Fundamental concepts and results from ldquonumber,rdquo ldquoring,rdquo and ldquoideal theoryrdquo are subsequently employed to develop systematic complete algorithmic procedures to solve the problem. We demonstrate the application of the proposed theoretical concepts to high-level (behavioral/RTL) verification of bit-vector arithmetic within practical computer-aided design settings. Using our approach, we verify a set of arithmetic datapaths at RTL, where contemporary verification approaches prove to be infeasible.

Development of a High-Level Algorithm Verification and Validation Procedure for Traffic Microsimulation Models

The successful acceptance of traffic microsimulation software depends crucially on the verification and validation (V&V) procedures for testing the core behavioral algorithms. These must be sufficient to convince researchers, software developers, and practitioners that the algorithms are accurate and robust. V&V procedures must also be well documented to ensure public acceptance. A suggested V&V procedure is presented. The central theme is that verification and validation are integral parts of the entire algorithm development process. A three-stage algorithm development and V&V procedure for traffic microsimulation algorithms is recommended. Algorithm development includes identifying key variables and setting model parameters. Next, the software implementation of the algorithm is tested during the algorithm-level testing stage with a combination of hypothetical and simple real-world data. Finally, systemlevel testing of the algorithm software is done within a complete microsimulation modeling system. In the last stage, the system with the new algorithm is tested against complex real-world data sets.

Impacts of verification on a numeral string recognition system

In this paper we discuss the use of high-level verification on handwritten numeral strings. First of all, we introduce the concept of levels of verification and present the baseline system used to carry out the experiments. Two different strategies were developed: absolute and one-to-one verifiers. A thorough error analysis is also presented in order to identify under which conditions high-level verification is more appropriate. Experimental results are presented on NIST SD19 database.

C-based SoC design flow and EDA tools: an ASIC and system vendor perspective

This paper examines the achievements and future of system-on-a-chip (SoC) design methodology and design flow from the viewpoints of an in-house electronic design automation team of an application-specific integrated circuit and system vendor. We initially discuss the problems of the design productivity gap caused by the SoC's complexity and the timing closure caused by deep-submicrometer technology. To solve these two problems, we propose a C-based SoC design environment that features integrated high-level synthesis (HLS) and verification tools. A HLS system is introduced using various successful industrial design examples, and its advantages and drawbacks are discussed. We then look at the future directions of this system. The high-level verification environment consists of a mixed-level hardware/software co-simulator, formal and semi-formal verifiers, and test-bench generators. The verification tools are tightly integrated with the HLS system and take advantage of information from the synthesis system. Then, we discusses the possibility of incorporating physical design features into the C-based SoC design environment. Finally, we describe our global vision for an SoC architecture and SoC design methodology.