Abstract
It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification. For the very complex contemporary chips, this may prove prohibitive for the IC to arrive at the correct time in the market and therefore, valuable sales share may be lost by the developing industry. This problem is deteriorated by the fact that most of conventional verification flows are highly repetitive and a great proportion of the project time is spent on last-moment simulations. In this paper we present an integrated approach to rapid, high-level verification, exploiting the advantages of a formal High-level Synthesis tool, developed by the author. Verification in this work is supported at 3 levels: high-level program code, RTL simulation and rapid, generated C testbench execution. This paper is supported by strong experimental work with 3-4 popular design synthesis and verification that proves the principles of our methodology.
Highlights
Embedded, high-performance and portable computing systems digital circuits have highly complex design control & module hierarchy as well as interconnection schemes
Commercial and academic organizations have invested in High-Level Synthesis (HLS) and Electronic System Level (ESL) methodologies to achieve design automation, quality of implementations and short specification-to-product times [1,2,3,4,5,6]
High-level optimizations are based on software compiler optimizations, www.etasr.com allocation is selection of functional units and storing resources for the data and operations objects found in high-level program code, binding is the actual mapping of the above units to real hardware elements such as flip-flops, latches and combinatorial blocks such as functional operator hardware units, and scheduling is the arrangement of elementary operations to Finite State Machine (FSM) states in system’s clock cycles
Summary
High-performance and portable computing systems digital circuits have highly complex design control & module hierarchy as well as interconnection schemes This complexity cannot be dealt anymore with conventional methods such as Register Transfer Level (RTL) coding, since they involve highly iterative design flows, detailed and prolonged simulations and prohibitive development times. High-level optimizations are based on software compiler optimizations, www.etasr.com allocation is selection of functional units and storing resources for the data and operations objects found in high-level program code, binding is the actual mapping of the above units to real hardware elements such as flip-flops, latches and combinatorial blocks such as functional operator hardware units, and scheduling is the arrangement of elementary operations to Finite State Machine (FSM) states in system’s clock cycles These problems have been studied in research labs, the optimization of real-world complex applications, as well as their mapping onto custom hardware fails to produce competitive to manual implementations. In this way specification to product development times are compressed significantly, since lengthy RTL or gate-level simulations are avoided
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