Abstract
The increasing complexity of Application Specific Integrated Circuits (ASICs) and Systems-on-Chip (SoCs) that incorporate custom and standard embedded core IP blocks dictates the need for a new generation of automated and formal system EDA tools and methodologies. High-Level Synthesis (HLS) plays a critical role in the required Electronic System Level (ESL) methodologies. However, most of the available academic and commercial High-Level Synthesis (HLS) tools still do not play an established role in the system and hardware engineering teams. This is true for a number of practical reasons, analyzed and discussed in this work. The present article is a practical perspective of the required fully automated and formal tools, which are needed to constitute integral parts in Electronic Design Automation (EDA) flows. In addition, this article is a useful guide to the system engineer who wants to familiarize with HLS tools and to select the appropriate tool for the everyday engineering practice. The advanced HLS toolset that is analyzed in this paper is developed by the first author, its C-frontend by the second author, and they are both based on formal methods and fully automated techniques, thus they guarantee the correctness of the synthesized hardware implementations. This paper completes with a number of experiments that were executed using the author’s methodology and they are used to evaluate the specific HLS tools. Consequently, a number of conclusions are drawn as well as suggestions for the future directions of HLS technology. In this way, what is practically needed by the hardware systems engineering community is outlined at the end of the paper.
Highlights
Nowadays, digital integrated microelectronics feature extremely complex components, control/design hierarchy and interconnection schemes
What about the future? What should be the future directions in order to achieve industrial strength High-Level Synthesis (HLS)? More input programming languages (e.g. C++, System-C, UML, Fortran, Delphi-Pascal, Java, SystemC, Python, etc.) and a more globalized and integrated use of formal techniques throughout the flow of the HLS toolset are needed in order to bring practical results with acceptable quality of HLS results
The assumptions that many existing HLS tools make, produce disappointing synthesis results, since there is still no established methodology for feeding target technology characteristics back into the core of the HLS transformation process. In most cases these target implementation characteristics need to be fed into the synthesis flow and guide the complex synthesis transformations of the HLS tool, which makes the synthesis process manual, heavily interactive, cumbersome, prone to errors and very slow
Summary
Digital integrated microelectronics feature extremely complex components, control/design hierarchy and interconnection schemes. Recent research efforts include a multi-speculative approach to synthesize complex adders during datapath synthesis, which again contributes only towards linear flow oriented designs [8], a fixed-point accuracy analysis and optimization of polynomial data-flow graphs with respect to a reference model that is found in many DSP applications [9], a technique to improve nested loop pipelining for HLS, called Polyhedral Bubble Insertion [10], an equivalence checking method of FSMs with datapaths based on value propagation over model paths, for validation code motion, usually applied during the HLS scheduling phase [11], a formal method for accurate high-level casting of optimal adders and subtractors [12], and an exploration approach, called Spectral-aware Pareto Iterative Refinement, that uses response surface models (RSMs) and spectral analysis to predict the design quality without costly architectural synthesis procedures [13]
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