A study of high-level synthesis: Promises and challenges

Abstract

A wide variety of application domains such as networking, computer vision, and cryptography target FPGA platforms to meet computation demand and energy consumption constraints. However, design effort for FPGA implementations in hardware description languages (HDLs) remains high - often an order of magnitude larger than design effort using high level languages (HLLs). Instead of development in HDLs, high level synthesis (HLS) tools generate hardware implementations from algorithm descriptions in HLLs such as C/C++/SystemC. HLS tools promise reduced design effort and hardware development without the detailed knowledge of the implementation platform. In this paper, we study AutoPilot, a state-of-the-art HLS tool, and examine the suitability of using HLS for a variety of application domains. Based on our study of application code not originally written for HLS, we provide guidelines for software design, limitations of mapping general purpose software to hardware using HLS, and future directions for HLS tool development. For the examined applications, we demonstrate speedup from 4X to over 126X, with a five-fold reduction in design effort vs. manual design in HDLs.