High level verification of the VFAT3 ASIC for CMS GEM detectors

Abstract

A front-end readout chip VFAT3 was designed for the muon detector gas electron multipliers (GEM). GEMs were installed at the Compact Muon Solenoid (CMS) experiment of the Large Hadron Collider (LHC) at CERN for the high luminosity upgrade. The design of the VFAT3 uses 790 analog and 172 digital blocks which are highly integrated, thus it is crucial to ensure that the different blocks work together and the chip works as a whole. Mixed signal simulation methods were used to verify the high level functionality. Trigger latencies of 125, 150, 175 and 225 ns were found for front-end peaking times of 25, 50, 75 and 100 ns, respectively. The maximum trigger rate for reading out standard data packets was found to be 1.7 MHz. Results of the VFAT3 high level verification are presented and the simulation methods described.