High-lead Solder Research Articles

Damages and Microstructural Variation of High-lead and Eutectic SnPb Composite Flip Chip Solder Bumps Induced by Electromigration

The electromigration behavior of the high-lead and eutectic SnPb composite solder bumps was investigated at 150 °C with 5 × 103 A/cm2 current stressing for up to 1711 h. The diameter of the bumps was about 125 μm. The underbump metallization (UBM) on the chip side was sputtered Al/Ni(V)/Cu thin films, and the Cu pad on the board side was plated with electroless Ni/Au. It was observed that damages occurred in the joints in a downward electron flow (from chip side to the substrate side), while those joints having the opposite current polarity showed only minor changes. In the case of downward electron flow, electromigration damages were observed in the UBM and solder bumps. The vanadium in Ni(V) layer was broken under current stressing of 1711 h while it was still intact after current stressing of 1000 h. The electron probe microanalyzer (EPMA) elemental mapping clearly shows that the Al atoms in the trace migrated through the UBM into the solder bump during current stressing. Voids were found in the solder bump near the UBM/solder interface. The Sn-rich phases of the solder bumps showed gradual streaking and reorientation upon current stressing. This resulted in the formation of uniaxial Sn-rich phases in the middle of the solder bump, while the columnar and fibrous Sn-rich phases were formed in the surrounding regions. The formation mechanism of electromigration-induced damage to the UBM structure and solder bump were discussed.

Impression creep characterization of 90Pb-10Sn microelectronic solder balls at subsolvus and supersolvus temperatures

The creep behavior of Pb-10wt.%Sn, a common high-lead solder used in microelectronic packaging, was studied by impression creep testing of ball-gridarray (BGA) solder balls attached to an organic substrate, both above and below the solvus temperature (408 K). Below the solvus temperature, the solder microstructure consists of roughly equiaxed grains of the Pb-rich solid solution α, which contains <5wt.%Sn in solution, with a coarse dispersion of Sn-rich β precipitates. Here, the creep behavior of the solder is controlled by dislocation climb via dislocation core diffusion, yielding n≈4 and Q≈60 kJ/mole. Above the solvus temperature, where the entire 10wt.%Sn is in solution, the creep mechanism becomes controlled by viscous glide of dislocations, limited by solute drag, with n≈3 and Q≈92 kJ/mole. Based on experimental data, creep equations for the as-reflowed solder in the two temperature regimes are given. Comparison of the present data with those available in the literature showed good agreement with the proposed laws.

Reliability of an 1657CCGA (Ceramic Column Grid Array) Package With 95.5SN3.9AG0.6CU Lead-Free Solder Paste on PCBS (Printed Circuit Boards)

In many applications such as computers and telecommunications, the IC chip sizes are very big, the on-chip frequency and power dissipation are very high, and the number of chip I/Os is very large. The CCGA (ceramic column grid array) package developed by IBM is one of the best candidates for housing these kinds of chips. There are two parts in this study. One is to show that the two-parameter Weibull life distribution is adequate for modeling the thermal-fatigue life of lead-free solder joints. This is demonstrated by comparing the two-parameter and three-parameter Weibull distributions with life test data of an 1657-pin CCGA package with the 95.5 wt %Sn3.9 wt %Ag0.6 wt %Cu lead-free solder paste on lead-free printed circuit boards under thermal cycling conditions. The other part of this study is to determine the time-history creep strain energy density of the 1657-pin CCGA solder column with two different solder paste materials, namely, 95.5 wt %Sn3.9 wt %Ag0.6 wt %Cu and 63 wt %Sn37 wt %Pb and under three different thermal cycling profiles, namely, 25↔75°C, 0↔100°C, and −25↔125°C. The effects of these solder pastes and temperature conditions on the thermal-fatigue life of the high-lead (10 wt %Sn90 wt %Pb) solder columns of the CCGA package are provided and discussed.

Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps

Experiments were carried out to investigate the effect of reversing the heat flux direction during cooling on the formation of voids during the reflow process. Under different upward and downward solidification conditions, 480 high-lead (90Pb∕8Sn∕2Ag) solder joints of flip-chip assemblies were processed. The solder samples were then microsectioned to determine the size and location of voids. The results show that reversing the flow direction during cooling has a significant effect on the final void formation. For the case of the melting direction from top (flip-chip side) to bottom (test board side), reversing the heat flux direction results in solidification direction from top to bottom. The percentage of defective bumps was found to be 28% and the volume of voids per defective bump was 1.5%. This is the best reflow methodology to minimize voids. Without reversing the heat flux the defective bumps were 80% with 4.0% void volume. In the case of solidification direction/melting direction from bottom to top, the percentage of defective bumps increases from 40% to 51%, accompanying a rise of the volume of voids from 3.0% to 3.7%.

Constitutive Model and Numerical Analysis for High Lead Solders

High lead solder interconnects are extensively used in the electronic industry. This paper uses a unified creep plasticity (UCP) constitutive model to numerically simulate the mechanical performance of such interconnects under thermomechanical cyclic loading. The UCP model is capable of incorporating thermal and cyclic hardening effects. To make the model more objective, cyclic loading induced damage was also incorporated. The model is programmed into the commercially available finite element modeling software ABAQUS. A uniaxial tension case was analyzed to verify the model and reasonable agreement with experimental results was achieved. A typical three-dimensioned solder bump under shear deformation loading was analyzed and the strain/stress distribution within the solder bump was obtained.

Failure behavior upon shear test of 5Sn–95Pb solder bump after high temperature reliability test

The shear strength, intermetallic compound formation, and failure mechanism of high-lead solder (5Sn–95Pb) bump on flip chip under bump metallurgy, Al/Ni(V)/Cu, were investigated after thermal cycling, multiple reflow, and high-temperature aging. Two kinds of intermetallic compound, Cu3Sn and AlxNiy, were found at the interface. The Cu3Sn was formed between the solder and Ni(V) layer while AlxNiy was formed between Ni(V) and Al layer. The formation of the Cu3Sn compound will not affect the shear strength, 27–30 g, of the solder bump even after a high temperature long time aging test. However, the shear strength after the 30th reflow drops to less than 25 g, ascribed to the formation of a brittle compound, AlxNiy. The failure modes of the solder bump upon shear test were also discussed.

Parametric study on flip chip package with lead-free solder joints by using the probabilistic designing approach

The low cost tin–lead solders have been widely used in electronic industries for many years, but it is also well known to be one of the major factors for environmental pollution risk. Today, several kinds of lead-free soldered alloy have been developed as a choice for replacement of the high lead solders. However, because of the shortage of the facilitated experiment data for the thermal mechanical kinetics characterisations of these alloy, only very few parts of the parametric influence on reliability of the lead-free soldered flip chip package have been realized. In order to launch a further investigation on this issue, a numerical simulation-based parametric study on a flip chip is implemented in this paper by using the probabilistic designing approach. It combines the response surface strategy and the Monte Carlo random simulation method. The peak values of the inelastic strain and hydrostatic stress in solder joints, as well as the peel stress and the shear stress in the interface between silicon and underfill are investigated and used as response parameters. The response surface approximate functions between the output stress/strain values and the major packaging parameters are produced in the design of experiment (DOE) procedure of the numerical simulations. Statistical results of the parametric influence on lead-free soldered flip chip are also acquired by the Monte Carlo random simulation process. The results of our studies have shown that the different packaging parameters will influence the output stress/strain state of the lead-free soldered flip chip package in a very different way and degree. It is indicated that the substrate thickness is a major factor that should be taken into account for the lead-free package optimization design.

Spalling of Cu3Sn intermetallics in high-lead 95Pb5Sn solder bumps on Cu under bump metallization during solid-state annealing

We report the spalling of Cu3Sn intermetallics in high-lead 95Pb5Sn solder bumps on Cu under bump metallization (UBM) during solid state annealing. Upon reflow, the Cu3Sn intermetallics formed on Cu UBM. However, after solid state annealing at 170 °C, the Cu3Sn intermetallics spalled off from Cu UBM and the Pb phase filled the gap between the Cu3Sn intermetallics and Cu UBM. This is primarily explained by the loss of chemical adhesion between the Cu3Sn intermetallics and Cu UBM due to no additional chemical reaction. Thermodynamic principles are used to interpret the spalling phenomenon and the analysis showed that the interfacial free energy without spalling is greater than that with spalling after solid-state annealing. Spalling of the Cu3Sn intermetallics initiated at an open interface such as the edge of Cu UBM and finally extended to the flat interface at a slower rate.

Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies

Understanding the formation of voids in solder joints is important for predicting the long-term reliability of solder interconnects. This paper reports experimental research on the formation of void bubbles within molten solder bumps in flip-chip connections. For flip-chip-soldered electronic components, which have small solder volume, voids can be more detrimental to reliability. A previous theory based on thermocapillary flow reveals that the direction of heating influences void formation. Using different heating profiles, 480 solder joints of flip-chip assemblies were processed. A high-lead 90Pb∕8Sn∕2Ag solder was employed in the experiments. The solder samples were microsectioned to determine the actual size or diameter of the voids. A database on sizes and locations of voids was then constructed. More defective bumps, 80%, and higher void volume were found when the solder was melted from top (flip-chip side) to bottom (test board side). The observation on cases with melting direction from bottom to top had 40% defective bumps. The results show that a single big void is near the solder bump center with a few small voids near the edge. This supports the numerical study based on the thermocapillary theory. When the melting direction was reversed, many small voids appear near the edge. Big and middle-size voids tend to stay in the middle and outer regions from top towards middle layer of the bump. This experimental finding does not completely agree with the interpretation on the formation of voids by thermocapillary theory, however, the results do show that heat flux direction plays significant role in the formation and distribution of void bubbles in molten solder.

Electromigration at the high-Pb–eutectic SnPb solder interface

The electromigration behavior of the composite solder composed of eutectic and high-lead SnPb was investigated with 5.7 × 104 A/cm2 current stressing. Voids and hillocks were found only within the eutectic solder, and the high-lead solder remained intact. Electromigration was accelerated dramatically at 150 °C, and Pb became the major migration species of eutectic SnPb for the microstructure change at the anode. The polarity of the opposite current direction was also studied. When electrons drift from the eutectic side to the high-lead side, voids occurred at the eutectic–Cu interface whereas hillocks accumulated at the eutectic–high-lead interface. When the current was reversed, voids occurred at the eutectic–high-lead interface whereas hillocks accumulated at the eutectic–Cu interface. The anchoring effect, which results from the attaching of the lead-rich grains in the eutectic solder to the high-lead solder, was considered to retard the electromigration damage only in this current direction.

A constitutive model for a high lead solder

High lead solders have been widely used in chip scale packaging. This paper presents a comprehensive study of the various properties, such as Young's moduli, creep, plasticity, cyclic hardening and softening, fatigue, of a typical high lead solder, 96.5Pb-3.5Sn. Based on these studies, a unified creep and plasticity approach, incorporating damage, is adopted to construct a three-dimensional constitutive model for this solder. The model is then used to simulate cyclic hardening and softening behavior, isothermal and nonisothermal loading, and damage during the fatigue process. Experimental results from uniaxial tension tests are used to verify the model and good agreement has been achieved.

Application assessment of high throughput flip chip assembly for a high lead-eutectic solder cap interconnect system using no-flow underfill materials

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance.

Chip-scale packaging of power devices and its application in integrated power electronics modules

A power electronics packaging technology utilizing chip-scale packaged (CSP) power devices to build three-dimensional (3-D) integrated power electronics modules (IPEMs) is presented in this paper. The chip-scale packaging structure, termed die dimensional ball grid array (D/sup 2/BGA), eliminates wire bonds by using stacked solder joints to interconnect power chips. D/sup 2/BGA package consists of a power chip, inner solder caps, high-lead solder balls, and molding resin. It has the same lateral dimensions as the starting power chip, which makes high-density packaging and module miniaturization possible. This package enables the power chip to combine excellent thermal transfer, high current handling capability, improved electrical characteristics, and ultralow profile packaging. Electrical tests show that the V/sub CE/(sat) and on-resistance of the D/sup 2/BGA high speed insulated-gate-bipolar transistors (IGBTs) are improved by 20% and 30% respectively by eliminating the device wirebonds and other external interconnections, such as the leadframe. In this paper, we present the design, reliability, and processing issues of D/sup 2/BGA package, and the implementation of these chip-scale packaged power devices in building 30 kW half-bridge power converter modules. The electrical and reliability test results of the packaged devices and the power modules are reported.

Reliability evaluations of under bump metallurgy in two solder systems

Under bump metallurgy (UBM) reliability is one of the critical issues in the total reliability of a flip-chip bumping technology. Since the UBM materials and structures vary for different bumping technologies, the UBM strength and reliability need to be determined for each design and process. In addition, the stress that a UBM experiences during thermal cycles depends on the solder alloy used in the interconnect. Different solder alloys require different UBM structures and strengths to achieve good reliability in thermal cycling. In this study, a simplified stress model is developed to determine the UBM stress during thermal cycling. A simplified stress model for the UBM strength is also developed. These models are used to predict the stress and strength of the UBM under the die pull test and the thermal cycle conditions for both eutectic and high lead solder systems. A methodology for using the pull test results to evaluate UBM reliability is also discussed. This methodology can be extended to the studies of UBM's with other solder systems such as lead free solder systems.

Modeling the atomic transport kinetics in high-lead solders

The atomic mobilities of Au, In, Pb, and Sn in face-centered cubic Pb-Sn and Pb-In alloys are modeled using the available literature data. A set of parameters describing the composition and temperature dependence of diffusional mobility are provided. The calculated tracer diffusivities of Pb in ternary Pb-Sn-In and Pb-Sn-Au alloys are in very good agreement with the experimental data. Using the model parameters, both tracer and chemical diffusivities can be calculated in the composition and temperature ranges where experimental data is not available. On the assumption of local equilibrium, the simulation of dissolution kinetics of Pd in liquid Pb is demonstrated. The major source of discrepancy between the calculated and experimental diffusion profiles is the uncertainty of the atomic transport kinetics data in the liquid phase. The implications of current kinetic modeling are discussed briefly.

Reactions of high lead solders with BIOACT EC-7R semi-aqueous cleaning reagents

Due to environmental concerns, terpene-based cleaning fluids have replaced Freon in cleaning baths at several AT&T manufacturing sites. The terpene fluids are employed in a semi-aqueous process and, typically, are used to deflux circuit boards where most of the interconnections are formed using 60Pb/40Sn solder. Recently, the use of terpene cleaning BIOACT EC-7R was extended to thin film ceramic substrates where high lead solder (95Pb/5Sn) forms the interconnection. In the presence of high lead solder, EC-7R quickly changes from colorless to bright yellow. In addition, the cleaning process deteriorates and residues are found on the circuits. The goal of the work discussed below is to elucidate the reactions between the circuit metallurgy and the EC-7R chemical composition. A matrix experiment was performed where EC-7R and its component chemicals were reacted with pure lead, tin, copper, and two high lead solders (98Pb/2Sn and 95Pb/5Sn) for three months. In a second experimental group, 95Pb/5Sn solder was reacted with EC-7R containing varying amounts of water. Precipitates were observed in many reaction vessels, especially when water and high lead content were present. The precipitates could be responsible for the residues found in the production baths. Finally, we studied the reaction mixtures and determined some of the EC-7R bath oxidation mechanisms using UV-visible spectroscopy, and gas chromatography/mass spectroscopy (GC/MS). These results were used to formulate a high performance EC-7R, to monitor the EC-7R bath, and maintain longer lasting baths.

Effect of grain boundary failure on the fatigue life of high-lead SnPb solders: Vaynman, S. and Fine, M.E. Scr. Metall. Mater. Sept. 1990 24, (9), 1737–1739

A series of rolling contact fatigue tests were conducted on TIN coated 4118 carburized steel rollers against AISI 52100 steel disc using a two disk machine. Morphological pictures display features of shell pattern at the edge of spalls showing signs of crack propagation. The number and size of spalls are evaluated quantitatively and illustrate progressive damage of contact surfaces. Cross-sectional microstructure exhibits micro-crack propagation in the coating layer. Fatigue damage data indicates that thinner coatings result in a substantial improvement in the rolling contact fatigue life, and thicker coatings generate debonding or delamination more readily. Based on the patterns of micro-cracks and the morphology of spalled areas, failure mechanism of coated contact is suggested.

Presence of Anelastic Strains in High Lead Solders at Ambient and High Temperatures

AbstractWe had reported last year that cyclically tested Pb/Sn solders of different compositions exhibited a complicating anelastic effect. The storage and recovery of anelastic strains suppresses damaging creep strain from being stored thus causing non-conservative life prediction estimates and results in complications with respect to accelerated testing. These complications were at that time believed to be characteristic of only eutectic solders at near ambient temperatures. We now find that said complications exist for high end Pb solders and at higher temperatures. Strain rate behavior of high lead solders indicate that a different failure mechanism might exist at temperatures where the material exists as a two phase and in regimes where it exists as a solid solution. Experiments conducted to determine the effect of grain size on accelerated cycling indicated that recrystallization of large grains occurs due to cycling at high temperatures. At ambient temperature, which is greater than half the absolute melting temperature of 90/10 Pb/Sn, it was observed that large grains suppress creep.

Effect of grain boundary failure on fatigue life of high-lead SnPb solder

Effect of grain boundary failure on fatigue life of high-lead SnPb solder

Micromechanical Method to Predict Fatigue Life of Solder

Fatigue lifetimes of low-tin high-lead and tin-lead eutectic solders under total strain controlled tension-tension tests were studied in this paper. Based on the stress and strain micro-macro correlations, a modified Coffin-Manson law is obtained. The modified lifetime prediction formulas which had been used to predict the fatigue lifetime for low-tin high-lead solder, exhibiting cyclic hardening and then saturation, was found to apply to the eutectic solder, where substantial cyclic softening has been observed. This micromechanically based approach allows one to model the known physical phenomena in solders by modifying the appropriate parameters in the predictive micromechanically based constitutive equations.