High K Research Articles

Super High-k Unit-Cell-Thick α-CaCr2O4 Crystals.

High-dielectric-constant (high-k) insulators are indispensable components to integrate semiconductors into metal-oxide-semiconductor field-effect transistors with sub-10 nm channel length, where the equivalent oxide thickness (EOT) of high-k insulator needs to be decreased to subnanometer scale. The traditional insulators, including Al2O3, SiO2, and HfO2, fit well with the existing silicon industry but suffer from serious degeneration of insulating properties, such as large leakage currents caused by high-density borders and interface traps, when their thicknesses are reduced to a few nanometers. Here, we synthesize a high-quality nonlayered ultrathin α-CaCr2O4 crystal down to unit-cell thickness (∼1.2 nm) by an elements slow-supply chemical vapor deposition (CVD) method. The unit-cell-thick α-CaCr2O4 crystals show a super high dielectric constant of 87.34, which is over 20 times higher than that of well-known layered insulator h-BN and corresponds to an EOT below 1 nm. Furthermore, it has a high breaking strength (39 GPa) and excellent stability. This strategy can also be used to fabricate other ultrathin ternary oxides, such as high-k ultrathin FeNb2O6 crystals, demonstrating the universality of the CVD method.

Stabilization of Tetragonal Phase in Hafnium Zirconium Oxide by Cation Doping for High-K Dielectric Insulators.

As electronic circuit integration intensifies, there is a rising demand for dielectric insulators that provide both superior insulation and high dielectric constants. This study focuses on developing high-k dielectric insulators by controlling the phase of the Hf0.5Zr0.5O2 (HZO) film with additional doping, utilizing yttrium (Y), tantalum (Ta), gallium (Ga), silicon (Si), and aluminum (Al) as dopants. Doping changes the ratio of tetragonal to monoclinic phases in doped HZO films, and Y-doped HZO (Y:HZO) films specifically exhibit a high tetragonal phase ratio and a dielectric constant of 40.9, indicating superior insulating properties compared to undoped HZO films. To clarify the fundamental mechanism driving the enhancement in dielectric properties, we have carried out various analyses combined with density functional theory (DFT) calculations. Through the optimization of the post-deposition annealing (PDA) process and the heterojunction structure with Al2O3, an Al2O3/Y:HZO heterojunction with a high dielectric constant and even lower leakage current compared to a single layer was developed. The thin-film transistor (TFT) with the Au/Ti/amorphous InGaZnO4 (a-IGZO)/Al2O3/YHZO/TiN heterojunction structure exhibits low subthreshold swing (SS) values within a narrow gate-source voltage (Vsg) range. This study advances knowledge on how the controlled-phase doped HZO films affect the dielectric constant and leakage current and will contribute to semiconductor technology advancements by overcoming the limitations of conventional high-k dielectric insulators.

Device to circuit level implementation of JL-NSFET for DC/analog/RF applications at sub-5nm technology node: Design optimization and temperature analysis

Abstract ABSTRACT: This manuscript introduces, for the first time, a novel approach that incorporates a comprehensive analysis of sheet variations (1-5) and every individual sheet wise temperature variations, and as well as an investigation of various GS high-k gate dielectrics in Junction-less (JL) Nanosheet FET (JL-NSFET). The study starting from device level (Digital/Analog/Radio Frequency) to circuit (CMOS Inverter and ring oscillator) as a whole package is investigated through well calibrated TCAD simulation and the results portrayed. NSFETs are the ultimate choice for integrated circuits (ICs) at sub-5nm technology node. The notion of this paper is to design and optimization of NSFET with GS high-k gate dielectrics (Al2O3, HfO2, ZrO2 and TiO2) Initially. The switching/analog and RF metric revels that HfO2 is superior in terms SS, switching applications and more compactable with CMOS process. Further, adding number of sheets and temperature variation has been done later. As number of sheets increases, the effective channel width increases, electric field distribution takes place evenly and enhanced gate control owing to improved I_ON, I_ON/I_OFF ratio, SS and DIBL. However, increasing the number of vertical channel layers (sheets) more than 2 results into diminished analog/RF performance of JL-NSFET owing to increased parasitic capacitances. Further, the impact of temperature variations (250K to 450K) studied for different sheet variations (1 to 5) and noticed that analog/RF such as gm, gds, fT, TFP and GTFP are enhanced by 40.82%, 28.76%, 40.69%, 64.62% and 70.59%, respectively at lower temperature (250K). Furthermore, as the circuit level implementation CMOS inverter and 5-stage RO are examined for sheets increase, delay and EDP increases. For a CMOS inverter the NMH (0.295V) and NML (0.280V) are better at 2 sheets with a highest gain of 9.38 V/V. Hence, it is advised to use two or three sheets-based JL-NSFETs for high-performance and lower-power analog/RF applications.

WS2 Nanosheet-Based Ultrascaled Field-Effect Transistor for Hydrogen Gas Sensing: Addressing the Sensitivity-Downscaling Trade-Off.

In this paper, we propose an ultrascaled WS2 field-effect transistor equipped with a Pd/Pt sensitive gate for high-performance and low-power hydrogen gas sensing applications. The proposed nanosensor is simulated by self-consistently solving a quantum transport equation with electrostatics at the ballistic limit. The gas sensing principle is based on the gas-induced change in the metal gate work function. The hydrogen gas nanosensor leverages the high sensitivity of two-dimensional WS2 to its sur-rounding electrostatic environment. The computational investigation encompasses the nanosensor's behavior in terms of potential profile, charge density, current spectrum, local density of states (LDOS), transfer characteristics, and sensitivity. Additionally, the downscaling-sensitivity trade-off is analyzed by considering the impact of drain-to-source voltage and the electrostatics parameters on subthreshold performance. The simulation results indicate that the downscaling-sensitivity trade-off can be optimized through enhancements in electrostatics, such as utilizing high-k dielectrics and reducing oxide thickness, as well as applying a low drain-to-source voltage, which also contributes to improved energy efficiency. The proposed nanodevice meets the prerequisites for cutting-edge gas nanosensors, offering high sensing performance, improved scaling capability, low power consumption, and complementary metal-oxide-semiconductor compatibility, making it a compelling candidate for the next generation of ultrascaled FET-based gas nanosensors.

Fabrication and electrical properties of flexible polymer-based MIM capacitors of high-k nanolaminate dielectrics of HfO2–SnO2–TiO2 with ultrathin Al2O3 insertion layer by plasma-enhanced atomic layer deposition

Abstract Flexible metal–insulator–metal (MIM) capacitors of high-k nanolaminate HfO2–SnO2–TiO2 thin films were fabricated on several polymer substrates of polyethylene terephthalate, polyimide and epoxy resin at 80 °C by plasma-enhanced atomic layer deposition. The electrical properties were optimized by adjusting the sub-cycle ratio of Hf: Sn: Ti to 6: 5: 4. In order to reduce the leakage current density of flexible capacitors, the ultrathin Al2O3 layer varying from 0.5 to 1.5 nm was inserted to form Al2O3/HfO2–SnO2–TiO2/Al2O3 stacking capacitors. The effect of the Al2O3 insertion layer thickness and the super-cycle number of HfO2–SnO2–TiO2 on the capacitance density, leakage, and quadratic voltage linearity was investigated. Under optimal processing, flexible MIM capacitors could stand 40 000 bending cycles at curvature radius of 8.2 mm, indicative of better electrical stability. Moreover, compared with the polymer-based HfO2–SnO2–TiO2 capacitors, the introduction of 1 nm Al2O3 ultrathin layer greatly decreases the leakage current density by 4 orders of magnitude (10−8 A cm−2) with relative lower voltage linearity (350–540 ppm V−2), but the capacitance density also declines (∼3 fF μm−2) simultaneously. Despite this, the method of inserting Al2O3 ultra-thin layer is still an effective method to improve the electrical performances of polymer-based HfO2–SnO2–TiO2 nanolaminate capacitors for flexible electronics.

Enhanced Oxidation Resistance and Interface Stability of Atomic-Layer-Deposited MoNx Electrodes via TiN Passivation for DRAM Cell Capacitor Applications.

The continuous miniaturization of dynamic random-access memory (DRAM) capacitors has amplified the demand for electrode materials featuring specific characteristics, such as low resistivity, high work function, chemical stability, excellent interface quality with high-k dielectrics, and superior mechanical properties. In this study, molybdenum nitride (MoNx) films were deposited using a plasma-enhanced atomic layer deposition (PEALD) employing bis(isopropylcyclopentadienyl)molybdenum(IV) dihydride and NH3 plasma for DRAM capacitor electrode applications. Depending on the deposition temperatures of the PEALD MoNx films ranging from 200 to 400 °C, the Mo/N ratio and crystal structure varied, transitioning from the cubic NaCl-B1-type MoN phase with Mo/N ratio of 1.4 to the cubic γ-Mo2N phase with Mo/N ratio of 1.9. Notably, MoNx films grown at 400 °C exhibited low resistivity (435 μΩ·cm), a high work function (5.28 eV), and superior mechanical hardness (11.3 GPa) compared to ALD TiN films. Despite these excellent properties, the PEALD MoNx electrode demonstrated insufficient chemical stability, particularly in terms of oxidation resistance and interface quality with ALD HfxZr1-xO2 (HZO) films. This resulted in poor morphology and the formation of significant oxygen-deficient HZO layers (such as HfO2-x), leading to considerable degradation in the electrical performance of metal-insulator-metal (MIM) capacitors. To mitigate this issue, a thin (2.5-14 nm) ALD TiN layer was introduced as a passivation layer between the MoNx bottom electrode and HZO dielectric. The TiN-passivated MoNx (TiN/MoNx) electrode showed substantially enhanced oxidation resistance and reduced interfacial reactions with the HZO dielectric. Consequently, MIM capacitors with TiN/MoNx bottom electrodes demonstrated outstanding electrical performance, including excellent dielectric properties, low leakage current density, and high mechanical strength. Hence, this study proposes a promising candidates for storage nodes in the next-generation DRAM capacitors.

Liquid Metal Oxide-Assisted Integration of High-k Dielectrics and Metal Contacts for Two-Dimensional Electronics.

Two-dimensional van der Waals semiconductors are promising for future nanoelectronics. However, integrating high-k gate dielectrics for device applications is challenging as the inert van der Waals material surfaces hinder uniform dielectric growth. Here, we report a liquid metal oxide-assisted approach to integrate ultrathin, high-k HfO2 dielectric on 2D semiconductors with atomically smooth interfaces. Using this approach, we fabricated 2D WS2 top-gated transistors with subthreshold swings down to 74.5 mV/dec, gate leakage current density below 10-6 A/cm2, and negligible hysteresis. We further demonstrate a one-step van der Waals integration of contacts and dielectrics on graphene. This can offer a scalable approach toward integrating entire prefabricated device stack arrays with 2D materials. Our work provides a scalable solution to address the crucial dielectric engineering challenge for 2D semiconductor-based electronics.

Ultraflat single-crystal hexagonal boron nitride for wafer-scale integration of a 2D-compatible high-κ metal gate.

Hexagonal boron nitride (hBN) has emerged as a promising protection layer for dielectric integration in the next-generation large-scale integrated electronics. Although numerous efforts have been devoted to growing single-crystal hBN film, wafer-scale ultraflat hBN has still not been achieved. Here, we report the epitaxial growth of 4 in. ultraflat single-crystal hBN on Cu0.8Ni0.2(111)/sapphire wafers. The strong coupling between hBN and Cu0.8Ni0.2(111) suppresses the formation of wrinkles and ensures the seamless stitching of parallelly aligned hBN domains, resulting in an ultraflat single-crystal hBN film on a wafer scale. Using the ultraflat hBN as a protective layer, we integrate the wafer-scale ultrathin high-κ dielectrics onto two-dimensional (2D) materials with a damage-free interface. The obtained hBN/HfO2 composite dielectric exhibits an ultralow current leakage (2.36 × 10-6 A cm-2) and an ultrathin equivalent oxide thickness of 0.52 nm, which meets the targets of the International Roadmap for Devices and Systems. Our findings pave the way to the synthesis of ultraflat 2D materials and integration of future 2D electronics.

Influence of High-κ Dielectrics Integration on ALD-Based MoS2 Field-Effect Transistor Performance.

The integration of high-κ dielectrics on MoS2 field-effect transistors (FETs) is essential for the realization of MoS2 in ultrascaled nanoelectronic devices and circuits. Most studies covering this topic are based on exfoliated MoS2 flakes or chemical vapor deposition (CVD) grown MoS2 films, whereas other techniques, such as atomic layer deposition (ALD), are also gaining attention for the growth of MoS2 in recent years. In this work, we grow large-area MoS2 by means of plasma-enhanced (PE-)ALD and evaluate the influence of high-κ dielectrics on the properties of ALD-based MoS2 FETs through electrical characterization combined with surface-chemical and high-resolution scanning transmission electron microscopy (HR-STEM) analyses. We grow HfO x , AlO x , or both by means of PE-ALD or thermal ALD on our fabricated devices and show that, in addition to the dielectric constant, three other major parameters related to the processing of the dielectrics can simultaneously affect the MoS2 FET electrical characteristics and govern its doping. These parameters are the stoichiometry of the dielectric, its carbon impurity content, and the degree to which the MoS2 surface oxidizes upon the dielectric growth. When grown at 100 °C, our HfO x films are oxygen-vacant whereas our AlO x films are oxygen-rich. In addition, carbon impurities are incorporated into the dielectrics at low deposition temperatures, being one of the likely causes of the MoS2 FET overall n-type performance in all of the studied cases. Our investigations also reveal that PE-ALD of HfO x or AlO x oxidizes the MoS2 surface, whereas thermal ALD AlO x leaves MoS2 almost intact. In this respect, if thermal ALD AlO x of proper thickness is grown between MoS2 and HfO x , it can reduce the degree to which the MoS2 surface oxidizes by HfO x and meanwhile improve the total dielectric constant, altogether leading to the most optimal electrical performance in ALD-based MoS2 FETs.

The Impact of ALD Precursor Choice on Nucleation and Growth of Dielectrics on 2D Materials

Recently, atomically thin two-dimensional (2D) transition metal dichalcogenides (TMDs) have received significant attention due to their unique optical and electrical properties, lending themselves to exciting applications such as microelectronics, sensing, catalysis, photonics, and more. The properties of TMDs can be acutely impacted by their environment due to their atomic thinness. For instance, in a TMD-based transistor with a high-k dielectric surrounding the TMD semiconductor, the dielectric could dope the channel via charge transfer; it can improve charge carrier mobility by screening the impact of charged impurities on scattering; or it can worsen charge carrier mobility by introducing defect states or interfacial roughness. As such, the quality and nature of the dielectric is critical, and ultimately those properties are determined by the means of dielectric deposition. Atomic layer deposition (ALD) is a common thin film deposition technique used for depositing high-k dielectrics for transistor devices. ALD relies on sequential self-limiting reactions between a precursor or co-reactant and a surface in order to deposit a material in a layer-by-layer manner with a high degree of control over thickness, composition, and uniformity. However, the ideal basal planes of 2D materials possess no dangling bonds or reactive functional groups, making their surfaces largely inert to ALD chemistry. Hence, when conventional ALD is performed on TMDs, nucleation and growth proceeds only at defect sites, grain boundaries, and the more reactive edge sites. This sparse nucleation leads to poor quality films of low density, high surface roughness, and pinholes.In this work, we employ physisorption-assisted ALD processes and study the nucleation and quality of the deposited dielectrics. We deposit AlOx on atomically thin monolayer MoS2 (itself on SiO2/Si) using a series of ALD precursors in order to investigate the impact of the ALD precursor on nucleation. Using scanning electron microscopy (SEM), we study film nucleation and continuity as a function of ALD precursor, cycle number, and temperature. After optimizing each process for each precursor in terms of temperature and purge time for maximized nucleation, we fabricate transistor devices in which the deposited AlOx serves as a seed layer for high-k HfO2 deposition to create the gate stack. Au contacts and a Pd top gate were used to complete the devices. Using x-ray photoelectron spectroscopy (XPS) and electrical testing, we investigate the character of the dielectric/MoS2 interface. We observe that the precursor used in the ALD process can lead to a wide range of coverages, with more conventional precursors resulting in sparse coverage, and novel precursors introduced in this study leading to nearly full coverage after just 3 nm of AlOx is deposited. We hypothesize that the improved coverage for the novel precursor is the result of enhanced interactions between the precursor and the 2D material due to its particular chemical structure. The reduced nucleation delay leads to a denser, smoother film with fewer defects at the 2D/3D material interface. The devices fabricated using the novel precursor and improved dielectric show excellent performance such as good on/off ratios (106), small device-to-device variation (ΔV T < 1 V), and low effective oxide thickness (~1 nm). This work provides useful insights into how ALD precursors could be designed to improve the quality of dielectrics on 2D materials, potentially improving the viability of 2D materials for wide ranging applications.

Ab Initio Materials Modeling of Point Defects in a High-κ Metal Gate Stack of Scaled CMOS Devices: Variability Versus Engineering the Effective Work Function

Ab Initio Materials Modeling of Point Defects in a High-κ Metal Gate Stack of Scaled CMOS Devices: Variability Versus Engineering the Effective Work Function

Nonideality in Arrayed Carbon Nanotube Field Effect Transistors Revealed by High-Resolution Transmission Electron Microscopy.

High density and high semiconducting-purity single-walled carbon nanotube array (A-CNT) have recently been demonstrated as promising candidates for high-performance nanoelectronics. Knowledge of the structures and arrangement of CNTs within the arrays and their interfaces to neighboring CNTs, metal contacts, and dielectrics, as the key components of an A-CNT field effect transistor (FET), is essential for device mechanistic understanding and further optimization, particularly considering that the current technologies for the fabrication of A-CNT wafers are mainly laboratory-level solution-based processes. Here, we conduct a systematic investigation into the microstructures of A-CNT FETs mainly via cross-sectional high-resolution transmission electron microscopy and tentatively establish a framework consisting of up to 11 parameters which can be used for structure-side quality evaluation of the A-CNT FETs. The parameter ensemble includes the diameter, length (or terminal), and density distribution of CNTs, radial deformation of CNTs, array alignment defects, surface crystallography facets of contact metal, thickness distribution of high-k dielectrics (HfO2), and the contact ratios for the CNT-CNT, CNT-metal, CNT-dielectric, and CNT-substrate interfaces. Enriched array alignment defects, i.e., bundle, stacking, misorientation, and voids, are observed with a total ratio sometimes up to ∼90% in pristine A-CNTs and even up to ∼95% after the device fabrication process. Thus, they are suggested as the prevalent performance-limiting factors for A-CNT FETs. Complex interfacial structures are observed at the CNT-CNT, CNT-metal contact, and CNT-high-k dielectric interfaces, making the local environment and the property of each component CNT involved in an A-CNT FET distinct from others in terms of the diameters, radial deformation, and interactions with the local surroundings (mainly through van der Waals interactions). The present study suggests further improvements on the fabrication technology of A-CNT wafers and devices and mechanistic investigations into the impacts of complex array alignment defects and interface structures on the electrical performance of A-CNT FETs as well.

Performance enhancement of 4H-SiC superjunction trench MOSFET with extended high-K dielectric

This paper proposes a 4H-SiC superjunction trench MOSFET with extended high-K dielectric under metal gate (EHK SJ-TMOS). The characteristics of EHK SJ-TMOS include the use of the high-K (HK) dielectric as the gate dielectric and the extension of the HK dielectric as a deep trench into the N-type drift region. The extended HK trench effectively modulates the electric field distribution in the SJ drift region, which improves the breakdown voltage (BV). The introduction of HK dielectric also assists in depleting the SJ drift region, which enables the drift region of EHK SJ-TMOS to use a higher doping concentration, thereby reducing Ron,sp. Furthermore, the application of high-K gate dielectric alleviates the high gate oxide electric field problem in conventional SiC superjunction trench MOSFETs (SiC SJ-TMOS). The simulation results demonstrate that EHK SJ-TMOS exhibits a 59.2 % reduction in Ron,sp, a 2.4 % increase in BV, and a 156.5 % improvement in the FOM (FOM = BV2/Ron,sp) compared to the SiC SJ-TMOS, indicating enhanced performance.

Direct Growth of Bi2SeO5 Thin Films for High-k Dielectrics via Atomic Layer Deposition.

This study describes a modified atomic layer deposition (ALD) process for fabricating BiOxSey thin films, targeting their application as high-k dielectrics in semiconductor devices, especially for two-dimensional semiconductors. Using an intermediate-enhanced ALD technique for Bi2Se3 and a plasma-enhanced ALD process for Bi2O3, a method for the sequential deposition of Bi2SeO5 ternary films has been established. The thin film has been deposited on SiO2 and TiN substrates, exhibiting growth rates of 0.17 to 0.16 nm·cycle-1 without an incubation period, thanks to facile nucleation characteristics. The resulting film exhibited high flatness and reached 96% of its theoretical density, forming a uniform nanocrystalline structure. Electrical evaluations using metal-insulator-metal capacitors indicated the dielectric constant (∼17.6) and electrical breakdown strength (2.6 MV·cm-1), demonstrating their potential as a dielectric layer.

Enhanced electrical performance in graphene field-effect transistors through post-annealing of high-k HfLaO gate dielectrics

High-k gate dielectrics have attracted a great deal of attention in the investigation of transistors due to their unique properties such as superior gate controllability. However, their integration into graphene field-effect transistors (GFETs) remains problematic and the physical mechanisms governing the performance of these devices are still not fully understood. In this study, the effects of post-annealing on GFETs utilizing the high-k HfLaO ternary oxide as the gate dielectric were comprehensively investigated. The HfLaO film was deposited on top of graphene by magnetron sputtering, and the device performance with various post-annealing temperatures was conducted. It was found that post-annealing temperature can effectively increase the dielectric constant through balancing the oxygen-vacancy defects and moisture absorption. Both the surface morphology of HfLaO and performance of GFETs were investigated, and the fabricated GFETs exhibit notable electrical performance enhancements. Specifically, GFETs with a 200 °C post-annealed HfLaO gate dielectric demonstrate the optimal device performance, featuring a minimal Dirac point voltage (VDirac) of 1.1 V and a minimal hysteresis (ΔVDirac) of 0.5 V. The extracted hole and electron mobilities are 4012 and 1366 cm2/V · s, respectively, nearly one order of magnitude higher than that of GFETs with as-deposited HfLaO. This work outperforms other existing GFETs utilizing high-k gate dielectric and chemical vapor deposition grown graphene in terms of both carrier mobility and on–off ratio. It is also noted that the excessive post-annealing temperature can negatively impact the GFET performance through introducing oxygen vacancies, increasing the surface roughness, lowering the breakdown voltage, and inducing recrystallization.

Equivalent circuit fitting method for microwave characterisation of low-k dielectric thin films

Abstract A new equivalent circuit fitting analysis scheme is proposed to analyse the measured data of test structures originally developed to characterise high-κ dielectrics at frequencies up to 5 GHz (Zhengxiang et al 1998 IEEE Trans. Electron Devices 45 1811–6). It is compared to an extension of the analysis which can be used for high-κ dielectrics at up to 50 GHz (Rundqvist et al 2004 Integr. Ferroelectr. 60 1–19). The proposed scheme focuses on the accurate characterisation of low-κ dielectrics, which exhibit greater sensitivity to various parasitics. The scheme utilises the same concentric capacitor devices and measurement setup as the original method, maintaining the advantage of ease in fabrication of the original approach. The physical model employed in the analysis step of the original method, which tended to overestimate the dielectric permittivity, has been enhanced by incorporating fringing fields and a parasitic gap capacitance as circuit elements. The accuracy of the new approach is validated using experimental data, demonstrating its ability to more accurately determine the dielectric permittivity compared to the original method.

Hypoeutectic Liquid Metal Printing of 2D Indium Gallium Oxide Transistors.

2D native surface oxides formed on low melting temperature metals such as indium and gallium offer unique opportunities for fabricating high-performance flexible electronics and optoelectronics based on a new class of liquid metal printing (LMP). An inherent property of these Cabrera-Mott 2D oxides is their suboxide nature (e.g., In2O3-x), which leads high mobility LMP semiconductors to exhibit high electron concentrations (ne >1019cm-3) limiting electrostatic control. Binary alloying of the molten precursor can produce doped, ternary metal oxides such as In-X-O with enhanced electronic performance and greater bias-stress stability, though this approach demands a deeper understanding of the native oxides of alloys. This work presents an approach for hypoeutectic rapid LMP of crystalline InGaOx (IGO) at ultralow process temperatures (180°C) beyond the state of the art to fabricate transistors with 10X steeper subthreshold slope and high mobility (≈18cm2Vs-1). Detailed characterization of IGO crystallinity, composition, and morphology, as well as measurements of its electronic density of states (DOS), show the impact of Ga-doping and reveal the limits of doping induced amorphization from hypoeutectic precursors. The ultralow process temperatures and compatibility with high-k Al2O3 dielectrics shown here indicate potential for 2D IGO to drive low-power flexible transparent electronics.

Epitaxial Integration of Transferable High-κ Dielectric and 2D Semiconductor.

The synthesis of high-dielectric-constant (high-κ) dielectric materials and their integration with channel materials have been the key challenges in the state-of-the-art transistor architecture, as they can provide strong gate control and low operating voltage. For next-generation electronics, high-mobility two-dimensional (2D) layered semiconductors with dangling-bond-free surfaces and an atomic-thick thickness are being explored as channel materials to achieve shorter channel lengths and less interfacial scattering. Nowadays, the integration of high-κ dielectrics with high-mobility 2D semiconductors mainly relies on atomic layer deposition or transfer stacking, which may cause several undesirable problems, such as channel damage and interface traps. Here, we demonstrate the integration of high-mobility 2D semiconducting Bi2O2Se with transferable high-κ SrTiO3 as a 2D field-effect transistor by direct epitaxial growth. Remarkably, such 2D heterostructures can be efficiently transferred from the water-soluble Sr3Al2O6 sacrificial layer onto arbitrary substrates. The as-fabricated 2D Bi2O2Se/SrTiO3 transistors exhibit an on/off ratio over 104 and a subthreshold swing down to 90 mV/dec. Furthermore, the 2D Bi2O2Se/SrTiO3 heterostructures can be easily transferred onto flexible polyethylene terephthalate (PET) substrates, and the as-fabricated transistors exhibit good potential in flexible electronics. Our study opens up a new avenue for the integration of high-κ dielectrics with high-mobility 2D semiconductors and paves the way for the exploration of multifunctional electronic devices.

Effects of a Spike-Annealed HfO2 Gate Dielectric Layer on the On-Resistance and Interface Quality of AlGaN/GaN High-Electron-Mobility Transistors

Various high-k dielectrics have been proposed for AlGaN/GaN MOSHEMTs for gate leakage and drain-current collapse suppression. Hafnium oxide (HfO2) is particularly interesting because of its large bandgap, high dielectric constant, and ferroelectricity under specific phase and doping conditions. However, defects and surface scattering caused by HfO2 dissimilarity and degraded HfO2/GaN interface quality still leave the challenge of reducing the SS and Ron. In this study, we investigated the effects of the first spike-annealed HfO2 (6 nm) layer, compared with the conventional ALD-HfO2 (6 nm) layer in the HfO2 bilayer gate dielectric structure on AlGaN/GaN HEMTs. Both devices exhibit negligible hysteresis and near-ideal (~60 mV/dec) subthreshold slopes of more than three orders of magnitude. The device with the first annealed HfO2 layer exhibited a reduced Ron with notably less gate bias dependency and enhanced output current. On the other hand, the capacitance–voltage and conductance methods revealed that the border and interface trap densities of the device were inferior to those of the conventional HfO2 layer. The trade-off between enhanced electrical performance and oxide traps is discussed based on these results.

Revealing the controlling mechanisms of atomic layer etching for high-k dielectrics in conventional inductively coupled plasma etching tool

The possibilities of optimization of the two-step atomic layer etching process for HfO2 in conventional plasma etching tools were studied. The surface modification step was realized in Ar/CF4/H2 plasma, and the reaction between the modified layer and the surface was activated by Ar ion bombardment from the plasma in the second step. Investigation of the effects of activation step duration, DC bias during activation, and Ar plasma density was carried out. The mechanism of the etching process has been shown to involve fluorination of oxide during the modification step and subsequent removal of fluorine-containing particles at the activation step. An increase in parasitic sputtering rate and lower process saturation with the growth of DC bias during activation was demonstrated. The advantage of the ALE process in lower surface roughness over the conventional etching process was shown. Similar etching characteristics of HfO2 and ZrO2 suggest a similarity in the etching process for the mixed hafnium-zirconium oxide material.