High-k Materials Research Articles

Anisotropic dielectric dispersions and thermal behaviors in highly textured BN thin films for heat self-dissipating electronics

Mainstream high-k gate materials, such as SiO2, Al2O3, and HfZrO2, are in demand for modern electronics. However, these dielectrics possess lower thermal conductivity, significantly limiting thermal dissipation in electronic devices. Herein, we propose the utilization of complementary metal-oxide semiconductor- (CMOS) compatible high power impulse magnetron sputtering (HiPIMS) for the mass production of highly textured hexagonal boron nitride (h-BN) on (100)-, (110)-, and (111)-oriented SrTiO3 substrates. The as-prepared films exhibit distinct vertical alignments, as evidenced by HRTEM and FTIR analysis. Notably, the R value, ranging from 0.46 to 0.50, is associated with the stress in the film. Importantly, distinct anisotropies in thermal conductivity, dielectric constant, and optical band gap are observed. Furthermore, the values of thermal conductivity in these highly textured h-BN films are 4.5, 5.7, and 5.3 Wm−1K−1, which is almost three times larger than those of SiO2 (1.4 Wm−1K−1) and Al2O3 (1.35 Wm−1K−1), and even an order of magnitude larger than that of HfZrO2 (0.67 Wm−1K−1). The combination of excellent dielectric characteristics, favorable thermal conductivity, and superior stability over a broad temperature range makes this novel material outperform conventional dielectric gate materials in high-power electronics applications.

Quantum transport in WSe2/SnSe2 tunneling field effect transistors with high-k gate dielectrics

Combining two-dimensional materials and high-k gate dielectrics offers a promising way to enhance the device performance of tunneling field-effect transistor (TFET). In this work, the device performance of WSe2/SnSe2 TFET with various gate dielectric materials is investigated based on quantum transport simulation. Results show that TFETs with high-k gate dielectric materials exhibit improved on-off ratio and enhanced transconductance. The optimized WSe2/SnSe2 TFET with TiO2 gate dielectrics achieves an on-state current of 1560 μA/μm and a subthreshold swing (SS) of 48 mV/dec. The utilization of high-k gate dielectric materials results in shorter tunneling length, higher transmission efficiency, and increased electron tunneling probability. The performance of the WSe2/SnSe2 TFET would be affected by the presence of the underlap region. Moreover, WSe2/SnSe2 TFETs with La2O3 dielectric can be scaled down to 3 nm while meeting high-performance (HP) device requirements according to the International Technology Roadmap for Semiconductors (ITRS). This research presents a practical solution for designing advanced logic devices in the sub-5 nm technology node.

Analysis of breakdown voltage for GaN MIS-HEMT with various composite field plate configurations and passivation layers

The effects of different field plate designs on the breakdown voltage of GaN Metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) were examined in this study. The study's primary goal was to determine the dependence of breakdown voltage with respective to composite field plate designs using TCAD simulation. For devices featuring only G-FP, with a fixed gate to drain distance of 15 μm and a fixed G-FP to drain distance of 15 μm, the maximum breakdown voltage was achieved 1 μm G-FP. Breakdown voltage trends were also determined for composite field plate configurations, such as adding a source field plate (S-FP) or a drain field plate (D-FP) with a fixed 1 μm G-FP length. A further enhancement in device breakdown performance was demonstrated by employing a novel D-FP structure. A single D-FP improves the breakdown voltage from 1.4 kV (conventional breakdown voltage with 1um G-FP) to 1.6 kV when combined with 1 μm G-FP, while the novel two-step D-FP achieves a breakdown voltage of about 1.7 kV when combined with 1 μm G-FP. We also investigated the influence of high-k dielectric passivation layers on the breakdown voltage. The breakdown voltage of the devices with optimized G-FP can be further improved by using high-k dielectric material as a passivation layer. The thorough investigations contribute to a better understanding of GaN MIS-HEMT breakdown characteristics and prospective pathways for improving their performance via unique field plate designs and superior dielectric materials.

Design of Pentacene Thin-Film Transistor Based Hydrogen Gas Sensor with High-K Dielectric Materials for High Sensitivity

Electrical properties of an organic field-effect transistor were modelled in top gate top contact (TGTC) geometry and H2 gas sensors were designed for increased sensitivity based on the structure. Safety concerns related to hydrogen usage must be addressed; these hazardous characteristics include a wide flammable range (4%–75%) that results in a rapid burning velocity, a low minimum ignition energy (0.017 mJ), a high heat of combustion (143 kJ g−1), and the high diffusivity of hydrogen gas (0.61 cm2 s−1 in the air). These characteristics make it impossible to control hydrogen combustion after a specific time. All simulations were performed in the Silvaco TCAD ATLAS tool. We analysed the driving principle of gas sensors and introduced gas sensing properties in OFET using platinum metal at the gate electrode for H2 gas detection. IOFF, ION, and VTH are sensitivity parameters that alter when the metalwork function of the gate changes with respect to the gas present on it. The designed sensor was analysed for different dielectric materials. Results demonstrate that the increase in sensitivity for OFET-based H2 sensors is 73.4%, 80.7%, 90.5%, and 95.6% when the work function changes by 50, 100, 150, and 200 meV for Pt gate electrodes with an increase in dielectric value of insulating layer from SiO2 (3.9) to La2O3 (27). Results were compared with the In1-xGaxAs CGNWFET-based H2 sensor as the work function varies at 200 meV,the sensitivity enhancement with OFET-based H2 sensors is 8.09%.

Frequency doubler utilizing hetero gate dielectric tunnel field-effect transistor

With the rapid advancements in wireless communication and high-density integrated circuits, the demand for high-frequency sources has become paramount for transmitting vast amounts of information. Modern communication systems often utilize low-frequency sources at the transmitting end, converting them into high-frequency carriers through Intermediate Frequency (IF) for transmission to the receiving end. However, challenges arise in stabilizing high-frequency Voltage Controlled Oscillators (VCOs), leading to the necessity of Frequency Multipliers (FMs) in high-frequency circuits. While existing FMs face issues like harmonic distortion due to internal nonlinear devices, this paper proposes a single-device Frequency Doubler (FD) operation using Hetero-Gate Tunnel Field Effect Transistor (HG-TFET) with ambipolar characteristics. HG-TFET integrates high-κ (HK) materials and an HG structure in the gate dielectric, achieving independent control of tunneling distances and synchronous operation of source-to-channel and channel-to-drain tunneling currents (I SC and I CD) to facilitate FD operation. The paper presents the HG-TFET structure, process flow, and simulation models, followed by an exploration of its operating mechanism and characteristics. The FD circuit configuration, operational principles, and conditions for normal operation are detailed, emphasizing the importance of aligning I SC and I CD. The impact of adjusting HK lengths on I SC and I CD is analyzed, demonstrating the ability to independently control these currents through HG-TFET. Simulation results for FD operation under varying HK lengths (1–10 nm) validate the proposed approach. Additionally, the paper investigates the influence of dielectric constant (10–32) and gate dielectric thickness (2–5 nm) on FD performance, highlighting the potential for further optimization. In conclusion, this study establishes a foundation for normal FD operation through the symmetrical control of ambipolar and on currents using HG-TFET. The proposed structure and techniques open avenues for improving the efficiency and reliability of frequency-doubling applications in high-frequency circuits.

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.

Analysis of thermal stability in underlap and overlap DMG FinFETs including self-heating effects

This work investigates the impact of the self-heating effect (SHE) on SOI Dual-Material Gate (DMG) FinFETs with channel engineering including gate underlapped and overlapped structures. Both these structures are compared with conventional DMG FinFET to detect the possible effects of SHE on DC characteristics and thermal parameters. The drop rates of ON current (ION), Off-current (IOFF), Maximum transconductance (gm,max), ION/IOFF ratio, and Drain-induced barrier lowering (DIBL) are calculated to get the precise results. For extensive thermal reliability analysis, the two main distinguishing parameters lattice temperature and thermal resistance are also calculated and their dependency with gate/drain bias and operating temperature are also explored. Comparison between thin and thick BOX devices aimed at distinguishing possible effects of SHE on BOX thickness variation. The result shows that the SHE greatly improves ION/IOFF ratio by 220.8% in gate underlap structure due to large reduction in leakage current. Although lattice temperature is higher in gate overlap structure but thermal resistance decreases by 53.6 % due to its high ON current. Using high-k dielectric BOX materials, small improvement in device SHE characteristics is also accomplished.

Physical properties and mechanical stability of AlCu:XO2 (X=Hf, Zr) alloys from density functional theory (DFT): Prediction and analysis for photocatalysis and electronic devices applications

The electronic, optical and mechanical properties of AlCu:XO2 alloys (X=Hf, Zr) are investigated for the first time through the Density Functional Theory (DFT). The aim of this work is to evaluate the impact of aluminum-copper alloys on the physical response of high-k materials for both electronic and photocatalysis devices applications. It will be shown that 25% of Al is the appropriate composition leading to improved electrical and optical properties. Whereas by increasing the AlCu content (25%), the band gap energy decreases to reach 2.96 and 2.37 eV for HfO2 and ZrO2 respectively. A shift of the optical absorption to the visible light region is also observed making these configurations adequate for photocatalytic devices applications. The presence of AlCu alloy in these oxides shows that it is possible to reduce or suppress the defect states according to the electronic structure and enhance the mechanical stability of the AlCu:XO2 alloys.

Design and implementation of the logic gates using electrically doped configurable polarity control double gate tunnel FET

This paper designs and implements the basic logic and universal gates based on the proposed electrically doped, configurable polarity control double gate tunnel FET (ED-CPC-DGTFET). In contrast to the CMOS and MOSFET, the primary concern of the proposed device is to overcome the transistor count needed to design logic gates. A few compact realizations of logic gates have been reported earlier using conventional double-gate TFETs. The main key to designing and implementing logic gates with the proposed structure is controlling the channel’s tunneling barrier height by altering the gate electrode work function. Additionally, abrupt interband tunneling of TFET by varying gate bias makes the device appropriate for implementing logic gates. The proposed device has a dynamic configuration that can change from n-type to p-type DGTFET by varying the bias at PG-1 and PG-2. Since lightly doped TFETs have a low ON-state current therefore, a high-k material (HfO 2 ) is employed in place of SiO 2 on top of the source side to enhance the ON-state current. Using two-dimensional simulations, the device is designed to implement logic gates with gate lengths of 50 nm and silicon body thicknesses of 10 nm (t si ). OR and AND logic gates are implemented using the n-type ED-CPC-DGTFET structure, and universal gates are implemented using the p-type variant of the proposed ED-CPC-DGTFET structure by independently biasing the top and bottom gates against various inputs.

Investigation of thermal stress effects during annealing of hafnia-made thin film using molecular dynamics simulations

Hafnia or hafnium oxide is a high-κ dielectric material with paramount importance in the realm of semiconductor devices. Recent advancements in 3D device structures require a few nanometer-thick conformal films on non-planar substrates. During the fabrication stage, the annealing process of thin films has been discovered to mitigate delamination issues at the film-substrate interface. However, it has been observed that the residual stress, which emerges as the film cools to room temperature, may lead to delamination. In this study, we propose an idealized atomistic model to mimic the critical region of a 3D-NAND structure, to get insights into the effect of thermal stress and delamination during the annealing of hafnia-made thin film. We employ molecular dynamics simulation using charge-optimized many-body potential (COMB) to perform heating and cooling simulations for different thicknesses of the hafnia layer. Our results suggest that, during heating, as the annealing temperature increases, the severity of delamination decreases. At extremely low thickness of the hafnia layer, delamination does not occur. However, significant delamination is observed during the cooling process, especially when the high temperature gradient is high.

Voltage ramp stress based lifetime-prediction model of advanced Al-doped HfO[formula omitted] dielectric for 2.5D MIMCAPs

The reliability of an Al-doped HfO2 dielectric used in a high density 2.5D MIMCAP is investigated by constant voltage stress (CVS) and voltage ramp stress (VRS) measurements. The good agreement of the results from the two techniques allows to propose a model for lifetime prediction based on the breakdown characteristics. The extracted activation energy shows a voltage dependence associated with a change in the degradation characteristics of the high-κ material at high fields.

Modulation of electrical properties of sputtered Ta2O5 films by variation of RF power and substrate temperature

Dielectric thin films are important building blocks of microelectronic devices, and hence, research on the development of high-k dielectric thin films has drawn tremendous research interest. In this research, thin films of tantalum oxide (Ta2O5), a high-k dielectric material, are deposited on the Si substrate by the radio frequency (RF) magnetron sputtering technique. During the deposition of Ta2O5 thin film, the sputtering parameters such as sputtering power and substrate temperature were systematically varied, and post-deposition structural, morphological, and electrical properties of sputtered Ta2O5 films are studied by x-ray diffraction, Fourier transform infrared spectroscopy, atomic force microscope, capacitance–voltage (C-V) and current–voltage (I-V) measurement techniques. The annealed Ta2O5 thin film at the temperature of 900 °C for 1 h possesses polycrystalline nature with β—phase orthorhombic crystal structure. The film deposited at 150 W and substrate temperature at room temperature has shown comparatively lower surface roughness, which depicts the energy, and mobility of adatoms greatly influenced by RF power and substrate temperature. With the increase in sputtering power, the oxide charge density (Qox) is found to increase. On the other hand, Qox is found to decrease with the increase in substrate temperature. The film deposited at RF power of 150 W and substrate temperature of 300 °C is found to be of high dielectric constant, low oxide and interface charge density, and lower leakage current.

High-κ elastomer with dispersed ferroelectric nematic liquid crystal microdroplets

An emergent liquid ferroelectric material is dispersed into polydimethylsiloxane as microdroplets, realizing a stretchable and ferroelectric high-κ elastomer.

Electronic properties of ZrO2 films fabricated via atomic layer deposition on 4H-SiC and Si substrates

Being an important semiconductor material for high power applications, silicon carbide (SiC) faces the problems while used as a gate oxygen layer in traditional Si MOS devices. In view of this, an innovative approach was adopted in the present work to replace the conventional SiO2 with a high-k material (ZrO2) as the gate oxygen layer to investigate its effect on the electrical characteristics of the devices. In particular ZrO2 films were deposited on Si and SiC substrates by atomic layer deposition (ALD), and Al was used as the electrode. The atomic force microscopy (AFM) microregion scan revealed a highly flat surface with Rq < 1 nm after the ALD growth of ZrO2 layer. The sample surface analysis via x-ray photoelectron spectroscopy (XPS) suggested the presence of a small amount of ZrOx components. According to the electron energy loss spectrum (EELS), the band gap width (Eg) of this ALD ZrO2 dielectric was 5.45 eV, which met the requirements for high-quality 4H-SiC-related MOS devices. The electrical properties of the samples were then studied, and the maximum breakdown voltage of the Al/ZrO2/SiC/Al MOS structure was obtained to be 23 V, i.e., nearly twice that of the Si substrate. As for the oxide layer, the interface defect density (Dit) near the conduction band of the Al/ZrO2/SiC/Al MOS structure was only 1012 eV−1 cm−2 orders of magnitude. The Neff value (the movable charge) of the structure was also controlled at 1012 cm−2. Therefore, the overall performance of the ZrO2/SiC structure in terms of electrical properties exceeded that of the ZrO2/Si structure and previously reported counterparts. In this respect, the ZrO2/SiC MOS capacitor structure has great research potential.

Novel halogenated cyclopentadienyl hafnium precursor for atomic layer deposition of high-performance HfO2 thin film.

High dielectric constant (high-k) materials play a crucial role in modern electronics, particularly in semiconductor applications such as transistor gate insulators and dielectrics in metal-insulator-metal (MIM) capacitors. However, achieving optimal crystallinity and suppressing interfacial layer formation during deposition processes remain key challenges. To address these challenges, this study introduces a novel approach using atomic layer deposition (ALD) with a new Hf precursor incorporating an iodo ligand. The synthesized precursor, IHf, demonstrates enhanced thermal stability and reactivity, leading to superior film properties. ALD deposition of HfO2 thin films using IHf yields excellent crystallinity and effectively inhibits interfacial layer formation, resulting in enhanced capacitance density and improved leakage current characteristics in MIM capacitors. Notably, IHf-deposited HfO2 films exhibit a significant reduction in leakage current, achieving an equivalent oxide thickness of 1.73 nm at a leakage current density of 7.02 × 10-8 A cm-2 @ +0.8 V. These findings highlight the potential of IHf as a promising precursor for high-performance electronic device fabrication, paving the way for advancements in semiconductor technology.

Thermal Properties of Epoxy-GNP Based Nano-Dielectrics

This study highlights the thermal properties of nano-dielectrics materials composed of epoxy resin host and Graphene nano-platelets (GnP) have been studied. The introduction of the GnP nano-platelets (0.5, 1, 2, 3 and 5wt %) into the epoxy resin by the three roll mill technique following the Caframo mechanical mixer method is described. Asilane Coupling Agent (SCA) was used for the surface modification for better dispersion of filler in organic polymer matrix and for better compatibility between nano-platelets and host material. Thermal conductivity, glass transition temperature and thermal stability of nano-dielectrics were investigated based on the filler content. The synergistic effect was observed due to the introduction of GnP. The high-k nano-dielectric materials show better thermal conductivity and stability than that of the pure epoxy resins. The best performance of the composite is observed with 3wt% of graphene nano-platelets.

Study of Nb2O5 High-k Dielectric Material Deposited By Atomic Layer Deposition for Metal-Insulator-Metal Capacitor

Metal-Insulator-Metal (MIM) capacitors are important components in many electronic devices, including memory devices, filters, and oscillators. The performance of these devices depends strongly on the electrical properties of the dielectric layer. The application of new high-k materials can improve the properties of modern capacitors such as leakage current and capacitance density. However, it is necessary to understand the deposition conditions of both electrode and dielectric materials in order to master the dielectric properties in future MIM capacitors.One potentially interesting high-k material is niobium pentoxide (Nb2O5) with a wide band gap (3.6 eV) and high refractive index (n=2.3 @633 nm) deposited by Atomic Layer Deposition (ALD) using niobium (V) ethoxide as niobium precursor at 180°C and H2O as reaction agent and oxygen source. Nb2O5 films were deposited directly on a silicon (Si 100) substrate or on a 10nm of titanium nitride (deposited by ALD on Si substrate, n=1.4@633 nm). The Nb2O5 films were deposited with a good film thickness uniformity on the 6-inches of the wafers with a thickness ranging from 20 to 60 nm on each sample. The deposition was done under a suitable ALD temperature of 200-300 °C. In order to investigate the film growth, structure, morphology and optical properties, the samples were characterized by spectroscopic ellipsometry (SE), scanning electron microscopy (SEM), X-Ray diffraction (XRD) and atomic force microscopy (AFM). The as-deposited films were then annealed in a furnace at temperature ranging from 500 to 650°C under N2 atmosphere.Subsequently, a MIM structure (Al/Nb2O5/TiN) was produced by adding a second aluminum layer deposited at 250°C on a Nb2O5/TiN/Si stack by the sputtering method. The surface of the second electrodes was aimed to have 0.1-1.0 mm2 to confirm the surface dependency of the capacitance value. The electrical properties of Nb2O5 dielectric layer such as dielectric constant, breakdown voltage and leakage current at possible user voltage were measured on this last structure. The low leakage current density is desirable for MIM capacitors as it helps to minimize energy loss and increase the energy storage capabilities of the capacitors. The obtained J-E curve was compared to some electrical conduction mechanisms to identify its electrical conduction behaviors. The barrier height of the F-N tunneling mechanism was determined by fitting the experimental data to the F-N equation. These measurements indicate that the electrical properties of the Nb2O5 material produced by ALD with specific settings are promising for the application in capacitors. These results provide new insight into our understanding of the application of Nb2O5 realized by ALD for the MIM capacitor.

(Invited) Stacking High Mobility Channels

Beyond 3 nm node, the transistor architecture of stacked channel gate-all-around (GAA) FETs can replace FinFETs for advanced technology node due to the improvement of power, performance, and area by the enhanced short channel control, design flexibility, and drive current per footprint. High ION and small parasitic RC are the keys to extend nanosheet technologies for N+1 and N+2 nodes. To extend nanosheets to next nodes, we have demonstrated additional enabling knobs such as high mobility channels, high-k gate dielectrics, and highly stacked channels to effectively increase the ION for high performance. Beyond stacked nanosheets, new transistor architectures such as TreeFET (a combination of FinFET and stacked nanosheets) and CFET (3D stacked n and p FETs) can further enable cell height scaling. CFETs and atomic channels have potentials to be used in A5 and A2 nodes according to the transistor roadmap by IMEC [1], respectively. Note that ultrathin body as thin as 1 nm can be considered as atomic channels for nearly ideal SS and high ION/IOFF for low power application.First of all, high mobility channel material is the key factor to improve performance CV/I. As a result, Ge/GeSi and GeSn are the target high mobility channels for nFETs and pFETs, respectively. For nFETs, Ge is an attractive option for high mobility channel to boost the ION thanks to its higher electron mobility than Si [2]. For pFETs, strained GeSn has higher hole mobility than Ge to improve the ION for pFETs due to the hole effective mass reduction under compressive strain [3]. For a fixed footprint, the vertically highly stacked GAA channels can provide large ION to achieve high performance and area scaling for advanced technology node.In addition to high mobility channel, the performance of GAAFET can be improved by scaling down gate oxide thickness. However, the gate leakage problem increases with scaling down the gate oxide thickness. As a result, high-k materials were proposed as gate oxide for gate leakage reduction and performance enhancement in GAAFETs. Plasma-enhanced atomic layer deposition (PEALD) HfxZryO2 was reported to achieve high-k value by optimizing the Hf and Zr content [4], respectively. In this work, a high k value of 47 is achieved in Hf0.2Zr0.8O2 alloy. Furthermore, the high-k gate dielectrics is integrated into stacked GAAFETs successfully.However, the challenge of Ge-based channel is the large IOFF due to the small bandgap [5-7]. Ultrathin body device can effectively reduce the IOFF, but the mobility degradation is observed as the channel thickness decreases below 5nm due to surface roughness scattering. Moreover, the high mobility GeSn can afford some mobility loss due to the ultrathin body [8]. Furthermore, the ION can be further improved by channel stacking with the suppression of IOFF by the ultrathin body.For Si nanosheets, the mismatch between hole mobility and electron mobility in nanosheets [9] might lead to potential design challenges of CMOS. As a result, the TreeFET transistor architecture combining with FinFETs and stacked nanosheets is proposed [10] and experimentally demonstrated [11] as a candidate beyond nanosheets. TreeFETs with {100} surfaces can enhance the electron mobility of Si, while {110} sidewalls are beneficial to hole mobility for both Si and Ge. TreeFETs with additional fin interbridges (IB) between nanosheets can increase Weff and enhance ION per footprint for high-performance devices beyond FinFETs and stacked nanosheets.3D transistor stacking can enable further cell height scaling and extend Moore's law scaling. The pFET and nFET are able to fold on each other to reduce 50% of inverter cell area ideally in CFET [12, 13], as a promising transistor architecture beyond stacked nanosheets. As compared to the sequential 3D process, no wafer bonding or layer transfer is required in the monolithic 3D process. Moreover, monolithic 3D by epitaxy can reduce the FEOL cost and the parasitic RC as compared to sequential 3D. The high mobility channel material of GeSi is used for CFET demonstration in this work [14]. Heavily doped sacrificial layers are beneficial for S/D resistance reduction by thermal annealing during the device fabrication. Reportedly, dielectric layers in S/D regions are used for the electrical isolation between n/p FETs in CFET structure [15], but the complicated S/D recess and dual S/D selective epi regrowth are required. In this work, a simple process without S/D selective epi regrowth can achieve self-aligned CFETs with multiple P/N junction isolation to effectively reduce the leakage current. Acknowledgements- This work is supported by National Science and Technology Council (111-2218-E-002-040-MBK, 111-2634-F-A49-008-, and 111-2622-8-002-001-), Ministry of Education (NTU-CC-112L890901), and Taiwan Semiconductor Research Institute (TSRI), Taiwan. Figure 1

Synthesis of Dielectric Al-Doped HfO2 Thin Film by Polymer-Assisted Deposition

As transistors scale down, demands for high-k dielectric materials increase. Among various dielectric materials, HfO2 have drawn attention because of its large band gap, high dielectric constant, and excellent physical/chemical stability. Although several solution-based synthesis have been developed, their dielectric properties are inferior to those obtained by conventional vacuum processes (e.g., atomic layer deposition, sputtering). This study demonstrates a solution-based polymer-assisted deposition (PAD) of high-k Al-doped HfO2 thin films exhibiting excellent dielectric properties comparable to the conventional deposition methods. The PAD process enables the control of film thickness (≥3 nm) and the homogenous Al doping in the entire thin film. The key to the success is HCl-mediated coordination of metal ions and polymer. Systematic analysis on the structure and chemical composition of the dielectric layer is carried out. It is found that the phase transition from monoclinic phase to a mixture of tetragonal and amorphous phases results in excellent dielectric properties. The 7.8 nm thick thin film doped with 4.1 at% of Al exhibits a high dielectric constant of 30.2 with a high areal capacitance (674 nF cm−2 at 1.0 kHz), a low leakage current (3.3 × 10−9 A cm−2 at 2.0 MV cm−1), and a high breakdown voltage (7.7 V).

Atomic Layer Deposition of HfAlOx for High-k Gate Dielectrics

Nowadays, the downscaling of CMOS devices requires continued effort to propose high performance components with extremely compact size. Surely, this trend is not achievable without extremely enhanced High-k gate stack materials, inter alia. For years, HfO2-based dielectrics deposited using ALD (Atomic Layer Deposition) technique are perfect dielectrics of choice for various devices and applications (Memristor, resistive random access memory, ferroelectric random access memory, antiferrolectric capacitances, ferroelectric FET...).As such, HfAlOx films present a good compromise between HfO2 and Al2O3 in term of coupling properties and insulating capabilities in comparison with both single HfO2 and Al2O3 films. The purpose of this work is to evaluate binary high-k HfAlOx dielectrics deposited by ALD technique. ALD is well suited for deposition of ultrathin films with exceptional capabilities enabling precise thickness, stoichiometry control and conformal growth at atomic scale. In this work, we focused on Al2O3/HfO2 films fabricated using two approaches: (i) repeatedly alternating the deposition of two different and separate extremely thin oxides (Al2O3 and HfO2; particular focus on HfO2/Al2O3/HfO2/Al2O3/HfO2 multilayer stack with equivalent Al fraction around 30%); (ii) combination of ALD super cycles allowing the formation HfAlOx layers. We analyze the general performance and the behavior of the binary high-k HfAlOx dielectrics (10 nm thin layers deposited at 300°C using TiCl4-TMA-H2O precursors) using physico-chemical (X-ray photoelectron spectroscopy XPS, X-ray reflectometry XRR, wavelength dispersive X-ray fluorescence WDXRF) and electrical measurements (Hg probe measurements, MIM capacitance).The incorporation of Al2O3 in the composition of the HfO2 gate dielectrics allows a perfect monitoring of physico-chemical properties varying from HfO2 layers to Al2O3 layers by controlling the number of Al2O3 and HfO2 ALD cycles. In this respect, we were able to monitor the Al fraction in the range of 5% to ~86% in the mixed binary dielectrics (Figure 1: XRR density of mixed binary layers vs Al/[Al+Hf] ratio, Figure 2: Al and Hf fractions in the mixed layer determined by WDXRF and XPS analysis).The electrical characteristics of the HfAlOx dielectrics confirm the influence of the Al fraction in the HfO2 layer. The leakage currents of the mixed layers decreases with increasing the Al fraction (Figure 3: J/E characteristics of mixed and stacked HfAlOx layers). The breakdown voltages for all mixed HfAlOx layers are greater than that of reference HfO2 layer. On the other hand, the shown multilayer presents an intermediate leakage currents profiles between the two mixed HfAlOx (25%Al and 40%Al). Thus, the incorporation of Al in the construction of HfAlOx system is likely to decrease the number of defects. Furthermore, the fully integrated MIM structures exhibit areal capacitance in the range 10-15 nF/mm2 of ALD-based high-k HfAlOx (10 to 12 nm) depending on the Al fraction. Thus, ALD-HfAlOx with various composition highlight the potential tremendous for high-κ capacitances stack for CMOS semiconductor devices. Figure 1