High-k Materials Research Articles

Synthesis of Dielectric Al-Doped HfO2 Thin Film by Polymer-Assisted Deposition

As transistors scale down, demands for high-k dielectric materials increase. Among various dielectric materials, HfO2 have drawn attention because of its large band gap, high dielectric constant, and excellent physical/chemical stability. Although several solution-based synthesis have been developed, their dielectric properties are inferior to those obtained by conventional vacuum processes (e.g., atomic layer deposition, sputtering). This study demonstrates a solution-based polymer-assisted deposition (PAD) of high-k Al-doped HfO2 thin films exhibiting excellent dielectric properties comparable to the conventional deposition methods. The PAD process enables the control of film thickness (≥3 nm) and the homogenous Al doping in the entire thin film. The key to the success is HCl-mediated coordination of metal ions and polymer. Systematic analysis on the structure and chemical composition of the dielectric layer is carried out. It is found that the phase transition from monoclinic phase to a mixture of tetragonal and amorphous phases results in excellent dielectric properties. The 7.8 nm thick thin film doped with 4.1 at% of Al exhibits a high dielectric constant of 30.2 with a high areal capacitance (674 nF cm−2 at 1.0 kHz), a low leakage current (3.3 × 10−9 A cm−2 at 2.0 MV cm−1), and a high breakdown voltage (7.7 V).

Atomic Layer Deposition of HfAlOx for High-k Gate Dielectrics

Nowadays, the downscaling of CMOS devices requires continued effort to propose high performance components with extremely compact size. Surely, this trend is not achievable without extremely enhanced High-k gate stack materials, inter alia. For years, HfO2-based dielectrics deposited using ALD (Atomic Layer Deposition) technique are perfect dielectrics of choice for various devices and applications (Memristor, resistive random access memory, ferroelectric random access memory, antiferrolectric capacitances, ferroelectric FET...).As such, HfAlOx films present a good compromise between HfO2 and Al2O3 in term of coupling properties and insulating capabilities in comparison with both single HfO2 and Al2O3 films. The purpose of this work is to evaluate binary high-k HfAlOx dielectrics deposited by ALD technique. ALD is well suited for deposition of ultrathin films with exceptional capabilities enabling precise thickness, stoichiometry control and conformal growth at atomic scale. In this work, we focused on Al2O3/HfO2 films fabricated using two approaches: (i) repeatedly alternating the deposition of two different and separate extremely thin oxides (Al2O3 and HfO2; particular focus on HfO2/Al2O3/HfO2/Al2O3/HfO2 multilayer stack with equivalent Al fraction around 30%); (ii) combination of ALD super cycles allowing the formation HfAlOx layers. We analyze the general performance and the behavior of the binary high-k HfAlOx dielectrics (10 nm thin layers deposited at 300°C using TiCl4-TMA-H2O precursors) using physico-chemical (X-ray photoelectron spectroscopy XPS, X-ray reflectometry XRR, wavelength dispersive X-ray fluorescence WDXRF) and electrical measurements (Hg probe measurements, MIM capacitance).The incorporation of Al2O3 in the composition of the HfO2 gate dielectrics allows a perfect monitoring of physico-chemical properties varying from HfO2 layers to Al2O3 layers by controlling the number of Al2O3 and HfO2 ALD cycles. In this respect, we were able to monitor the Al fraction in the range of 5% to ~86% in the mixed binary dielectrics (Figure 1: XRR density of mixed binary layers vs Al/[Al+Hf] ratio, Figure 2: Al and Hf fractions in the mixed layer determined by WDXRF and XPS analysis).The electrical characteristics of the HfAlOx dielectrics confirm the influence of the Al fraction in the HfO2 layer. The leakage currents of the mixed layers decreases with increasing the Al fraction (Figure 3: J/E characteristics of mixed and stacked HfAlOx layers). The breakdown voltages for all mixed HfAlOx layers are greater than that of reference HfO2 layer. On the other hand, the shown multilayer presents an intermediate leakage currents profiles between the two mixed HfAlOx (25%Al and 40%Al). Thus, the incorporation of Al in the construction of HfAlOx system is likely to decrease the number of defects. Furthermore, the fully integrated MIM structures exhibit areal capacitance in the range 10-15 nF/mm2 of ALD-based high-k HfAlOx (10 to 12 nm) depending on the Al fraction. Thus, ALD-HfAlOx with various composition highlight the potential tremendous for high-κ capacitances stack for CMOS semiconductor devices. Figure 1

RETRACTED ARTICLE: Exploring High-Temperature Reliability of 4H-SiC MOSFETs: A Comparative Study of High-K Gate Dielectric Materials

RETRACTED ARTICLE: Exploring High-Temperature Reliability of 4H-SiC MOSFETs: A Comparative Study of High-K Gate Dielectric Materials

Chemisorption and Surface Reaction of Hafnium Precursors on the Hydroxylated Si(100) Surface

Hafnium oxide (HfO2) is widely recognized as one of the most promising high-k dielectric materials due to its remarkable properties such as high permittivity, wide band gap, and excellent thermal and chemical stability. The atomic layer deposition (ALD) of HfO2 has attracted significant attention in recent decades since it enables uniform and conformal deposition of HfO2 thin films on various substrates. In this study, we examined the initial surface reactions of a series of homoleptic hafnium precursors on hydroxylated Si(100) surfaces using density functional theory calculations. Our theoretical findings align with previous experimental studies, indicating that hafnium amides exhibit higher reactivity compared to other precursors such as hafnium alkoxides and hafnium halides in surface reactions. Interestingly, we found that the chemisorption and reactivity of hafnium precursors are considerably affected by their thermal stability and size. For alkoxide precursors, which have similar thermal stabilities, the size of alkoxide ligands is an important factor in determining their reactivity. Conversely, the reactivity of hafnium halides, which have ligands of similar sizes, is primarily governed by their thermal stability. These insights are valuable for understanding the surface reaction mechanisms of precursors on hydroxylated Si(100) surfaces and for designing new materials, particularly heteroleptic precursors, in future research.

Microstructure, dielectric and optical properties of transparent flexible high-k Bi1.5MgNb1.5O7 thin films

High-k insulation materials can effectively reduce the operating voltage and leakage current of TFT devices, improving device performance owing to their high dielectric constant and insulation properties. Transparent flexible Bi1.5MgNb1.5O7 (BMN) dielectric thin films were synthesized via RF magnetron sputtering at room temperature. The impact of argon to oxygen ratio (Ar:O2) on the microstructure, elemental composition, optical, and dielectric properties of the BMN dielectric films was systematically explored. X-ray photoelectron spectroscopy, scanning electron microscopy, and optical property tests revealed that the proportion of metallic Bi and grain size play crucial roles in the optical transmittance and optical bandgap of the BMN films. Moreover, the dielectric properties were significantly influenced by the space charge polarization resulting from the percolation capacitance model formed by metallic Bi in the samples. To further optimize the dielectric properties of BMN films, sandwich structured OAO (BMNO/BMNAr/BMNO) composite films were designed. The OAO composite film exhibited the best overall performance, with an average transmittance of 92.27 %, a dielectric constant of 84, a dielectric loss of 0.00672, and a leakage current density of approximately 1.4 × 10−8 (5 V) when the thickness of the BMNO layer was 15 nm. These results highlight the significant potential of BMN as a transparent flexible high-k dielectric material.

Atomic layer deposition of magnetic thin films: Basic processes, engineering efforts, and road forward

Atomic layer deposition (ALD) is known as a key enabler of the continuous advances in device engineering for microelectronics. For instance, the state-of-the-art transistor technology depends entirely on ALD-grown high-κ materials. Another application branch where ALD could potentially play a similar important role in future is the magnetic thin film devices. Spin-based devices based on high-quality magnetic thin films are anticipated to provide high-efficiency operations with low power consumption. The strict quality demands the magnetic thin films must fulfill in the next-generation applications form the strong bases for the efforts to implement ALD in this application area. In this first comprehensive review on the topic, our aim is to provide an insightful account of the ALD processes so far developed for magnetic materials and to highlight the application-relevant magnetic properties of the thus fabricated thin films. Moreover, we discuss the various innovative engineering efforts made toward different multi-layered and nanostructured composite materials and complex architectures uniquely enabled by the sophisticated self-terminated film-growth mechanism of ALD. The review is finished with a brief outlook toward the future prospects and challenges in the field.

Performance evaluation of split high–K material based stacked hetero-dielectrics tunnel FET

This research investigates the performance evaluation of a double gate TFET (DGTFET) by employing a hetero-dielectric gate structure featuring distinct high-K dielectrics with different work functions in a dual-material gate configuration. The gate dielectric stack is comprised of split high–K materials placed on the SiO2 dielectric. An outline of the analytical model for the validation of the novel device is developed and 2D simulations-based analysis and investigation are carried out. The impact of different high-K dielectric materials layered on top of silicon dioxide (SiO2) is examined; its effect on transfer characteristics, subthreshold swing (SS), minimum tunneling width, ratio of ON to OFF currents ION/IOFF, and energy band bending are investigated. The work functions optimization for the auxiliary and tunnel gates are made in this work to minimize OFF current, to reduce ambipolar phenomena and to enhance tunnel rate. The effects of gate potentials, source/ drain doping concentrations on the results are further studied. The threshold voltage of DGTFET is also modelled and computed for the proposed structures. The present findings revealed that the low OFF current (10−17 A μm−1) is provided by the proposed device structure, improved ratio of ION/IOFF (1011), and lowered subthreshold swing required for future era.

Enhanced charge trapping characteristics through composite high-k material phase separation

Charge trapping memory with the P-Si/Al2O3/LaTiO/Al2O3/Pt structure was fabricated by a pulsed laser deposition system. An innovative high-k nanocrystal-amorphous phase structure could be stably formed in the charge trapping layer. The La2O3 nanocrystals are embedded in amorphous TiO2. Numerous charge traps are generated at the phase interface, which could significantly increase the charge trapping capability. A larger memory window of 16.56 V at ±12 V sweep voltage is observed, comparing with a lower value of 5.52 V for the simple amorphous structure. The device also demonstrated excellent stability, with only a 13% charge loss rate after 10 years and an unchanged memory window after 105 program/erase cycles. It is attributed to the structure that the amorphous phase isolates the trapped electrons around the nanocrystal and, thus, is resistant to loss. This work could provide an approach to generating charge traps by phase separation of high-k materials for future nonvolatile memory applications.

Gate Stack Analysis of Nanosheet FET for Analog and Digital Circuit Applications

This manuscript demonstrates the performance comparison of vertically stacked nanosheet FET with various high-k materials in gate stack (GS) configuration. As the high-k dielectric materials are inevitable to continual scaling, in this paper, various high-k dielectric materials such as Si3N4, Al2O3 and HfO2 are incorporated in the GS, and the performance is studied. Further, DC and Analog/RF performance metrics are discussed in detail, and it is noticed that by using HfO2 in high-k GS, the on current (I ON) is enhanced by 46.7% and off current (I OFF) is decreased by 81.6% as compared to conventional NSFET (C-NSFET) without high-k GS. Also, the switching ratio (I ON/I OFF) is increased by 8× from SiO2 to HfO2, ensuring good logic applications. Moreover, compared to the C-NSFET, GS-NSFET with HfO2 offers better values for analog metrics like transconductance (gm) and transconductance generation factor (TGF). However, as the k value increases, the capacitances are also observed to be increased. As a result, the intrinsic delay (τ) increases by 9%, 6% and 20% from SiO2 to Si3N4, Si3N4 to Al2O3, Al2O3 to HfO2, respectively. On top of that, the circuit level demonstration is also performed for resistive load based inverter and ring oscillator (RO) for both C-NSFET GS NSFET with HfO2 as GS material. From circuit analysis, it is observed that by using the GS, the performance of the inverter is increased in terms of noise margins and DC gain. However, the oscillation frequency (f OSC) of 3-stage RO is decreased by 14.7% with the incorporation of GS owing to the increment in gate capacitance (Cgg). Consequently, the results will give deep insights into the performance analysis of NSFET with various high-k materials in gate stack at both device and circuit levels.

An experimental comparison of interface trap density in hafnium oxide-based FeFETs

In recent years, there has been significant progress in the development of high-κ materials in the semiconductor industry. Given that the contact between the channel and the electrode has a crucial impact on reliability, the selection of electrode materials and their deposition technology is an area that requires extensive research. Additionally, interface trap density has long played a critical role in determining the reliability of field-effect transistors (FETs). Therefore, this paper presents the results of interface trap density in high-κ FETs obtained using 2-level and 3-level charge pumping methods. Measurements were conducted on a 10 nm oxide thickness n-doped silicon substrate using native k materials such as silicon and zirconium-doped hafnium oxide. The results demonstrate that chlorine-based HfO2 oxide with zirconium doping exhibits the lowest interface defects.

Solving the issue of increasing forming voltage during device miniaturization in hafnium oxide-based resistive access memory using high-k sidewall material

An electrothermal coupling model of resistive random access memory (RRAM) was established based on the oxygen vacancy conduction mechanism. By resolving the partial differential equation for the coefficients, the variation process of the device resistance was simulated. In our studies, a device model was proposed which can accurately simulate the whole process of RRAM forming, reset, and set. Based on the established model, a new high dielectric constant (high-k) material (La2O3) is introduced as the sidewall material. The La2O3 sidewall material can concentrate the electric field and helps to speed up the formation of conductive filaments. The La2O3 sidewall can effectively reduce the forming voltage increase during the miniaturization process. Then, the influence of sidewall thermal conductivity on forming voltage is studied, and it is discovered that low thermal conductivity helps to reduce the model’s forming voltage and increase the temperature concentration. These findings serve as a foundation for more studies on the choice of sidewall materials.

Engineering DyCrO3 ceramics toward room-temperature high-κ dielectric applications

The search for a high-κ dielectric material that combines a high dielectric constant (ϵ′) and low dielectric loss is very crucial because of its widespread use in gate dielectrics to avoid the leakage current that arises due to continued miniaturization of present SiO2-based metal-oxide semiconductor field-effect transistor devices. RCrO3 (R is a rare-earth ion) materials have been at the center of interest because of their intriguing ferroelectric and magnetic properties, as well as their room-temperature colossal dielectric constant (CDC) values. Although CDC (ϵ′∼104) in RCrO3 materials is quite common, it is unsuitable for device applications since it is associated with a larger dielectric loss value (tan δ∼7 at 11 kHz). Here we have focused on polycrystalline DyCrO3, prepared using multiple synthesis techniques, and thoroughly investigated the origin and tuning of the various dielectric relaxations that give rise to CDC and large dielectric loss values. A clear understanding of the origin of dielectric relaxations enables us to design a specially synthesized DyCrO3 (SPS-DCO) in which the extrinsic dielectric relaxations driven large dielectric loss values can be completely suppressed and which is found to be associated with optimized high-κ dielectric properties [ϵ′∼130, tan δ∼0.06, and temperature coefficient of dielectric constant (TCϵ) ∼ 2280 ppm/K at 11 kHz, 300 K]. The only remaining intrinsic Debye-type dielectric relaxation in SPS-DCO arises due to electric-field-assisted charge hopping among various valences of Cr (investigated using x-ray photoelectron spectroscopy) that presently limits the lowest attainable loss value.

Correlation of interfacial and dielectric characteristics in atomic layer deposited Al2O3/TiO2 nanolaminates grown with different precursor purge times

Considering the potential applications of Al2O3/TiO2 nanolaminates (ATA NLs) in storage capacitors, device-grade ATA NLs are fabricated using an ALD system, wherein the effect of precursor purging time on interfacial, and dielectric properties is thoroughly investigated. With an increase in half-cycle purging time from 2 to 4 s, the observed improvement in interface quality and sublayer density of these NLs is ascribed to the efficient removal of reaction by-products and impurities. Moreover, with an increase in purge time from 2 to 4 s, the increase in dielectric constant and concurrent decrease in dielectric loss from ∼132 to 154 and from ∼0.29 to 0.2, respectively, are primarily assigned to the improvement in sublayer conductivity contrast assisted Maxwell–Wagner interfacial polarization across Al2O3/TiO2 interfaces. The NL based devices fabricated at 4 s purging time, exhibited a capacitance density of ∼18.94 fF/μm2, low equivalent oxide thickness of ∼1.82 nm, and reduced leakage current density of ∼3.04 × 10−5 A/cm2 at 2 V applied bias, which demonstrates its suitability as high-k materials for energy storage applications. Furthermore, this study not only gives an insight of the purging time induced growth chemistry of ATA NLs but also explores the possibility of improving its dielectric performance essential for multifaceted applications.

(Invited) A Novel Computational Framework for Simulations of Bio-Field Effect Transistors

In this paper, we present the simulation results of a BioFET using a novel simulation methodology implemented in a computational framework called the Biomolecule-Oxide Simulator (BOxSim). Our novel simulation methodology is based on Gouy-Chapman-Stern and the modified Site-binding models [1][2]. Moreover, our “BOxSim” framework is the computational simulation framework that works on the hierarchical inclusion of interdependent functions to operate multiple models simultaneously. BOxSim is flexible simulation environment which considers the problems of reactive sites from oxide surfaces or non-specific bindings along with the noise present in the experimental signal to calibrate and extract the required device output characteristics [3]. It can help in generating the sensor response which can be experimentally calibrated to confirm the surface density of the specific and non-specific binding as a yield of the process while filtering the noise with the help of the developed methodology. BOxSim is designed in a way [shown in the attached block diagram] that can interact with the commercial tool (e.g., Synopsys TCAD) and our inhouse-simulator called Nano-electronic Simulation Software (NESS) to simulate the main device characteristics for designing either Ion-sensitive FET (ISFET) or Chem/Bio-FET based on the application. Industry-standard compact (BSIM) models can also be used to interact with the BOxSim which takes the generated surface potential from the BOxSim simulator and transfers it into a circuit simulator to evaluate various ISFET circuit designs.To show the capabilities of our BOxSim framework, as input we have considered several oxides, amino acids (AA) and short peptides which generate distinct signatures for arch AA or peptide. We have investigated the impact of various high-k dielectric materials [4][5] as the gate oxide on important Figures of Merit (FoM) such as current in the channel of the device, surface potential (Ψ o ), sensitivity and intrinsic buffer capacitance [6]. More importantly, the variation of differential capacitance (CT ) with the second gradient of drain current (d2 I o /dpH2 ) and surface potential (d2 Ψ o /dpH2 ) are used to uniquely identify the signatures of different amino acids or peptides. Fig. 1 shows the characteristics of different oxides with respect to the pH variation. The surface potential of oxides is dependent on the affinity constants and the zero-crossover point represents the zwitterion state. Similarly, we have simulated the detection process of different AA such as Glutamic Acid (E) and Lysine (K) immobilized with carboxyl (C-Imm.) or amine (N-Imm.) terminal [Fig. 2]. The affinity constants, isoelectric point, and density of amino acids can be extracted from the d2Ψo/dpH2 variation with the bulk pH. Other than amino acids, we have shown the distinct features of short a peptide Phenylalanine-Proline (FP) immobilized with carboxyl-terminal and the addition of Glutamic Acid to the sequence [Fig. 3]. The sensor output can be observed as the variation of drain current with the pH for the immobilized peptide sequence on the sensing surface. We have also confirmed the reliability of the designed model by calibrating the simulated results with the experimental data [7] for different physical conditions [Fig. 4]. The proposed method can be helpful in defining an efficient method for label-free protein sequencing.

On the flexoelectric-like effect of Nb-doped SrTiO3 single crystals

The enhanced flexoelectric-like effect in oxide semiconductors has outstanding properties that compare favorably with those of high-K materials, and this finding has stimulated research aimed at enhancing flexoelectricity of such materials. However, the effective flexoelectric coefficient approaches limits under different doping methods, which implies that there are still some fundamental questions that need to be addressed. In this context, we revisit the origin of the flexoelectric-like effect in oxide semiconductors, which differs significantly from flexoelectricity in dielectrics. The effective flexoelectric coefficient of Nb-doped SrTiO3 single crystals increases with a larger doping concentration of Nb and is linearly proportional to the reciprocal of the depletion layer width, which is consistent with the theoretical model. More interestingly, due to the doping with Nb, the sign of the flexoelectric-like effect is reversed, which emphasizes the distinction from intrinsic flexoelectricity. Despite the contribution of electrons, frequency-scan measurements indicate that the presence of oxygen vacancies has a crucial impact on flexoelectricity at low frequencies. These results provide insights into semiconductor flexoelectricity and provide a strategy for enhancing the flexoelectric-like effect by optimizing the depletion layer.

A simple figure of merit to identify the first layer to degrade and fail in dual layer SiOx/HfO2 gate dielectric stacks

Understanding the degradation dynamics and the breakdown sequence of a bilayer high-k (HK) gate dielectric stack is crucial for the improvement of device reliability. We present a new Figure of Merit (FoM), the IL/HK Degradation Index, that depends on fundamental materials properties (the dielectric breakdown strength and the dielectric constant) and can be used to easily and quickly identify the first layer to degrade and fail in a bilayer SiO2/HK dielectric stack. Its dependence on IL and HK material parameters is investigated and its validity is demonstrated by means of accurate physics-based simulations of the degradation process. The proposed FoM can be easily used to understand the degradation dynamics of the gate dielectric stack, providing critical insights for device reliability improvement.

Scalable integration of hybrid high-κ dielectric materials on two-dimensional semiconductors.

Two-dimensional (2D) semiconductors are promising channel materials for next-generation field-effect transistors (FETs). However, it remains challenging to integrate ultrathin and uniform high-κ dielectrics on 2D semiconductors to fabricate FETs with large gate capacitance. We report a versatile two-step approach to integrating high-quality dielectric film with sub-1 nm equivalent oxide thickness (EOT) on 2D semiconductors. Inorganic molecular crystal Sb2O3 is homogeneously deposited on 2D semiconductors as a buffer layer, which forms a high-quality oxide-to-semiconductor interface and offers a highly hydrophilic surface, enabling the integration of high-κ dielectrics via atomic layer deposition. Using this approach, we can fabricate monolayer molybdenum disulfide-based FETs with the thinnest EOT (0.67 nm). The transistors exhibit an on/off ratio of over 106 using an ultra-low operating voltage of 0.4 V, achieving unprecedently high gating efficiency. Our results may pave the way for the application of 2D materials in low-power ultrascaling electronics.

Overcoming sub-threshold slope degradation in sub 10 nm technologies

Sub-threshold slope degradation is one of the difficulties preventing microchip scaling. This paper mainly concentrates on sub-threshold region of MOSFET and introduces the definition of sub-threshold swing (inverse of sub-threshold slope). The reason for this work is also told. Basing on ideal assumptions, the work considers 8 influence factors of sub-threshold. After comparison, high-k material, lower doping density, higher bias voltage and more ideal surface are good ways to solve the problem. Changing work function is conditional. The result is meaningful for further understanding of sub-threshold region and further scaling-down.

Vertically grown ultrathin Bi2SiO5 as high-κ single-crystalline gate dielectric

Single-crystalline high-κ dielectric materials are desired for the development of future two-dimensional (2D) electronic devices. However, curent 2D gate insulators still face challenges, such as insufficient dielectric constant and difficult to obtain free-standing and transferrable ultrathin films. Here, we demonstrate that ultrathin Bi2SiO5 crystals grown by chemical vapor deposition (CVD) can serve as excellent gate dielectric layers for 2D semiconductors, showing a high dielectric constant (>30) and large band gap (~3.8 eV). Unlike other 2D insulators synthesized via in-plane CVD on substrates, vertically grown Bi2SiO5 can be easily transferred onto other substrates by polymer-free mechanical pressing, which greatly facilitates its ideal van der Waals integration with few-layer MoS2 as high-κ dielectrics and screening layers. The Bi2SiO5 gated MoS2 field-effect transistors exhibit an ignorable hysteresis (~3 mV) and low drain induced barrier lowering (~5 mV/V). Our work suggests vertically grown Bi2SiO5 nanoflakes as promising candidates to improve the performance of 2D electronic devices.

Thermostimulated luminescence analysis of oxygen vacancies in HfO[formula omitted] nanoparticles

Hafnia has already been established in CMOS technologies as a high-k metal gate material, however, recently it has also become a promising material in ferroelectric applications. In this study we have investigated intrinsic defects such as oxygen vacancies in undoped and 5at%Eu HfO2 synthesized by sol-gel, combustion, auto-ignition combustion, hydrothermal and precipitation methods. All samples were of monoclinic phase with crystallite sizes of 16–40 nm. Photoluminescence (PL), thermostimulated luminescence (TSL) both below and above room temperature as well as XRD and TEM methods were used to identify potential VO3+1, VO3+2, VO4+1 and VO4+2 defects. Activation energies were determined for the oxygen vacancies and grain boundary effects were studied. Both PL and TSL wavelength peak spectra shift to higher energies with the increase of temperature was observed.