High-k Gate Dielectrics Research Articles

Device to circuit level implementation of JL-NSFET for DC/analog/RF applications at sub-5nm technology node: design optimization and temperature analysis

Abstract This manuscript introduces, for the first time, a novel approach that incorporates a comprehensive analysis of sheet variations (1–5) and every individual sheet wise temperature variation, and as well as an investigation of various GS high-k gate dielectrics in Junction-less (JL) Nanosheet FET (JL-NSFET). The study starting from device level (Digital/Analog/Radio Frequency) to circuit (CMOS Inverter and ring oscillator) as a whole package is investigated through well calibrated TCAD simulation and the results portrayed. NSFETs are the ultimate choice for integrated circuits (ICs) at sub-5 nm technology node. The notion of this paper is to design and optimization of NSFET with GS high-k gate dielectrics (Al2O3, HfO2, ZrO2 and TiO2) Initially. The switching/analog and RF metric revels that HfO2 is superior in terms SS, switching applications and more compactable with CMOS process. Further, adding number of sheets and temperature variation has been done later. As number of sheets increases, the effective channel width increases, electric field distribution takes place evenly and enhanced gate control owing to improved I O N , I O N / I O F F r a t i o , SS and DIBL. However, increasing the number of vertical channel layers (sheets) more than 2 results into diminished analog/RF performance of JL-NSFET owing to increased parasitic capacitances. Further, the impact of temperature variations (250 K to 450 K) studied for different sheet variations (1 to 5) and noticed that analog/RF such as gm, gds, fT, TFP and GTFP are enhanced by 40.82%, 28.76%, 40.69%, 64.62% and 70.59%, respectively at lower temperature (250 K) when compared to high temperature (450 K). These enhancements make the device is ideal for applications in cryogenic computing systems, satellites, deep space probes, and other aerospace technologies. Furthermore, as the circuit level implementation CMOS inverter and 5-stage ring oscillator (RO) are examined for different sheets and observed as sheets increase delay and EDP increases. For a CMOS inverter the NMH (0.295 V) and NML (0.280 V) are better at 2 sheets with a highest gain of 9.38 V/V. Hence, it is advised to use two or three sheets-based JL-NSFETs for high-performance and lower-power analog/RF applications.

Investigation of the Electrical Characteristics of AlGaN/AlN/GaN Heterostructure MOS-HEMTs with TiO2 High-k Gate Insulator

This paper investigates the impact of TiO2 high-k gate insulator on the electrical characteristics of AlGaN/AlN/GaN MOS-HEMT transistors using MATLAB and Atlas-TCAD simulation software. The physical analytical model of the MOS-HEMTs is used for simulation from Al2O3, HfO2, and TiO2 as the gate dielectric materials, which provide higher performance and reliability of the MOS-HEMT devices. The device shows a good improvement in its result of the DC and AC characteristics with different permittivity of insulator materials. Thus, the DC and AC performance of GaN MOS-HEMTs is higher than with other insulators, such as Al2O3 and HfO2 by using TiO2 as the gate dielectric. Moreover, the simulation results proved that TiO2 is the better gate dielectric material to enhance the electrical reliability of the power switching devices for high-temperature applications such as electric automobiles.

Liquid Metal Oxide-Assisted Integration of High-k Dielectrics and Metal Contacts for Two-Dimensional Electronics.

Two-dimensional van der Waals semiconductors are promising for future nanoelectronics. However, integrating high-k gate dielectrics for device applications is challenging as the inert van der Waals material surfaces hinder uniform dielectric growth. Here, we report a liquid metal oxide-assisted approach to integrate ultrathin, high-k HfO2 dielectric on 2D semiconductors with atomically smooth interfaces. Using this approach, we fabricated 2D WS2 top-gated transistors with subthreshold swings down to 74.5 mV/dec, gate leakage current density below 10-6 A/cm2, and negligible hysteresis. We further demonstrate a one-step van der Waals integration of contacts and dielectrics on graphene. This can offer a scalable approach toward integrating entire prefabricated device stack arrays with 2D materials. Our work provides a scalable solution to address the crucial dielectric engineering challenge for 2D semiconductor-based electronics.

Enhanced electrical performance in graphene field-effect transistors through post-annealing of high-k HfLaO gate dielectrics

High-k gate dielectrics have attracted a great deal of attention in the investigation of transistors due to their unique properties such as superior gate controllability. However, their integration into graphene field-effect transistors (GFETs) remains problematic and the physical mechanisms governing the performance of these devices are still not fully understood. In this study, the effects of post-annealing on GFETs utilizing the high-k HfLaO ternary oxide as the gate dielectric were comprehensively investigated. The HfLaO film was deposited on top of graphene by magnetron sputtering, and the device performance with various post-annealing temperatures was conducted. It was found that post-annealing temperature can effectively increase the dielectric constant through balancing the oxygen-vacancy defects and moisture absorption. Both the surface morphology of HfLaO and performance of GFETs were investigated, and the fabricated GFETs exhibit notable electrical performance enhancements. Specifically, GFETs with a 200 °C post-annealed HfLaO gate dielectric demonstrate the optimal device performance, featuring a minimal Dirac point voltage (VDirac) of 1.1 V and a minimal hysteresis (ΔVDirac) of 0.5 V. The extracted hole and electron mobilities are 4012 and 1366 cm2/V · s, respectively, nearly one order of magnitude higher than that of GFETs with as-deposited HfLaO. This work outperforms other existing GFETs utilizing high-k gate dielectric and chemical vapor deposition grown graphene in terms of both carrier mobility and on–off ratio. It is also noted that the excessive post-annealing temperature can negatively impact the GFET performance through introducing oxygen vacancies, increasing the surface roughness, lowering the breakdown voltage, and inducing recrystallization.

Impact of Gate-Electrode Material on Channel-Carrier Mobility of Thin-Film Transistor With High-k Gate Dielectric

Impact of Gate-Electrode Material on Channel-Carrier Mobility of Thin-Film Transistor With High-k Gate Dielectric

Statistical Scaling in Localization-Induced Failures

Abstract The investigation of statistical scaling in localization-induced failures dates back to da Vinci's speculation on the length effect on rope strength in 1500 s. The early mathematical description of statistical scaling emerged with the birth of the extreme value statistics. The most commonly known mathematical model for statistical scaling is the Weibull size effect, which is a direct consequence of the infinite weakest-link model. However, abundant experimental observations on various localization-induced failures have shown that the Weibull size effect is inadequate. Over the last two decades, two mathematical models were developed to describe the statistical size effect in localization-induced failures. One is the finite weakest-link model, in which the random structural resistance is expressed as the minimum of a set of independent discrete random variables. The other is the level excursion model, a continuum description of the finite weakest-link model, in which the structural failure probability is calculated as the probability of the upcrossing of a random field over a barrier. This paper reviews the mathematical formulation of these two models and their applications to various engineering problems including the strength distributions of quasi-brittle structures, failure statistics of micro-electromechanical systems (MEMS) devices, breakdown statistics of high– k gate dielectrics, and probability distribution of buckling pressure of spherical shells containing random geometric imperfections. In addition, the implications of statistical scaling for the stochastic finite element simulations and the reliability-based structural design are discussed. In particular, the recent development of the size-dependent safety factors is reviewed.

Solution-processable low-voltage carbon nanotube field-effect transistors with high-k relaxor ferroelectric polymer gate insulator

Achieving energy-efficient and high-performance field-effect transistors (FETs) is one of the most important goals for future electronic devices. This paper reports semiconducting single-walled carbon nanotube FETs (s-SWNT-FETs) with an optimized high-k relaxor ferroelectric insulator P(VDF-TrFE-CFE) thickness for low-voltage operation. The s-SWNT-FETs with an optimized thickness (∼800 nm) of the high-k insulator exhibited the highest average mobility of 14.4 cm2 V−1s−1 at the drain voltage (I D) of 1 V, with a high current on/off ratio (I on/off >105). The optimized device performance resulted from the suppressed gate leakage current (I G) and a sufficiently large capacitance (>50 nF cm−2) of the insulating layer. Despite the extremely high capacitance (>100 nF cm−2) of the insulating layer, an insufficient thickness (<450 nm) induces a high I G, leading to reduced I D and mobility of s-SWNT-FETs. Conversely, an overly thick insulator (>1200 nm) cannot introduce sufficient capacitance, resulting in limited device performance. The large capacitance and sufficient breakdown voltage of the insulating layer with an appropriate thickness significantly improved p-type performance. However, a reduced n-type performance was observed owing to the increased electron trap density caused by fluorine proportional to the insulator thickness. Hence, precise control of the insulator thickness is crucial for achieving low-voltage operation with enhanced s-SWNT-FET performance.

Quantum transport in WSe2/SnSe2 tunneling field effect transistors with high-k gate dielectrics

Combining two-dimensional materials and high-k gate dielectrics offers a promising way to enhance the device performance of tunneling field-effect transistor (TFET). In this work, the device performance of WSe2/SnSe2 TFET with various gate dielectric materials is investigated based on quantum transport simulation. Results show that TFETs with high-k gate dielectric materials exhibit improved on-off ratio and enhanced transconductance. The optimized WSe2/SnSe2 TFET with TiO2 gate dielectrics achieves an on-state current of 1560 μA/μm and a subthreshold swing (SS) of 48 mV/dec. The utilization of high-k gate dielectric materials results in shorter tunneling length, higher transmission efficiency, and increased electron tunneling probability. The performance of the WSe2/SnSe2 TFET would be affected by the presence of the underlap region. Moreover, WSe2/SnSe2 TFETs with La2O3 dielectric can be scaled down to 3 nm while meeting high-performance (HP) device requirements according to the International Technology Roadmap for Semiconductors (ITRS). This research presents a practical solution for designing advanced logic devices in the sub-5 nm technology node.

The lattice thermal conductivity of hafnia: The influence of high-order scatterings and phonon coherence

Hafnia (HfO2) is a potential candidate for the high-k gate dielectrics in next-generation high-power electronics. Its thermal transport properties, which determine the performance of these related high-power electronics, are critical while rarely investigated. Here, the thermal transport properties of HfO2 in a wide temperature range of 300–2000 K with a phase transition between monoclinic and tetragonal phases at ∼1765 K, are systematically studied based on the temperature-dependent effective potential landscapes with both propagating and coherence thermal transport considered. It is found that the cage-like structure of monoclinic HfO2 results in the avoid crossing in the phonon band structures, which increases the three-phonon scattering largely. Some phonon modes with significant scattering matrix can have relatively larger 3ph and 4ph scattering rates in tetragonal HfO2. Consequently, the thermal conductivity of HfO2 is only 11.95–1.72 W/mK at 300–2000 K. Our results further show that propagating phonon channels dominate the thermal transport in HfO2 and contribute at least 70% to the total thermal conductivity. The rest of the thermal conductivity of HfO2 results from the coherence thermal transport channels, which is caused by the overlap of phonons. Four-phonon scatterings are found to be significant for the thermal transport in tetragonal HfO2, which can result in a thermal conductivity reduction of ∼50%. Our results here advance the understanding of the thermal transport in HfO2, which may benefit the performance optimization of HfO2-related electronics.

Heterogeneous integration of high-k complex-oxide gate dielectrics on wide band-gap high-electron-mobility transistors

Heterogeneous integration of dissimilar crystalline materials has recently attracted considerable attention due to its potential for high-performance multifunctional electronic and photonic devices. The conventional method for fabricating heterostructures is by heteroepitaxy, in which epitaxy is performed on crystallographically different materials. However, epitaxial limitations in monolithic growth of dissimilar materials prevent implementation of high quality heterostructures, such as complex-oxides on conventional semiconductor platforms (Si, III-V and III-N). In this work, we demonstrate gallium nitride (GaN) high-electron-mobility transistors with crystalline complex-oxide material enabled by heterogeneous integration through epitaxial lift-off and direct stacking. We successfully integrate high-κ complex-oxide SrTiO3 in freestanding membrane form with GaN heterostructure via a simple transfer process as the gate oxide. The fabricated device shows steep subthreshold swing close to the Boltzmann limit, along with negligible hysteresis and low dynamic on-resistance, indicating very low defect density between the SrTiO3 gate oxide and GaN heterostructure. Our results show that heterogeneous integration through direct material stacking is a promising route towards fabricating functional heterostructures not possible by conventional epitaxy.

Low voltage operation of organic thin-film transistor with atmospheric coating of high-k polymer dielectric

We investigated high-k polymers as gate dielectrics to develop an atmospheric-pressure process for organic transistors. A high-k terpolymer, p(VDF-TrFE-CFE), was formed by drop-casting. Self-assembled molecules (SAM) of triptycene derivatives have been utilized as surface modifiers for high-k gate dielectrics to improve the transistor characteristics. High-k terpolymers reduce the operating voltage of organic thin-film transistors (TFTs) by up to 2.5 V to their high capacities. Introducing a SAM onto the gate dielectric surface improved the organic TFTs’ mobility by more than three orders of magnitude. In addition, a terpolymer and a SAM can be formed simultaneously by drop-casting. This atmospheric processing of the gate dielectric is expected to contribute to organic electronics in large-area or mass production, such as roll-to-roll processes.

(Invited) Stacking High Mobility Channels

Beyond 3 nm node, the transistor architecture of stacked channel gate-all-around (GAA) FETs can replace FinFETs for advanced technology node due to the improvement of power, performance, and area by the enhanced short channel control, design flexibility, and drive current per footprint. High ION and small parasitic RC are the keys to extend nanosheet technologies for N+1 and N+2 nodes. To extend nanosheets to next nodes, we have demonstrated additional enabling knobs such as high mobility channels, high-k gate dielectrics, and highly stacked channels to effectively increase the ION for high performance. Beyond stacked nanosheets, new transistor architectures such as TreeFET (a combination of FinFET and stacked nanosheets) and CFET (3D stacked n and p FETs) can further enable cell height scaling. CFETs and atomic channels have potentials to be used in A5 and A2 nodes according to the transistor roadmap by IMEC [1], respectively. Note that ultrathin body as thin as 1 nm can be considered as atomic channels for nearly ideal SS and high ION/IOFF for low power application.First of all, high mobility channel material is the key factor to improve performance CV/I. As a result, Ge/GeSi and GeSn are the target high mobility channels for nFETs and pFETs, respectively. For nFETs, Ge is an attractive option for high mobility channel to boost the ION thanks to its higher electron mobility than Si [2]. For pFETs, strained GeSn has higher hole mobility than Ge to improve the ION for pFETs due to the hole effective mass reduction under compressive strain [3]. For a fixed footprint, the vertically highly stacked GAA channels can provide large ION to achieve high performance and area scaling for advanced technology node.In addition to high mobility channel, the performance of GAAFET can be improved by scaling down gate oxide thickness. However, the gate leakage problem increases with scaling down the gate oxide thickness. As a result, high-k materials were proposed as gate oxide for gate leakage reduction and performance enhancement in GAAFETs. Plasma-enhanced atomic layer deposition (PEALD) HfxZryO2 was reported to achieve high-k value by optimizing the Hf and Zr content [4], respectively. In this work, a high k value of 47 is achieved in Hf0.2Zr0.8O2 alloy. Furthermore, the high-k gate dielectrics is integrated into stacked GAAFETs successfully.However, the challenge of Ge-based channel is the large IOFF due to the small bandgap [5-7]. Ultrathin body device can effectively reduce the IOFF, but the mobility degradation is observed as the channel thickness decreases below 5nm due to surface roughness scattering. Moreover, the high mobility GeSn can afford some mobility loss due to the ultrathin body [8]. Furthermore, the ION can be further improved by channel stacking with the suppression of IOFF by the ultrathin body.For Si nanosheets, the mismatch between hole mobility and electron mobility in nanosheets [9] might lead to potential design challenges of CMOS. As a result, the TreeFET transistor architecture combining with FinFETs and stacked nanosheets is proposed [10] and experimentally demonstrated [11] as a candidate beyond nanosheets. TreeFETs with {100} surfaces can enhance the electron mobility of Si, while {110} sidewalls are beneficial to hole mobility for both Si and Ge. TreeFETs with additional fin interbridges (IB) between nanosheets can increase Weff and enhance ION per footprint for high-performance devices beyond FinFETs and stacked nanosheets.3D transistor stacking can enable further cell height scaling and extend Moore's law scaling. The pFET and nFET are able to fold on each other to reduce 50% of inverter cell area ideally in CFET [12, 13], as a promising transistor architecture beyond stacked nanosheets. As compared to the sequential 3D process, no wafer bonding or layer transfer is required in the monolithic 3D process. Moreover, monolithic 3D by epitaxy can reduce the FEOL cost and the parasitic RC as compared to sequential 3D. The high mobility channel material of GeSi is used for CFET demonstration in this work [14]. Heavily doped sacrificial layers are beneficial for S/D resistance reduction by thermal annealing during the device fabrication. Reportedly, dielectric layers in S/D regions are used for the electrical isolation between n/p FETs in CFET structure [15], but the complicated S/D recess and dual S/D selective epi regrowth are required. In this work, a simple process without S/D selective epi regrowth can achieve self-aligned CFETs with multiple P/N junction isolation to effectively reduce the leakage current. Acknowledgements- This work is supported by National Science and Technology Council (111-2218-E-002-040-MBK, 111-2634-F-A49-008-, and 111-2622-8-002-001-), Ministry of Education (NTU-CC-112L890901), and Taiwan Semiconductor Research Institute (TSRI), Taiwan. Figure 1

(Invited) Characteristics of GaN/High-k Capacitors Under Positive Bias Stress

Vertical GaN-based trench gate metal-oxide-semiconductor field-effect transistors (MOSFETs) have been widely investigated to suppress leakage currents for applications associated with high power and high frequency. Various materials with high dielectric constant (High-k) such as Al2O3, HfO2, AlSiO x , HfSiO x , and HfAlOx have been studied as gate insulator to obtain high gm value of GaN MOSFET [1-6]. The structure of High-k gate insulator and interface between GaN and High-k is well known to affect characteristics of GaN MOS capacitor. An amorphous HfAlOx film could be fabricated by forming (HfO2)/(Al2O3) nanolaminate films via plasma-enhanced atomic layer deposition and post-deposition annealing at 800°C. Al2O3 and HfAlOx gate insulators with an amorphous structure found to exhibit superior fundamental electrical properties including no frequency dispersion, a high breakdown voltage and a low interface state density [3,5,6]. However, reliability characteristics under high voltage sweep and positive bias stress (PBS) conditions are not currently well understood.In this paper, we investigate flatband voltage (Vfb) shift of the Al2O3 and HfAlOx capacitors by varying effective electric field (Eeff) from Vfb under PBS. We also compare Vfb shift behavior among Al2O3, HfAlOx and reported High-k gate insulators.Here, to understand influence of the thermal budget at 800°C on electrical property, two n-GaN/Al2O3(10nm)/Pt MOS capacitors were prepared: One was fabricated by thermal budget at 300°C (AlO). The other was fabricated by the same capacitor fabrication process, with the GaN substrate annealed at 800°C before Al2O3 film deposition (Pre800C-AlO). To examine interface properties of the n-GaN/HfAlOx, n-GaN/interfacial layer (IL)/HfAlOx(10nm)/Pt capacitor with a 0.5nm-thick-Al2O3-IL (AlO/HfAlO) and a 0.5nm-thick-HfO2-IL (HfO/HfAlO) and without IL (HfAlO) were prepared.All High-k gate insulators had an amorphous structure. The k-values of Al2O3 and HfAlOx gate insulators estimated from C-V measurement were 8 and 17.2, respectively [3,6]. All capacitors exhibited the smooth J-Eeff properties due to an amorphous structure regardless of the 800°C pre-annealing of the GaN substrate and IL of HfAlOx case. All capacitors also exhibited no frequency dispersion in the range of 1k-1MHz. However, the Pre800C-AlO capacitor showed a large hump due to the electrical defects in the C-V curve. The Vfb shift behavior of the capacitor was examined by varing Eeff from Vfb of PBS. The Eeff was estimated from the applied voltage divided by capacitanc equivalent thickness. The Eeff from Vfb of Al2O3 and HfAlOx capacitors were varied from 4.1-8.7 and 6.5-15.4MVcm-1, respectively. The stress time was varied from 0 to 300s . The sweep voltage range of C-V measurement for obtaining Vfb in each stress time was always applied smaller than the PBS voltage. The positive Vfb shift was observed in all capacitors after PBS, indicating the presence of some electron trapping sites. The positive Vfb increased siginificantly up to a stress time of 10s, gradually increased up to 200s, and saturated above 200s in all Eeff from Vfb regions. The positive Vfb value of all capacitors reached to around 0.2V when the Eeff from Vfb was applied to 6.5MVcm-1 at 300s. Above 6.5MVcm-1, different Vfb shift profiles were observed for two Al2O3 and three HfAlOx capacitors. The positive Vfb value of the Al2O3 capacitors increased drastically to 0.5V as the Eeff from Vfb increased from 6.5 to 8.7MVcm-1. Furthermore, the Pre800C-AlO capacitor became larger Vfb shift than the AlO capacitor because the Pre800C-AlO capacitor is due to the introduction of some defects on the GaN surface by pre-annealing at 800°C. On the other hand, for the HfAlO, AlO/HfAlO and HfO/HfAlO capacitors, the positive Vfb shift value was suppressed to 0.3V even when the Eeff from Vfb was applied to 15.4 MVcm-1. Furthermore the Vfb shift showed similar behavior regardless of Al2O3- and HfO2-IL. Based on these experimental data, we conclude that the HfAlOx capacitors have a high reliability under PBS condition.This work was supported by the MEXT Program for Creation of Innovative Core Technology for Power Electronics Grant Number JPJ009777. This work was supported in part by JSPS KAKENHI Grant No. JP20H02189.[1] J. T. Asubar et al., J. Appl. Phys. 129, 121102 (2021). [2] Y. Ando et al., Appl. Phys. Lett. 117, 102102 (2020). [3] K. Yuge et al., Semicond. Sci. Technol. 34, 034001 (2019). [4] D. Kikuta et al., Appl. Phys. Express 13, 026504 (2020). [5] T. Nabatame et al., Appl. Phys. Express 12, 011009 (2019). [6] T. Nabatame et al., ECS Trans. 104 113 (2021).

Mixed Oxide High-K Dielectrics - from Gate Dielectrics to Non-Volatile Memories to SSI-LEDs

Metal oxides were first used as the high-k gate dielectrics in thin film transistors (TFTs). In late 1990s, they were applied to MOSFETs to solve the high leakage current problem in the ultra-thin SiO2 gate dielectric. HfO2 was identified as a viable solution for this application due to its relatively large effective k value and low leakage current. However, HfO2 is subject to crystallization at a relative low temperature of about 600ºC. We introduced the doping method, i.e., by adding a third element to the metal oxide, to solve this problem. The crystallization temperature, the effective k value, the interface state density, and the interface layer thickness of the new film were influenced by the concentration of the added element (1). Eventually, we demonstrated that the 12% Zr doped HfO2, i.e., ZrHfO, had a crystallization temperature higher than 900ºC and many good dielectric properties. The ZrHfO thin film can be sputter deposited.In this talk, structures, preparation methods, operation principles, and characteristics of the following devices will be discussed and new developments will be addressed. < 1 nm EOT ZrHfO gate dielectric layers (2),nanocrystals embedded ZrHfO NVMs in which electrons and holes could be stored separately based on the type of nanocrystal material (3), andsolid state incandescent LEDs (SSI-LEDs) which are formed from the thermal excitation of the simultaneous formation of a large number of nano-resistors during the dielectric breakdown process (4,5,6). J.-Y. Tewg, Y. Kuo, and J. Lu, Electrochem. Solid-State Letters, 8(1), G27-G29 (2005).Yan, Y. Kuo, and J. Lu, Electrochem. Solid-State Letts., 10(7), H199-H202 (2007).Zhang and Y. Kuo, ECS Trans., 66(4), 195-202 (2015).Y. Kuo and S. Zhang, ECS J. Solid State Sci. Technol., 8(12), Q223-Q225 (2019).W.-S. Lin and Y. Kuo, ECS J. Solid State Sci. Technol., 10, 126001 (2021).A. Samuel and Y. Kuo, Solid State Electronics, 204, 108651 (2023).

(Invited) Leading-Edge Diamond FET, MEMS, and Photodetector Devices

Diamond is a candidate material for next-generation power electronics, micro-electro mechanical systems (MEMS), and solar-blind deep-ultraviolet (DUV) photodetector devices with excellent thermal stability and radiation hardness, which operate under extreme environment. In order to use an advantage of high-density hole channel of hydrogenated diamond (H-diamond) surface, we have developed the high-k stack gate dielectrics and AlN heterojuction gate for H-diamond FETs, such as HfO2/HfO2, LaAlO3/Al2O3 Ta2O5/Al2O3, and ZrO2/Al2O3, AlN/Al2O3 prepared by a combination of sputter-deposition (SD) and atomic layer deposition (ALD) techniques [1,2]. We also demonstrated the artificial diamond Fin-FETs with high-current level [3] and the nanolaminate insulator gate metal-oxide-gate FETs (MOSFETs) with k value as high as 100 [4], and the new transistor concept named by metal-insulator-metal-semiconductor field-effect transistor (MIMS-FET) to achieve normally-off operation by combining the advantages of MOSFET and metal-semiconductor FET [5]. In addition, we developed the routine ion-implantation process for preparing the diamond cantilever with a resonant frequency quality factor as high as one million [6,7]. We have also developed thermally stable Schottky barrier photodiode (SPD), metal-semiconductor-metal photodetector (MSMPD), and MSM-type SPD (IDF-SPD) with a large photoconductivity gain in DUV wavelength and a large discrimination ratio between DUV/visible light responsivity [8,9]. In this presentation, we will review the comprehensive our work on the diamond FET, MEMS, and photodetector devices. Acknowledgements: This work was in collaboration with J-W. Liu, M. Imura, M-Y. Liao, J. Alvarez in NIMS and A. Ouchiero and E. Obaldia in University of Taxes, Dallas, and partly supported by JSPS KAKENHI Grant Number 20H00313.

Comparison and analysis of gate dielectrics for SiC MOSFET

SiC MOSFET has been widely used for its characteristics of lower on-off resistance, less switching loss, higher working frequency, and high-temperature resistance. With the scale down of Moore's Law, better gate dielectrics should be selected to improve the breakdown voltage and reduce the gate-drain current to ensure a good working mode of MOSFETs. The traditional gate dielectric is SiO2 but their dielectric constant is low and the interface characteristics at the junction of SiO2 and SiC are poor so various emerging materials have been created to replace the traditional SiO2. Emerging gate dielectrics such as high-k gate dielectrics are receiving a lot of attention today, they can increase breakdown voltage and decrease gate-drain current while maintaining oxide thickness. Among many emerging gate dielectrics, Al2O3, HfO2, and HfSiON have been noticed due to their good characteristics and a lot of research on them. This paper will focus on the analysis of the characteristics of these three materials and their applications in MOSFET. Finally, after a detailed analysis of the three materials, they three materials are compared to understand their differences.

Boronization: A General Strategy for Rare Earth Oxides with Enhanced High-κ Gate Dielectric Performance.

Rare earth oxides (REOs) can be used as high-κ gate dielectrics that are at the core of electronic devices. However, a bottleneck remains with regard to obtaining high-performance REO dielectrics due to the serious hygroscopic issue and high defect states. Here, a general boronization strategy is reported to enhance the high-κ REO gate dielectric performance. Complementary characterization reveals that boronization is capable of reducing oxygen vacancies/hydroxyl defects in REOs and suppressing moisture absorption, leading to the improvement of leakage current, breakdown strength (up to 9 MV/cm), and capacitance-frequency stability. Furthermore, oxide transistors based on boronized REO dielectrics demonstrate state-of-the-art device characteristics with a high mobility of 40 cm2/V s, a current on/off ratio of 108, a subthreshold swing of 82 mV/dec, a hysteresis of 0.05 V, and superior bias stress stability.

Review on remote phonon scattering in transistors with metal-oxide-semiconductor structures adopting high-k gate dielectrics

One main obstacle to obtaining high carrier mobility in transistors with metal-oxide-semiconductor (MOS) structures is carrier scattering, which has been systematically investigated. In the past few decades, much attention was preferentially paid to the scatterings arising from the region near the semiconductor/oxide interface because they can affect the carrier transport in the semiconductor channel more directly and effectively, e.g., polaronic effect, Coulomb scattering, surface-roughness scattering, and intrinsic phonon scattering resulted from the thermal vibration of the semiconductor channel. However, scattering originated from hybrid interface plasmon/optical-phonon excitations, so-called remote phonon scattering, has been neglected to some extent, but is especially severe for gate oxides with high dielectric constants due to the easy vibrations of their atoms. On the other hand, plasmons generated from the oscillations of majority carriers in the gate electrode can couple with the remote phonons to suppress the remote phonon scattering, which is called the gate screening effect. However, when the frequency of the gate-electrode plasmon is close/equal to that of the gate-dielectric phonon, the resonance between the gate electrode and the gate dielectric greatly enhances the remote phonon scattering to severely degrade the carrier mobility (so-called gate antiscreening effect). This work intends to give a comprehensive review on the origins, effects, suppression methods, and recent advances of the remote phonon scattering, with a view to achieving high-mobility MOS devices (including those based on two-dimensional semiconductors) with high-k gate dielectrics for future high-speed electronic applications.

Enhanced physical and electrical properties of HfO2 deposited by atomic layer deposition using a novel precursor with improved thermal stability

With the increased application range of Hf-based oxides in memory devices, such as high-k capacitors, gate dielectrics, and ferroelectric devices, improvement in the properties of HfO2 thin films have been received considerable attention. To achieve improved properties HfO2 thin films deposited by atomic layer deposition (ALD), one strategic way is to develop a process incorporating a new precursor with improved thermal stability. In this paper, HfO2 thin films were deposited by ALD process using a novel precursor modified with a cyclopentadienyl-based ligand to improve thermal stability, and the improved properties were investigated. The ALD process window has been extended to higher temperatures. In addition, with increases in deposition temperature, the impurity concentration, surface roughness, density, and crystallinity of HfO2 were improved. Finally, the HfO2 thin film deposited at a high temperature significantly reduced the leakage current (from 5.2 × 10−7 A/cm2 to 3.1 × 10−9 A/cm2 measured at 0.7 V) without a significant change in dielectric constant, and the remanent polarization characters were also observed. Therefore, we suggest that HfO2 deposited using the proposed hafnium precursor can be applied as a key high-k component in next-generation memory devices and ferroelectric-based semiconductor devices.

Trapping effects on charge transport in graphene field-effect transistors with high-K gate dielectrics

This paper investigates near-interfacial charge trapping effects in graphene field-effect transistors with high-K gate dielectrics. Experimental and model-based analysis elucidates the impact of trapped charge on the transport properties of graphene. Landauer formalism is applied to correlate trapping-enhanced charged impurity scattering to degradation in conductivity and mobility. The analysis shows a significant reduction in conductivity and mobility with a transition toward the dominance of charge impurity scattering as evidenced by their dependence on the sheet carrier density. Moreover, we quantify the impact of trapped charge buildup on the carrier backscattering mean free path associated with charged impurities. This work provides new insights into the impact of charge trapping toward the development of logic, memory, and neuromorphic devices based on graphene and other low-dimensional materials and ultrascaled high-K dielectrics.