High-k Gate Dielectrics Research Articles

Ultralow-Power Synaptic Transistor Based on Wafer-Scale MoS2 Thin Film for Neuromorphic Application

In the next-generation computing framework, synaptic devices modulated using analogue weight storage are expected with capability of performing neuromorphic computing tasks. Recently, 2D transition metal dichalcogenides (TMDCs) based solid-state devices have demonstrated excellent electrical performance showing great potential in nanoscale synaptic electronics. In this letter, artificial synaptic transistors are proposed and fabricated on the atomic layer deposited 2D MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> thin film with an integrated high-k dielectric gate stack. The synapse cells can simulate fundamental synaptic functions similar to those of biological synapses, such as long-term potentiation and depression. Moreover, the ultralow power consumption shows that the proposed synapse is more efficient than most three-terminal synaptic transistors. We also emulate a multi-synapse network to demonstrate intrinsic heterogeneity in biological brain. The experimental results have validated the feasibility of synaptic devices based on 2D TMDCs and have contributed a promising approach to the development of the next-generation brain-like neuromorphic systems.

An Insight into the DC and Analog/RF Response of a Junctionless Vertical Super-Thin Body FET towards High-K Gate Dielectrics

An Insight into the DC and Analog/RF Response of a Junctionless Vertical Super-Thin Body FET towards High-K Gate Dielectrics

Effect of Gd3+ Doping on Sol-Gel Prepared Y₂O₃ Films as Gate Insulators for Oxide Thin Film Transistors.

The relationships between the microstructure and the dielectric properties of sol-gel prepared Y₂O₃ films with various Gd3+ doping were systematically investigated. Robust solution processed lanthanide films, (Y1-xGdx)₂O₃ (0 < x ≤ 0.5), are demonstrated as high-k gate insulators for low voltage-driven oxide thin film transistors and their optimized composition is presented. With the proper amount of Gd3+ doping, the corresponding thin film insulators exhibit low leakage current with increased dielectric constant. The resultant Zn-Sn-O/(Y, Gd)₂O₃ TFT exhibits enhanced performance, by a factor of 10.7 compared with TFTs using a SiO2 insulator, with a field-effect mobility of ~3.15 cm²V-1s-1 and an exceptionally low operating voltage <15 V.

Re-examination of effects of ALD high-k materials on defect reduction in SiGe metal–oxide–semiconductor interfaces

We study the impact of the atomic layer deposition high-k gate insulators on metal–oxide–semiconductor (MOS) interface properties of Si0.78Ge0.22 gate stacks with TiN gate electrodes and the physical origins of the reduction in MOS interface defects. The SiGe MOS interface properties of TiN/Y2O3, Al2O3, HfO2, and ZrO2 gate stacks are compared over a wide range of annealing temperatures. It is found that the lowest interface trap density (Dit) is obtained by TiN/Y2O3 stacks with post-metallization annealing (PMA) at 450 °C among the gate stacks with other gate insulators. Moreover, it is revealed that less amount of GeOx in the interfacial layer leads to lower Dit and that the Y2O3 stacks yield further reduction in Dit during PMA at 450 °C. These results can be explained by the reduction in distorted Ge–O bond densities in GeOx in ILs by scavenging and annealing effects during PMA and the suppression of Ge dangling bond generation by incorporating Y atoms into GeOx during PMA at 450 °C.

Enhanced screening on remote phonon scattering in InGaZnO thin-film transistor by using Ge gate electrode

Room-temperature-processed amorphous InGaZnO thin-film transistors (TFTs) with three different semiconductors (Si, GaAs, and Ge) of various doping concentrations as gate electrodes are fabricated. Like the conventional Si gate devices, both their GaAs and Ge counterparts show carrier mobility increasing with increasing gate doping concentration, further supporting that the holes at/near the surface of a p-type gate electrode can have a screening effect on the remote phonon scattering caused by the surface phonons of their high-k gate dielectrics. Moreover, for the same gate doping concentration, the Ge gate device has a carrier mobility about three times that of its conventional Si gate counterpart. This implies that lower-mass charge carriers in the gate electrode could have a stronger screening effect on remote phonon scattering. As a result, even with a moderate gate doping concentration of 1.0 × 1018 cm−3, the room-temperature-processed Ge gate device shows a high carrier mobility of 60.8 cm2/V s. The enhanced screening effect of the Ge gate electrode should be due to its higher-energy plasmons, which could couple more strongly with the phonons of the gate dielectric to result in weaker gate-dielectric vibration.

Plasmon-phonon resonance at gate-electrode/gate-dielectric interface on carrier mobility of organic TFTs with high-k gate dielectrics

The resonance between the plasmons in gate electrode and the phonons in gate oxide of the omnipresent metal–oxidesemiconductor devices predicted in 2004 is experimentally demonstrated to degrade the mobility of the carriers in the semiconductor channel. By using bottom-gated pentacene organic thin-film transistors fabricated on n-type Si substrates with different resistivities, this work experimentally shows that even for thick HfLaO gate dielectric (~50 nm), the interaction between the gate plasmons and the dielectric phonons can significantly affect the carrier mobility. FTIR and Raman spectra reflect that the phonon frequency of the dielectric ranges from 13.2 to 24.9 THz, overlapping the gate-plasmon frequency (13.2 ~ 18.7 THz) of the 0.01 ~ 0.015 Ω·cm substrate. Therefore, the predicted mobility reduction can be explained by a simpler concept of “resonance”: when the oscillations of gate carrier and dielectric atom have about the same frequency, the remote phonon scattering of the gate dielectric on the channel carriers is greatly enhanced to reduce their mobility. In summary, this resonance-induced mobility reduction could pose a temperature-related reliability problem to electronic circuits when carrier freeze-out at low working temperature reduces the carrier density in the gate electrode to about 3 × 1018 cm−3 to result in a plasmon frequency close to the phonon frequency of the gate dielectric.

Impact of the channel length on molybdenum disulfide field effect transistors with hafnia-based high-k dielectric gate

Field effect transistors (FETs) using two-dimensional molybdenum disulfide (MoS2) as the channel material has been considered one of the most potential candidates for future complementary metal-oxide-semiconductor technology with low power consumption. However, the understanding of the correlation between the device performance and material properties, particularly for devices with scaling-down channel lengths, is still insufficient. We report in this paper back-gate FETs with chemical-vapor-deposition grown and transferred MoS2 and Zr doped HfO2 ((Hf,Zr)O2, HZO) high-k dielectric gates with channel lengths ranging from 10 to 30 µm with a step of 5 µm. It has been demonstrated that channels with the length to width ratio of 0.2 lead to the most superior performance of the FETs. The MoS2/HZO hybrid FETs show a stable threshold voltage of ∼1.5 V, current on/off ratio of &amp;gt;104, and field effect mobility in excess of 0.38 cm2 V−1 s−1. The impact of the channel lengths on FET performance is analyzed and discussed in depth. A hysteresis loop has been observed in the Ids − Vgs characteristics of the hybrid FETs, which has been further studied and attributed to the charge effect at the interfaces. The HZO films show a relatively weak ferroelectric orthorhombic phase and thus serve mainly as the high-k dielectric gate. Charge trapping in the HZO layer that might induce hysteresis has been discussed. Our results show that MoS2/HZO hybrid FETs possess great potential in future low power and high-speed integrated circuits, and future work will focus on further improvement of the transistor performances using ferroelectric HZO films and the study of devices with even shorter MoS2 channels.

Implementation of oxide vertical channel TFTs with sub-150 nm channel length using atomic-layer deposited IGZO active and HfO2 gate insulator

We fabricated vertical channel thin film transistors (VTFTs) with a channel length of 130 nm using an ALD In–Ga–Zn–O (IGZO) active channel and high-k HfO2 gate insulator layers. Solution-processed SiO2 thin film, which exhibited an etch selectivity as high as 4.2 to drain electrode of indium-tin oxide, was introduced as a spacer material. For the formation of near-vertical sidewalls of the spacer patterns, the drain and spacer were successively patterned by means of two-step plasma etching technique using Ar/Cl2 and Ar/CF4 etch gas species, respectively. The SiO2 spacer showed smooth surface morphology (R q = 0.45 nm) and low leakage current component of 10–6 A cm−2 at 1 MV cm−1, which were suggested to be appropriate for working as spacer and back-channel. The fabricated VTFT showed sound transfer characteristics and negligible shifts in threshold voltage against the bias stresses of +5 and −5 V for 104 s, even though there was abnormal increase in off-currents under the positive-bias stress due to the interactions between hydrogen-related defects and carriers. Despite the technical limitations of patterning process, our fabricated prototype IGZO VTFTs showed good operation stability even with an ultra-short channel length of 130 nm, demonstrating the potential of ALD IGZO thin film as an alternative channel for highly-scaled electronic devices.

Analog/RF and Power Performance Analysis of an Underlap DG AlGaN/GaN Based High-K Dielectric MOS-HEMT

This paper exemplifies an exhaustive, figurative and subjective study on the RF performance and DC characteristics analysis of an Underlapped Double-Gate (U-DG) AlGaN/GaN heterojunction-based MOS-HEMT device with Hafnium-based high-k dielectric gate material. This paper depicts the effect of gate length variations on the drain current (ID), the transconductance (gm), the transconductance generation factor (gm/ID) and the RF FOMs intrinsic capacitances (CGD, CGS and CGG), intrinsic resistances (RGD and RGS), cut-off frequency (fT) and maximum oscillation frequency (fMAX). This study reveals shortening of channel length leading to better gate controllability hence an overall superior analog and RF performance is achieved. The U-DG AlGaN/GaN based MOS-HEMT device of 100 nm channel length shows a better Power Output Efficiency (POE) of 33% in contrast to 31% and 23% for the 200 nm and 300 nm devices respectively.

A physical model of cylindrical surrounding double-gate metal-oxide-semiconductor field-effect transistor

&lt;sec&gt;The cylindrical surrounding double-gate metal-oxide-semiconductor field-effect transistor (CSDG MOSFET) is formed by adding an internal control gate to the cylindrical surrounding-gate (CSG) MOSFET. The inner gate of CSDG MOSFET acts as a second gate for enhanced charge control. At present, the research of CSDG MOSFET structure is widely concerned. Compared with double-gate MOSFET, triple-gate MOSFET and CSG MOSFET, the CSDG MOSFET provides good controllability of the gate over the channel. Additionally, the device allows for higher volume inversion than CSG MOSFET, which leads to better output characteristics.&lt;/sec&gt;&lt;sec&gt;In order to study the electrical characteristics of CSDG MOSFET, the potential model of CSDG MOSFET is obtained by solving the two-dimensional Poisson equation in cylindrical coordinates. The effects of gate dielectric, channel length and gate dielectric thickness on the surface potential and electric field of CSDG MOSFET are studied. Besides, the drain-source current model of CSDG MOSFET is established by integrating the inverse charge along the channel. The effects of gate dielectric and gate dielectric thickness on the transconductance of CSDG MOSFET are studied. In addition, the effects of the downscaling of device parameters on the transfer characteristics and transconductance of CSDG MOSFET are studied.&lt;/sec&gt;&lt;sec&gt;The electrical characteristics of CSDG MOSFET are analyzed and discussed. The results show that the minimum surface potential along the channel of CSDG MOSFET decreases with the increase of gate dielectric constant of gate dielectric layer. The electric field along the channel and along the radius, drain-source current and transconductance of CSDG MOSFET increase as the gate dielectric constant increases. The threshold voltage of CSDG MOSFET decreases as the gate dielectric constant increases. Moreover, with the downscaling of device parameters, the transfer characteristics and transconductance of CSDG MOSFET decrease. The performance of CSDG MOSFET can be significantly improved by using high-k gate dielectrics. &lt;/sec&gt;

Investigation of High-K Gate Dielectrics and Chirality on the Performance of Nanoscale CNTFET

Investigation of High-K Gate Dielectrics and Chirality on the Performance of Nanoscale CNTFET

Optimized Al-doped TiO2 gate insulator for a metal-oxide-semiconductor capacitor on a Ge substrate

Atomic layer deposited TiO2- and Al2O3-based high-k gate insulators (GIs) were examined for the Ge-based metal-oxide-semiconductor field effective transistor (MOSFET) application.

Bias Stress Effects in Low Temperature Amorphous Hf-In-ZnO TFTs Using RF-sputtering HfO2 as High-k Gate Dielectric

In this work we analyze the electrical performance, contact resistance and the effects of positive and negative gatebias stress of Hf-In-ZnO/HfO2 thin film transistors. Devices were fabricated using RF-magnetron sputtering at room temperature and fully patterned, with operation voltage below 6 V. Devices with drain-currents up to 2x10-6 A and threshold voltages of ~2 V were analyzed under negative and positive gate bias stress. Devices under negative gate-bias stress showed a slightly threshold voltage shift due to the transistor channel is depleted of electrons at the channel/dielectric interface. Devices under positive gate-bias stress, showed threshold voltage shifts in the negative direction due to the reversible charge/discharge effect of the electrons in pre-existing high-k HfO2 bulk traps. Positive gate-bias stress does not cause any degeneration, since stressed devices tend to recover after 5 mins.

High-mobility pentacene organic thin-film transistors achieved by reducing remote phonon scattering and surface-roughness scattering

Pentacene organic thin-film transistors (OTFTs) with very high carrier mobility have been achieved on both rigid and flexible substrates by using high-k gate dielectric and metal gate. The high-k gate dielectric with suitable thickness can reduce the surface-roughness scattering, while the metal gate can suppress the remote phonon scattering. As a result, based on NbLaO gate dielectric, OTFTs with high carrier mobility of 10.6 cm2 V−1 s−1 (7.99 cm2 V−1 s−1) with the capacitance per unit area measured at frequency of 1 kHz and small threshold voltage of −0.92 V (−0.74 V) fabricated on Pd-coated Si substrate (Pd-coated vacuum tape) are realized, though they have rougher dielectric surface and smaller pentacene grains than their counterparts fabricated on n-Si substrate. Moreover, with the addition of 13-nm SiO2 interlayer between the NbLaO gate dielectric and metal gate electrode, the carrier mobility decreases by 71% and 65% for the OTFTs on Si and V.T. substrates, respectively, highlighting the importance of the RPS.

Q-Factor Performance of 28 nm-Node High-K Gate Dielectric under DPN Treatment at Different Annealing Temperatures

Q-factor is a reasonable index to investigate the integrity of circuits or devices in terms of their energy or charge storage capabilities. We use this figure of merit to explore the deposition quality of nano-node high-k gate dielectrics by decoupled-plasma nitridation at different temperatures with a fixed nitrogen concentration. This is very important in radio-frequency applications. From the point of view of the Q-factor, the device treated at a higher annealing temperature clearly demonstrates a better Q-factor value. Another interesting observation is the appearance of two troughs in the Q-VGS characteristics, which are strongly related to either the series parasitic capacitance, the tunneling effect, or both.

Design and Analysis of Dual-Metal-Gate Double-Cavity Charge-Plasma-TFET as a Label Free Biosensor

In this paper, the bipolar nature of tunnel field effect transistor (TFET) has been utilized for the first time for the identification of biomolecules. C harge plasma concept has been employed to achieve simpler process of fabrication, lower cost and to overcome random dopant fluctuation. The focus of this work is to utilize both ON and ambipolar state of dual metal gate double cavity charge plasma TFET (DMG-DC-CPTFET) biosensor for sensing the biomolecules. Consideration of cavities at both tunneling junctions, it is possible to sense different kinds of biomolecules simultaneously. Gate workfunction engineering has been employed to improve sensitivity and to minimize the OFF state current of the proposed biosensor. High-k gate dielectric is used to achieve maximum ON current. The variation in electrical characteristics like energy band, surface potential and the electric field resulting from the presence of charged and neutral biomolecules in the cavities has been studied. The proposed model offers maximum sensitivity of $2.88\times 10\,\,^{{11}}$ ( $2.88\times 10^{13}$ %) under ON state and $1.37\times 10^{{7}}$ ( $1.37\times 10^{9}$ %) under ambipolar state.

High-performance Te-doped p-type MoS2 transistor with high-K insulators

Molybdenum disulfide (MoS2) films possess intrinsic n-type conductivity, and thus development of p-type MoS2 films for realizing practical next-generation complementary metal oxide semiconductor devices is extremely challenging. The use of dopants is a well-known conventional approach for engineering intrinsic conductivity with improved device performance. Herein, we demonstrate the n-type conductivity suppressing property of the tellurium (Te)-doped multilayer MoS2, grown by metal-organic chemical vapor deposition. The back-gated as-grown Te-doped multilayer MoS2 field-effect transistor (FET) is observed to exhibit p-type behavior with a maximum mobility of 0.036 cm2/V·s, ON/OFF current ratio of 7.8×103, and a Schottky barrier height of 32 meV. A quantitative Schottky barrier height of a p-type multilayer MoS2-based FET with Au electrode has been obtained by analyzing its low-temperature transport characteristics. Enhanced device performance has been achieved by doping the p-type MoS2 transistors in a back-gate structure and high-K dielectric gate insulators with Te. pFET devices containing Al2O3 dielectric insulators exhibit extremely high performance, including a maximum mobility of ∼182 cm2/V·s, maximum ON/OFF current ratio of ∼105, and a low subthreshold swing of ∼215 mV/dec. These improvements have been attributed to the charge screening effect associated with the high-K dielectrics and a low Schottky barrier height.

Novel modification in evanescent mode analysis to incorporate sub-1 nm equivalent oxide thickness in the subthreshold model of junctionless asymmetric double gate FETs

A novel modification in the evanescent mode analysis is presented in this work to comprehend the implication of a high gate dielectric constant in the subthreshold model of junctionless (JL) asymmetric double gate (DG) FETs. A brief study is presented to highlight the lack of an appropriate device model for the JL FET with a sub-1 nm equivalent oxide thickness. This work elaborates the effect of a high-k gate dielectric on one of the most important parameters of evanescent mode analysis, known as the inverse characteristics length. Thereby, an appropriate modification is incorporated in the widely adopted evanescent mode analysis to develop the subthreshold model compatible with high-k gate-dielectric materials and sub-1 nm gate-oxide thickness. Subsequently, the subthreshold model of DG FET with a high-k gate dielectric is presented. The DG FET assumes gate-oxide asymmetry as well as channel doping asymmetry arising due to the ion-implantation and subsequent annealing. With the help of the developed model, the subthreshold characteristics of the device are studied with the variations in device dimensions, the gate-dielectric constant, the doping profile, etc. The results have been found to be in good agreement when numerically studied in comparison with the outcomes of the Synopsys Sentaurus™ Device simulation tool.

A charge-based capacitance model for double-gate hetero-gate-dielectric tunnel FET

In this paper, a charge-based capacitance model has been proposed for a double-gate (DG) hetero-gate-dielectric tunnel FET (HGD-TFET). By solving the Poisson equation, the surface potential model is developed. The developed potential model is then used for developing the terminal capacitance model and drain current model. The device is working under enhancement-mode as the channel region is considered to be n-type doped. For developing the charge model, accumulated charges and ionized impurity charges are included in the channel charge equation. The developed model can capture the impact of V G = 0 V and V D = 0 V. The model can also successfully capture the scaling issues and gate dielectric variation. To ensure the performance of the developed model, the results are validated with TCAD simulation results and a good agreement is achieved between them. Since, high-k gate dielectric and low-k gate dielectric are used in a single structure, it combines the merit of both and hence, results in the performance improvement. • Physics-based analytical model has been developed for Hetero-gate dielectric TFET. • Surface potential, capacitance and drain current for HGD-TFET are modeled. • The models include the impact of zero gate bias and zero drain bias. • Impact of scaling and dielectric variation can also be captured by the developed model.

Why and How ITRS Worked to Recover the Breakdown of “Scaling Law” in 2000s—Structural Frame Analysis of Si-CMOS Semiconductor Technologies

International Technology Roadmap for Semiconductors (ITRS) is referred to as one of the most successful roadmapping attempts in high-tech industries. ITRS constantly gave orientation to industries (device/equipment/materials), academia, and governments for continuing miniaturization. The 2000s, the period of utmost attention to ITRS, is also the period of gradual “breakdown” of Dennard's Scaling Law which stipulates the “technological merits” attained by miniaturization of Si-CMOS semiconductors: 1) shrink in chip size; 2) lowered power consumption, and 3) boosted computation speed, simultaneously. The author discusses that ITRS of 2000s had worked for “recovering” the “breakdown” of the Law and that it is attributed to the highly structured nature of Si-CMOS semiconductor technologies in a frame of “(manufacturing) process-device structure-function.” Then, he evaluates the validity of the hypothesis by analyzing wide range of technologies newly introduced in 2000s, namely 1) variety of supplementary methods for “prolonging” the life of Argon Fluoride Laser lithography; 2) high-k dielectric membranes and metal gate for reducing gate-leak current; and 3) low-k dielectric membranes and strained-silicon transistors to boost computation speed. Thus, the author concludes that 1) ITRS at least functioned to let the consensus (among early adopters) be “established” in wide range of research community; 2) under the “gradual breakdown” of Dennard's Scaling Law in 2000s, ITRS worked to keep the Si-CMOS semiconductor's “killing-three-birds-with-one-stone” nature; and 3) the success of ITRS in 2000s is attributed to the structural frame of Si-CMOS semiconductor technologies characterized as “fixed-in-total and disruptive-in-parts.”