High-density Integration Research Articles

High performance junctionless FDSOI SiGe channel p-FinFET with high ION/IOFF ratio and excellent SS

This paper presents a novel FDSOI FinFETs with SiGe channel/Si cap layer (35 nm/5 nm) formed on SOI wafers with 20 nm Si body. Electrical characterization result shows that JL FDSOI FinFETs with SiGe channel exhibited low subthreshold slope (SS) of 86 mV/decade and record high ON-OFF current ratio (ION/IOFF = 2 × 106) at VD = -0.5V, respectively. Device performance improvement was mainly attributed to high-epitaxial quality compressive strained SiGe channel and novel device structure. The strain in the channel of the transistors was estimated locally in TEM using Nano beam diffraction (NBD) technique. The FDSOI FinFET with SiGe channel, lays the foundation for the further development of high speed, high density, low cost, and 3D monolithic integration circuits.

Self‐assembled vapor-transport-deposited SnS nanoflake-based memory devices with synaptic learning properties

The most salient features of resistive switching (RS) devices are low energy consumption, fast switching speed, and high-density integration, which render them promising candidates for realizing non-volatile memory and artificial synaptic devices. However, the growth of functional switching layers for RS devices needs innovative deposition techniques. Herein, we utilize a high-throughput vapor-transport-deposition (VTD) technique for synthesizing self-assembled tin-sulfide (SnS) nanoflakes, which are then used as a switching layer to fabricate an RS device. First principle calculations are conducted to understand the optoelectronic properties of SnS by employing density functional theory. The proposed Ag/SnS/Pt memory device exhibits substantial merits, including low-switching voltages (VSET: 0.22 V and VRESET: −0.20 V), suitable ON/OFF ratio (∼259), excellent endurance (106), and extended memory retention (106 s) characteristics. In addition, RS stochasticity is modeled using statistical time-series analysis via Holt’s exponential smoothing. Interestingly, the device can emulate multiple synaptic functionalities, including potentiation, depression, paired-pulse facilitation, paired-pulse depression, excitatory postsynaptic current, inhibitory postsynaptic current, and advanced spike-timing dependent plasticity rules. Moreover, the proposed synaptic device can detect the edge of images by utilizing a convolutional neural network. The unique and efficient VTD-SnS-based device will be a potential candidate for high-density non-volatile memory and neuromorphic computing applications.

High-Density Artificial Synapse Array Consisting of Homogeneous Electrolyte-Gated Transistors.

The artificial synapse array with an electrolyte-gated transistor (EGT) as an array unit presents considerable potential for neuromorphic computation. However, the integration of EGTs faces the drawback of the conflict between the polymer electrolytes and photo-lithography. This study presents a scheme based on a lateral-gate structure to realize high-density integration of EGTs and proposes the integration of 100×100 EGTs into a 2.5×2.5cm2 glass, with a unit density of up to 1600devicescm-2 . Furthermore, an electrolyte framework is developed to enhance the array performance, with ionic conductivity of up to 2.87×10-3 Scm-1 owing to the porosity of zeolitic imidazolate frameworks-67. The artificial synapse array realizes image processing functions, and exhibits high performance and homogeneity. The handwriting recognition accuracy of a representative device reaches 92.80%, with the standard deviation of all the devices being limited to 9.69%. The integrated array and its high performance demonstrate the feasibility of the scheme and provide a solid reference for the integration of EGTs.

Monolithic 3D integration of 2D materials-based electronics towards ultimate edge computing solutions.

Three-dimensional (3D) hetero-integration technology is poised to revolutionize the field of electronics by stacking functional layers vertically, thereby creating novel 3D circuity architectures with high integration density and unparalleled multifunctionality. However, the conventional 3D integration technique involves complex wafer processing and intricate interlayer wiring. Here we demonstrate monolithic 3D integration of two-dimensional, material-based artificial intelligence (AI)-processing hardware with ultimate integrability and multifunctionality. A total of six layers of transistor and memristor arrays were vertically integrated into a 3D nanosystem to perform AI tasks, by peeling and stacking of AI processing layers made from bottom-up synthesized two-dimensional materials. This fully monolithic-3D-integrated AI system substantially reduces processing time, voltage drops, latency and footprint due to its densely packed AI processing layers with dense interlayer connectivity. The successful demonstration of this monolithic-3D-integrated AI system will not only provide a material-level solution for hetero-integration of electronics, but also pave the way for unprecedented multifunctional computing hardware with ultimate parallelism.

Ultralow-resistance electrochemical capacitor for integrable line filtering.

Electrochemical capacitors are expected to replace conventional electrolytic capacitors in line filtering for integrated circuits and portable electronics1-8. However, practical implementation of electrochemical capacitors into line-filtering circuits has not yet been achieved owing to the difficulty in synergistic accomplishment of fast responses, high specific capacitance, miniaturization and circuit-compatible integration1,4,5,9-12. Here we propose an electric-field enhancement strategy to promote frequency characteristics and capacitance simultaneously. By downscaling the channel width with femtosecond-laser scribing, a miniaturized narrow-channel in-plane electrochemical capacitor shows drastically reduced ionic resistances within both the electrode material and the electrolyte, leading to an ultralow series resistance of 39 mΩ cm2 at 120 Hz. As a consequence, an ultrahigh areal capacitance of up to 5.2 mF cm-2 is achieved with a phase angle of -80° at 120 Hz, twice as large as one of the highest reported previously4,13,14, and little degradation is observed over 1,000,000 cycles. Scalable integration of this electrochemical capacitor into microcircuitry shows a high integration density of 80 cells cm-2 and on-demand customization of capacitance and voltage. In light of excellent filtering performances and circuit compatibility, this work presents an important step of line-filtering electrochemical capacitors towards practical applications in integrated circuits and flexible electronics.

3D printing of a SiO2@BN TPMS structure: Efficient heat transfer strategy for BN/epoxy composites

The high integration density of microelectronic devices leads to local heat accumulation, and effective heat dissipation and signal transmission of packaging materials have become the primary issues to be solved. However, existing polymer materials have difficulty meeting the requirements due to their unsatisfactory thermal conductivity and thermal expansion properties. In this work, we proposed the use of digital light processing (DLP) printing technology to construct a triply periodic minimum surface (TPMS) skeleton, and a continuous and efficient heat conduction path was successfully constructed in epoxy resin by impregnating h-BN on the skeleton surface. When the loading of h-BN was 20 vol%, the thermal conductivity of the TPMS(SiO2)@BN/EP(BN) composites was 1.86 W/(m·K), which was 786 % higher than that of pure epoxy resin. In addition, the thermal expansion coefficient of the composites decreased by more than 70 %. At the test frequencies of 3∼10 MHz, the composites showed stable dielectric properties, and the dielectric constant was always maintained in a low range, between 3.85 and 4.15. This work has realized the transformation of the method for constructing a heat conduction path from disordered to ordered and from random to repeatable. This provides a new strategy for the selection of microelectronic packaging materials.

GWalloc: A self-adaptive generational wear-aware allocator for non-volatile main memory

Phase Change Memory (PCM) is considered a promising replacement for DRAM due to its superior performance characteristics such as low leakage power, high integration density, byte addressability and non-volatility. However, PCM’s limited write endurance significantly hinders its wide application. For example, PCM wears out quickly with traditional dynamic memory allocation policy in embedded systems which aggregates lots of writes in few memory blocks. To extend the lifespan of PCM, some wear-aware dynamic memory allocators have been proposed, which generally depend on some fixed parameters to limit the wear of PCM. However, these allocators can be inflexible as it is difficult to specify appropriate values for the required parameters in different scenarios. In this paper, we propose a Self-Adaptive Generational Wear-Aware Allocator (GWalloc). GWalloc divides memory blocks into two generations: the young and the old generation, according to their number of allocation times. GWalloc also dynamically adjusts the system’s wear threshold during allocations so that it can effectively balance the wear degree of PCM and the consumed memory space. The wear threshold restricts the upper wear limit of young memory blocks. Experimental evaluations show that compared with the state-of-the-art wear-aware dynamic memory allocators (NVMalloc, Walloc and UWLalloc), GWalloc improves PCM wear-leveling (evaluated by CV, a wear leveling indicator) by 38.6%, 39.1% and 38.3%, and saves 62.1%, 22.2% and 37.2% memory space overhead.

A Compact Fully-Differential Distributed Amplifier with Coupled Inductors in 0.18-µm CMOS Technology

This paper presents a compact fully-differential distributed amplifier using a coupled inductor. Differential distributed amplifiers are widely required in optical communication systems. Most of the distributed amplifiers reported in the past are single-ended or pseudo-differential topologies. In addition, the differential distributed amplifiers require many inductors, which increases the silicon cost. In this study, we use differentially coupled inductors to reduce the chip area to less than half and eliminate the difficulties in layout design. The challenge in using coupled inductors is the capacitive parasitic coupling that degrades the flatness of frequency response. To address this challenge, the odd-mode image parameters of a differential artificial transmission line are derived using a simple loss-less model. Based on the analytical results, we optimize the dimensions of the inductor with the gradient descent algorithm to achieve accurate impedance matching and phase matching. The amplifier was fabricated in 0.18-μm CMOS technology. The core area of the amplifier is 0.27 mm2, which is 57% smaller than the previous work. Besides, we demonstrated a small group delay variation of ±2.7 ps thanks to the optimization. the amplifier successfully performed 30-Gbps NRZ and PAM4 transmissions with superior jitter performance. The proposed technique will promote the high-density integration of differential traveling wave devices.

Bonding Property of Flip-Chip Chip-Scale Package with Vacuum Reflow and Thermal Compression Bonding Processes

The package-on-package technology has been developed to facilitate high-density integration of semiconductor packaging. As the solder bump pitch is decreased, the void content in solder bump joints increases, thereby decreasing its reliability. Consequently, vacuum reflow (VR) is used to increase void fluidity and decrease void content in micro bump joints. Generally, silicon chips in application processor modules are bonded using thermal compression (TC) bonding, followed by the attachment of passive components through hot air reflow soldering. However, the simultaneous bonding of Si chips and passive components using VR can improve productivity.In this study, we performed TC and VR bonding without additional solder pastes, between an Si chip with a Cu pillar/Sn-2.5Ag bump and a bismaleimide triazine substrate plated with electroless-nickel electroless-palladium immersion-gold. It was observed that the void content at the Si chip solder joints yielded by VR (10.8%) was similar to that yielded by TC (11.2%). Furthermore, the Si chip solder joint of the VR sample was thicker than that of the TC sample. This process also resulted in the formation of the intermetallic compounds Cu<sub>6</sub>Sn<sub>5</sub>, (Cu,Ni)<sub>6</sub>Sn<sub>5</sub>, Ag<sub>3</sub>Sn, and Ni<sub>3</sub>P, at the Si chip solder joints. The results of this study suggest that co-bonding of active and passive components is possible through VR soldering for semiconductor packaging.

Hybrid Dry and Wet Etching of LiNbO3 Domain-Wall Memory Devices with 90° Etching Angles and Excellent Electrical Properties.

Ferroelectric domain walls, agile nanoscale interfaces of polar order, can be selectively controlled by electric fields for their position, conformation, and function, which is ultimately the key to realizing novel low-energy memory and computing structures. LiNbO3 single-crystal domain wall memory has the advantages of high operational speed, high integration density, and virtually unlimited endurance cycles, appearing as a good solution for the next generation of highly miniaturized low-energy memories. However, the etching process poses significant challenges in the nanofabrication and high-density integration of LiNbO3 domain-wall memories. Here, we employed a hybrid etching technique to achieve smooth sidewalls with a 90° inclined angle, leading to a 24% reduction in the coercive field and a 2.5-fold increase in the linear domain wall current density with a retention time of more than 106 seconds and endurance of over 105 writing cycles. Combined with the results of X-ray diffraction patterns and X-ray photoelectric spectra, it is concluded that the excellent electrical performance is related to the formation of an oxygen-deficient LiNbO3-x layer on the sidewall surface during the wet chemical etching process, which is a conductive layer that reduces the thickness of the "dead" layer between the side electrodes and the LiNbO3 cell and rectifies the diode-like wall currents with an onset voltage reduced from 1.23 to 0.28 V. These results prove the high-density integration of ferroelectric domain-wall memories at the nanoscale and provide a new strategy applicable to the development of LiNbO3 photonic devices.

Controllable analog-to-digital bipolar resistive switching behavior and mechanism analysis in δ-MnO2-based memristor

Memristor is one of the most emerging electronic components to realize synaptic functions in the neuromorphic computing. Memristor with controllable analog-to-digital resistive switching behaviors has the potential to considerably accelerate the realization of high-performance neuromorphic computing. In this work, a memristor with Ag/δ-MnO2/Ti structure was fabricated, and an analog-to-digital resistive switching behavior with voltage regulation was demonstrated. Memristive switching with analogue characteristics can generate a gradual increase in conductance at low voltage of less than 1.3 V to aid in the building of artificial synapses. The Ag/δ-MnO2/Ti memristor with excellent digital resistive switching performance can be applied for data storage and in-memory computation at voltage windows of higher than 1.3 V. Furthermore, the resistive switching mechanism was analyzed by employing the first-principle calculation. The main reason for the emergence of digital memristor characteristics is the Ag+ ions can enter to the δ-MnO2 layer driven by a larger voltage and continue to cluster and form conductive filament. This work enriches the application of analog-to-digital bipolar memristor in neuromorphic computing, and facilitates further realization of memristor in low-power and high-density circuit integration.

Ultra High-Density SOT-MRAM Design for Last-Level On-Chip Cache Application

This paper presents ultra high-density spin-orbit torque magnetic random-access memory (SOT-MRAM) for last-level data cache application. Although SOT-MRAM has many appealing attributes of low write energy, nonvolatility, and high reliability, it poses challenges to ultra-high-density memory implementation. Due to using two access transistors per cell, the vertical dimension of SOT-MRAM is >40% longer than that of the spin-transfer torque magnetic random-access memory (STT-MRAM), a single transistor-based design. Moreover, the horizontal dimension cannot be reduced below two metal pitches due to the two vertical metal stacks per cell. This paper proposes an ultra-high-density SOT-MRAM design by reducing the vertical and horizontal dimensions. The proposed SOT-MRAM is designed by a single transistor with a Schottky diode to achieve lesser vertical dimension than the two-transistor-based design of conventional SOT-MRAM. Moreover, the horizontal dimension is also reduced by sharing a vertical metal between two consecutive bit-cells in the same row. The comparison of the proposed designs with the conventional SOT-MRAM reveals a 63% area reduction. Compared with STT-MRAM, the proposed high-density memory design achieves 48% higher integration density, 68% lower write power, 29% lower read power, and 1.9× higher read-disturb margin.

Emerging Opportunities for 2D Materials in Neuromorphic Computing.

Recently, two-dimensional (2D) materials and their heterostructures have been recognized as the foundation for future brain-like neuromorphic computing devices. Two-dimensional materials possess unique characteristics such as near-atomic thickness, dangling-bond-free surfaces, and excellent mechanical properties. These features, which traditional electronic materials cannot achieve, hold great promise for high-performance neuromorphic computing devices with the advantages of high energy efficiency and integration density. This article provides a comprehensive overview of various 2D materials, including graphene, transition metal dichalcogenides (TMDs), hexagonal boron nitride (h-BN), and black phosphorus (BP), for neuromorphic computing applications. The potential of these materials in neuromorphic computing is discussed from the perspectives of material properties, growth methods, and device operation principles.

Site-Specific Emulation of Neuronal Synaptic Behavior in Au Nanoparticle-Decorated Self-Organized TiOx Surface.

Neuromorphic computing is a potential approach for imitating massive parallel processing capabilities of a bio-synapse. To date, memristors have emerged as the most appropriate device for designing artificial synapses for this purpose due to their excellent analog switching capacities with high endurance and retention. However, to build an operational neuromorphic platform capable of processing high-density information, memristive synapses with nanoscale footprint are important, albeit with device size scaled down, retaining analog plasticity and low power requirement often become a challenge. This paper demonstrates site-selective self-assembly of Au nanoparticles on a patterned TiOx layer formed as a result of ion-induced self-organization, resulting in site-specific resistive switching and emulation of bio-synaptic behavior (e.g., potentiation, depression, spike rate-dependent and spike timing-dependent plasticity, paired pulse facilitation, and post tetanic potentiation) at nanoscale. The use of local probe-based methods enables nanoscale probing on the anisotropic films. With the help of various microscopic and spectroscopic analytical tools, the observed results are attributed to defect migration and self-assembly of implanted Au atoms on self-organized TiOx surfaces. By leveraging the site-selective evolution of gold-nanostructures, the functionalized TiOx surface holds significant potential in a multitude of fields for developing cutting-edge neuromorphic computing platforms and Au-based biosensors with high-density integration.

Vacuum Tunneling Transistor with Nano Vacuum Chamber for Harsh Environments.

A nano vacuum tube which consists of a vacuum transistor and a nano vacuum chamber was demonstrated. For the device, a vacuum region is an electron transport channel, and a vacuum is a tunneling barrier. Tilted angle evaporation was studied for the formation of the nano level vacuum chamber structure. This vacuum tube was ultraminiaturized with several tens of 10-18 L scale volume and 10-6 Torr of pressure. The device structure made it possible to achieve a high integration density and to sustain the vacuum state in various real operations. In particular, the vacuum transistor performed stably in extreme external environments because the tunneling mechanism showed a wide range of working stability. The vacuum was sustained well by the sealing layer and provided a defect-free tunneling junction. In tests, the high vacuum level was maintained for more than 15 months with high reliability. The Al sealing layer and tube structure can effectively block exposed light such as visible light and UV, enabling the stable operation of the tunneling transistor. In addition, it is estimated that the structure blocks approximately 5 keV of X-ray. The device showed stable operating characteristics in a wide temperature range of 100-390 K. Therefore, the vacuum tube can be used in a wide range of applications involving integrated circuits while resolving the disadvantages of a large volume in old vacuum tubes. Additionally, it can be an important solution for next-generation devices in various fields such as aerospace, artificial intelligence, and THz applications.

Exploring amorphous Ge-As-Se-Te as an active layer candidate in memristive devices

The implementation of resistive switches in neuromorphic computing and long-term data storage has been delayed by inherent difficulties in their fabrication process, their stability and reproducibility. Low operating voltages, high-density integration and low energy consumption are common challenges in resistive switch design. Here, we report the implementation of a resistive switch based on the amorphous semiconductor Ge15As25Se15Te45 (GAST) between an inert (W) and an active (Ag) electrode. The device was built using contact photolithography and standard microfabrication techniques, allowing the integration with traditional manufacturing processes. The device is able to switch at voltages as low as 0.15V and 0.6V, when operating in DC and pulsed conditions, respectively. Our results suggest that the adoption of mixed conductors such as GAST may yield devices that operate at low voltages and low energy for neuromorphic applications.

Thermal Crosstalk Analysis of Phase Change Memory Considering Thermoelectric Effect and Thermal Boundary Resistance

Phase change memory (PCM) has emerged as a promising memory for next-generation applications due to its high-speed read and write capabilities as well as non-volatility. However, as PCM scales down to smaller feature sizes, it faces the challenge of thermal crosstalk. During the reset operation, a large amount of heat is generated and dissipated in the PCM array, potentially affecting adjacent memory cells, compromising device stability, and limiting high-density integration. To accurately investigate the thermal crosstalk in the PCM array, the conventional finite element model of the PCM array is improved by incorporating the thermoelectric effect and thermal boundary resistance. Under the 65, 45, 32, and 22-nm process nodes, the improved model reveals the occurrence of thermal crosstalk within the PCM array, whereas the conventional model is unable to detect this phenomenon at the 65-nm node. The improved model proposed in this paper incorporates more comprehensive considerations, providing a more precise analysis of the thermal crosstalk phenomenon in the PCM array, and thereby offering theoretical reference for high-density integration of the PCM.

Single-Electron Transistor Operation of a Physically Defined Silicon Quantum Dot Device Fabricated by Electron Beam Lithography Employing a Negative-Tone Resist

We have proposed and demonstrated a device fabrication process of physically defined quantum dots utilizing electron beam lithography employing a negative-tone resist toward high-density integration of silicon quantum bits (qubits). The electrical characterization at 3.8 K exhibited so-called Coulomb diamonds, which indicates successful device operation as single-electron transistors. The proposed device fabrication process will be useful due to its high compatibility with the large-scale integration process.

Process and Design Challenges for Hybrid Bonding

Achieving high-quality interconnect interfaces for fine pitch integration is crucial in today's advanced electronic systems. Among various interconnect options, hybrid bonding stands out as a superior choice due to its ability to accommodate a high input/output (I/O) count, enabling high-density memory integration, increased power delivery, and improved signal speed. To ensure the utmost quality in hybrid bonding, embedding Cu interconnects within the dielectric layer has proven effective. Furthermore, the surface planarization process, accomplished through chemical mechanical polishing (CMP), plays a pivotal role. In this regard, the final CMP process typically involves a meticulous two-step procedure involving copper bulk CMP followed by barrier CMP. The latter yields the desired surface finish crucial for successful hybrid bonding. Several key surface properties, including copper recess (referred to as dishing) in the vias, erosion and roughness of the dielectric layer, and surface topography changes from high-density to low-density copper vias, significantly impact the overall bond yield. To optimize these parameters, a comprehensive understanding of the design of the interconnect layer for the CMP process is essential. In this study, we explore the impact of via scaling and via density for interconnect pitches from 5 μm to 1 μm and the surface topography due to dummy vias of the final bonding surface.

Microring structure for flexible polymer waveguide-based optical pressure sensing.

Flexible pressure sensors provide a promising platform for artificial smart skins, and photonic devices provide a new technique to fabricate pressure sensors. Here, we present a flexible waveguide-based optical pressure sensor based on a microring structure. The waveguide-based optical pressure sensor is based on a five-cascade microring array structure with a size of 1500 µm × 500 µm and uses the change in output power to linearly characterize the change in pressure acting on the device. The results show that the device has a sensing range of 0-60 kPa with a sensitivity of 23.14 µW/kPa, as well as the ability to detect pulse signals, swallowing, hand gestures, etc. The waveguide-based pressure sensors offer the advantages of good output linearity, high integration density and easy-to-build arrays.