High Gain Operational Amplifier Research Articles

A high-gain high-drive operational amplifier

Abstract This paper presents a high-gain, high-drive operational amplifier based on the 0.18 μm technology. The first stage employs a current-reuse common-source common-gate structure to enhance gain, while the second stage utilizes a transconductance-enhanced push-pull output stage. This design achieves high-drive performance while retaining a high gain. Simulation using Cadence software demonstrates that, under a 5 V power supply voltage, the amplifier exhibits a low-frequency gain of 120 dB, with output sink and source current capabilities reaching 17.7 mA and 2.53 mA, respectively.

Design, Simulation and Comparative Analysis of Two Stage Operational Amplifier Based on CNTFETs Using Indirect Feedback Frequency Compensation

In the course of this study, an efficient implementation of a high gain and low power two-stage operational amplifier using indirect feedback frequency compensation based on CNTFETs. HSPICE software was used to develop and simulate CNTFETs. The op-amps were designed using 0.9[Formula: see text]V input supply voltage. The proposed structures were formed either using CNTFETs only known as pure CNTFET-IFFC-2SOA or hybrid structures consisting a mix of both CNTFETs and conventional CMOS named as PCNTFET-NMOS-IFFC-2SOA and NCNTFET-PMOS-2SOA. The comparative investigation revealed that CNT-based structures performed significantly better than the traditional CMOS-based devices. In the instance of CNTFET-IFFC-2SOA, there was a considerable improvement in DC gain, power dissipation, phase margin, and CMRR. The DC Gain increased by 140.92%, the CMRR increased by 32.94%, and the phase margin increased by 4.9%. Furthermore, at the 32[Formula: see text]nm technology node, a GNRFET-based structure was designed and compared to conventional CMOS and pure CNTFET-based IFFC-2SOA. It was discovered that the DC gain, phase margin, and power dissipation obtained by the CNTFET-based structure were superior to both. The DC Gain of CNTFET-IFFC-2SOA was 156.79% more than that of GNRFET-IFFC-2SOA. To confirm the workability of the proposed circuits, an integrator was designed and simulated as its application. The CNTFET-based IFFC-2SOA integrators showed better integration action than the traditional CMOS-IFFC-2SOA.

A 65 nm CMOS rail-to-rail auto-zero operational amplifier based on charge pump internal power supply

A high-gain, low-offset, and low-power auto-zero operational amplifier with rail-to-rail input/output is proposed. Based on a time-interleaved charge pump high-voltage on-chip internal power supply, the PMOS differential pair input configuration will achieve a rail-to-rail input range with constant transconductance. Time-interleaved auto-zero continuously eliminates the input offset voltage of the operational amplifier in the time domain. An nA-level bias circuit to realize low power. The operational amplifier circuit is based on a 65 nm CMOS process. Under 1.2V power supply voltage and temperature 27 °C, the input offset voltage of the operational amplifier is 3.16 μV and the input offset current is less than 20 pA. The temperature drift coefficient of offset voltage is 0.005 μV/°C between −40 °C and 90 °C. The variation rate of input transconductance is only 5.6 % among the rail-to-rail input range. The equivalent DC gain is 106.4 dB, the unit gain bandwidth is 0.54 MHz, the phase margin is 76.5°, and the power consumption is about 0.19 mW. The layout area is 0.83 × 0.75 mm2.

An NMOS transistor-based high-gain operational amplifier designed in 0.25-micron CMOS technology

This project describes in detail the process of designing and simulating at first a one stage folded cascode operational amplifier using 0.25 um CMOS Technology with the self-biasing scheme for the NMOS differential input stage is discussed here. The design of the required circuits is done using the LTspice simulator. We will see that the simulation results approximately matches with the desired and theoretically calculated performance values. We are changing width values to bring all the transistors of the circuit in saturation. Then two Stage Folded Cascode Operational Amplifier with Miller compensation technique for the NMOS input. The operational amplifiers circuit is designed with 0.25 µm CMOS Technology using LTspice software. The applied methodology to implement the circuit design for a given specification has clearly described including all the design equation has been presented. All the parameter like DC Gain and Phase Margin (PM) are presented and discussed. Finally, we have got after performance analysis that designed circuit based on NMOS input provide a 96 DC Gain.

A 50 dB high-gain operational amplifier integrated with metal-oxide TFTs

This paper presents a 50 dB high-gain operational amplifier (OPAMP), which is fabricated by unipolar n-type indium–zinc–oxide thin-film transistors. Different positive feedback technologies are employed to achieve sufficient voltage gain. The fabricated OPAMP exhibits an open-loop voltage gain (A v) of 50 dB over a −3 dB bandwidth of 15 kHz at the supply voltage of 20 V. The measured unity-gain frequency (f UG) and the DC power consumption are 500 kHz and 8.07 mW, respectively. In addition, an effective frequency compensation scheme is also introduced and simulated. The simulation results that the proposed OPAMP has a voltage gain of 50 dB with 60° phase margin at 150 kHz unity-gain frequency after compensation.

A Low-Voltage, Ultra-Low-Power, High-Gain Operational Amplifier Design for Portable Wearable Devices

Based on the SMIC 0.13 um CMOS technology, this paper uses a 0.8 V supply voltage to design a low-voltage, ultra-low-power, high-gain, two-stage, fully differential operational amplifier. Through the simulation analysis, when the supply voltage is 0.8 V, the design circuit meets the ultra-low power consumption and also has the characteristic of high gain. The five-tube, fully differential, and common-source amplifier circuits provide the operational amplifier with high gain and large swing. Unlike the traditional common-mode feedback, this paper uses the output of the common-mode feedback as the bias voltage of the five-tube operational transconductance amplifier load, which reduces the design cost of the circuit; the structure involves self-cascoding composite MOS, which makes the common-mode feedback loop more sensitive. The frequency compensation circuit adopts Miller compensation technology with zero-pole separation, which increases the stability of the circuit. The input of the circuit uses the current mirror. A small reference current is chosen to reduce power consumption. A detailed performance simulation analysis of this operational amplifier circuit is carried out on the Cadence spectre platform. The open-loop gain of this operational amplifier is 74.1 dB, the phase margin is 61°, the output swing is 0.7 V, the common-mode rejection ratio is 109 dB, and the static power consumption is only 11.2 uW.

Design of Low Voltage Low Power High Gain Operational Transconductance Amplifier

In this paper, a high gain structure of operational transconductance amplifier is presented. For low voltage operation with improved frequency response bulk driven quasi-floating gate MOSFET is used at the input. Further for achieving high gain the modified self cascode structure is used at the output. Compared to conventional self cascode the modified self cascode structure used provides higher transconductance which helps in significant boosting of gain of the amplifier. The modification is achieved by employing quasi-floating gate transistor which helps in scaling of the threshold which as a result increases the drain-to-source voltage of linear mode transistor thus changing it to saturation. This change of mode boosts the effective transconductance of self cascode MOSFET. The proposed operational transconductance amplifier when compared to its conventional showed improvement in DC gain by 30dB and also the unity gain bandwidth increases by 6 fold. The MOS models used for amplifier design are of 0.18µm CMOS technology at supply of 0.5V.

Design of high gain and high bandwidth operational transconductance amplifier (OTA)

ABSTRACT A novel operational transconductance amplifier (OTA) having high gain and high bandwidth for high-speed analog communication techniques and precision filtering is designed in this paper. The designed OTA uses β-multiplier-based current biasing scheme with folded cascode amplifier scheme in order to improve the small signal models and the DC gain of circuit. The OTA design was carried out using TSMC 65 nm CMOS technology using Cadence Virtuoso tool with 1 V supply voltage and 10 pf capacitive load. The output DC gain was found to be approximately 75.3 dB. In addition, the unity gain frequency for the designed OTA was found to be around 200 MHz. Superior common mode rejection ratio, power supply rejection ratio and slew rates along with compact chip area and low power are other salient features of the designed OTA. The designed OTA can be employed in order to design high performance analog circuits like data converters, phase-locked loops, etc.

Modification of De’ Sauty Bridge Network for Accurate Measurement of Process Variables by Variable Parameter Transducers

In variable parameter transducers, the small change in passive parameters such as resistance, capacitance, and inductance, generally changes linearly with the process variable in process plant. The classical method of measurement of passive parameters generally uses an ac bridge circuit. However, this type of bridge measurement technique suffers from errors due to the effect of stray capacitances in between bridge output terminals and ground. These errors can be minimized by using the Wagner-earth technique, but the limitation is the repetition of bridge balance, which is required in every observation so that continuous measurement is not possible, which is the basic needs of a transducer. In this article, a modified De’ Sauty bridge network has been developed by using a high-gain operational amplifier to minimize the stray capacitances in case of measurement of the small change in resistances or capacitances. A potentiometer has been used to adjust the sensitivity of the bridge. For a particular value of bridge sensitivity factor, the change of passive parameters of sensor equivalent and the change of actual process variables have been observed and found good linearity and repeatability.

Improvement of Gain Accuracy and CMRR of Low Power Instrumentation Amplifier Using High Gain Operational Amplifiers

Background: Sensing of biomedical signals is crucial for monitoring of various health conditions. These signals have a very low amplitude (in μV) and a small frequency range (<500 Hz). In the presence of various common-mode interferences, biomedical signals are difficult to detect. Instrumentation amplifiers (INAs) are usually preferred to detect these signals due to their high commonmode rejection ratio (CMRR). Gain accuracy and CMRR are two important parameters associated with any INA. This article, therefore, focuses on the improvement of the gain accuracy and CMRR of a low power INA topology. Objective: The objective of this article is to achieve high gain accuracy and CMRR of low power INA by having high gain operational amplifiers (Op-Amps), which are the building blocks of the INAs. Methods: For the implementation of the Op-Amps and the INAs, the Cadence Virtuoso tool was used. All the designs and implementation were realized in 0.18 μm CMOS technology. Results: Three different Op-Amp topologies namely single-stage differential Op-Amp, folded cascode Op-Amp, and multi-stage Op-Amp were implemented. Using these Op-Amp topologies separately, three Op-Amp-based INAs were realized and compared. The INA designed using the high gain multistage Op-Amp topology of low-frequency gain of 123.89 dB achieves a CMRR of 164.1 dB, with the INA’s gain accuracy as good as 99%, which is the best when compared to the other two INAs realized using the other two Op-Amp topologies implemented. Conclusion: Using very high gain Op-Amps as the building blocks of the INA improves the gain accuracy of the INA and enhances the CMRR of the INA. The three Op-Amp-based INA designed with the multi-stage Op-Amps shows state-of-the-art characteristics as its gain accuracy is 99% and CMRR is as high as 164.1 dB. The power consumed by this INA is 29.25 μW by operating on a power supply of ±0.9V. This makes this INA highly suitable for low power measurement applications.

High gain operational amplifier and a comparator with a‐IGZO TFTs

This study presents a novel high gain operational amplifier (op-amp) and a comparator using n -type all enhancement amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). The proposed op-amp employs regulated cascode topology in conjunction with capacitive bootstrap load, which enhances the gain to 159.87% (V/V) as compared to op-amp with bootstrapping load. In addition, common mode feedback is introduced in the circuit which improves the common-mode rejection ratio (CMRR) of the amplifier without hampering the output voltage swing. The proposed op-amp offers a voltage gain of 46.2 dB, phase margin of 67°, CMRR of 51.8 dB, unity gain frequency of 215 kHz and power consumption of 0.22 mW. Furthermore, a novel comparator circuit at a clock frequency of 50 kHz is reported. The power consumption of the circuit is 0.248 mW and it can discriminate a minimum voltage of 50 mV. The performance of the proposed circuits is demonstrated using an analytical model of a-IGZO in Cadence environment with a channel length of 20 µm at a supply voltage of 10 V. Further with the help of the circuits reported in this work, many sensing systems of practical importance can be developed, such as smart packaging and bio-medical wearable devices using flexible electronics.

An Ultra Low Power CMOS Sigma Delta ADC Modulator for System-on-chip (SoC) Temperature Sensor for Aerospace Applications

In the current paper, an accurate with low power consumed sigma delta (ΣΔ) analog to digital converter has been designed for the aerospace applications. The sigma delta ADC has been designed in such a way that it works fine with consumption of low power and high accuracy in the system on chip (SoC) temperature sensor where the analog output from the temperature sensor unit will be the fed to the analog to digital converter. To check the robustness, different parameters with variation has been analyzed. The high gain operational amplifier plays a vital role in the circuits design. Hence, a 30 MHz operational amplifier has also been proposed whose unity gain bandwidth (UGB) has been observed of about 30 MHz, 51.1dB dc gain and slew rate (SR) of about 27.9 V/ μsec. For the proper operation of the circuit, a power supply of +1.3V to -1.3V is used. The proposed sigma delta ADC modulator is showing better results over previously designed modulator in terms of power consumption, error and performance. The design and simulation have been tested with the help of cadence analog design environment with UMC 90nm CMOS process technology.

A Sampling Holder Using A Bootstrapped Switch

This paper describes the design of a sampling holder, Using a higher linearity bootstrapped switch, by using the bottom plate sampling to offset the effect of charge injection effect, By using the capacitance flip type structure to reduce power consumption, designing a high gain and high speed operational trans-conductance amplifier to improve gain and speed.

A 43-mW MASH 2-2 CT $\Sigma \Delta$ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS

This paper proposes a multistage noise-shaping continuous-time sigma-delta modulator (CT $\Sigma \Delta \text{M}$ ) with on-chip RC time constant calibration circuits, multiple feedforward interstage paths, and a fully integrated noise-cancellation filter (NCF). The core modulator architecture is a cascade of two single-loop second-order CT $\Sigma \Delta \text{M}$ stages, each of which consists of an integrator-based active- RC loop filter, current-steering feedback digital-to-analog converters, and a 4-b flash quantizer. On-chip RC time constant calibration circuits and high-gain multistage operational amplifiers are realized to mitigate quantization noise leakage due to process variation. Multiple feedforward interstage paths are introduced to: 1) synthesize a fourth-order noise transfer function with dc zeros; 2) simplify the design of NCF; and 3) reduce signal swings at the second-stage integrator outputs. Fully integrated in 40-nm CMOS, the prototype chip achieves 74.4 dB of signal-to-noise-and-distortion ratio (SNDR), 75.8 dB of signal-to-noise ratio, and 76.8 dB of dynamic range in 50.3 MHz of bandwidth (BW) at 1 GHz of sampling frequency with 43 mW of power consumption (P) from 1.1/1.15/2.5-V power supplies. It does not require external software calibration and possesses minimal out-of-band signal transfer function peaking. The figure-of-merit (FOM), defined as $\text {FOM}=\text {SNDR}+10\times \log _{10}(\text {BW}/\text {P})$ , is 165.1 dB.

Synthesis of High Gain Operational Transconductance Amplifiers for Closed-Loop Operation Using a Generalized Controller-Based Compensation Method

This paper presents a systematic procedure that can be used to create operational transconductance amplifiers (OTAs) for closed-loop operation using multiple low-gain stages to realize extremely high DC gain. Such devices are necessary to realize analog functions with demanding absolute accuracy requirements, e.g., high-resolution ADCs and DACs. The principle is based on the cascade of undamped integrators to realize large DC gains and a state-space derived controller to stabilize its operation in a closed-loop configuration. A programmable OTA fabricated in the IBM 130 nm CMOS process is used as a test vehicle to prove the design principle through its 2 to 5th-order realization. Measured data reveals DC gains ranging from 50 to 150 dB with a 3-dB bandwidth of 10 kHz and a unity gain frequency of 10 MHz. While this paper demonstrates the design principles using CMOS integrated circuits, the principle is general and can be applied to any type of circuit technology in integrated or discrete implementation. Moreover, the methods are easily automated as the principles are based on closed-form formulae as opposed to iterative numerical search techniques.

Low Power and High Gain Operational Transconductance Amplifier

A Positive feedback method for operational transconductance amplifiers is proposed operating at subthreshold region. In this paper a differential amplifier has designed with gain enhancement technique using positive feedback. The proposed circuit has improved specifications such as high DC gain, low power dissipation as compared to previous work. We designed CMOS OTA in a UMC 180nm technology powered with 1.8V exhibits 91.23-dB DC gain while consuming 35.72nW.

A simple structure for noise-shaping SAR ADC in 90 nm CMOS technology

This paper presents a simple structure for error feedback based noise-shaping successive approximation register (NSSAR) analog-to-digital converter (ADC), which obviates the need for a high output swing, fast-settling and high gain Operational Transconductance Amplifier (OTA). The ADC has a simple structure and its quantization noise is extracted and transferred via a finite impulse response (FIR) filter, without any attenuation. To make a good matching, a 5-bit segmented array is utilized as a digital-to-analog converter (DAC). In this way, the required total capacitance of the ADC is reduced more than 96% compared to a 10-bit conventional SAR (CSAR) ADC. Also, due to noise-shaping property the comparator specifications are relaxed. The ADC is designed and simulated in 90nm CMOS technology with HSPICE simulator. Simulation results show that the ADC's average power consumption is about 4.4μW at a 0.5V power supply. By using an oversampling ratio (OSR) of 16, the ADC achieved maximum SNDR and SFDR of 59.6dB and 58dB, respectively, from transient noise simulation. The figure of merit (FoM) is about 56.4fJ/conversion-step.

3段構成高利得 CMOS OPアンプの一設計

3段構成高利得 CMOS OPアンプの一設計

A low phase noise and low power 3–5 GHz frequency synthesizer in 0.18 µm CMOS technology

A low power frequency synthesizer for WLAN applications is proposed in this paper. The NMOS transistor-feedback voltage controlled oscillator (VCO) is designed for the purpose of decreasing phase noise. TSPC frequency divider is designed for widening the frequency range with keeping low the power consumption. The phase frequency detector (PFD) with XOR delay cell is designed to have the low blind and dead zone, also for neutralizing the charge pump (CP) output currents; the high gain operational amplifier and miller capacitors are applied to the circuit. The frequency synthesizer is simulated in 0.18µm CMOS technology while it works at 1.8V supply voltage. The VCO has a phase noise of −136dBc/Hz at 1MHz offset. It has 10.2% tuning range. With existence of a frequency divider in the frequency synthesizer loop the output frequency of the VCO can be divided into the maximum ratio of 18. It is considered that the power consumption of the frequency synthesizer is 4mW and the chip area is 10,400µm2.

A High-Gain and Low-Noise 0.9 µW Operational Amplifier

A low-voltage, low-power, high-gain and low-noise operational transconductance amplifier (OTA) by modifying conventional one is presented and analyzed. Design strategies are discussed for minimizing noise and increasing gain. The simulation results show that the open loop gain is improved from 68 dB to 74 dB and the input referred noise is also reduced from 926 / nV Hz to 475 / nV Hz . This amplifier operates at 0.8 V power supply voltage with a power consumption of 0.9 µW. All the simulations are obtained by using Hspice tool with 0.18 µm CMOS TSMC parameters.