A low phase noise and low power 3–5 GHz frequency synthesizer in 0.18 µm CMOS technology

Abstract

A low power frequency synthesizer for WLAN applications is proposed in this paper. The NMOS transistor-feedback voltage controlled oscillator (VCO) is designed for the purpose of decreasing phase noise. TSPC frequency divider is designed for widening the frequency range with keeping low the power consumption. The phase frequency detector (PFD) with XOR delay cell is designed to have the low blind and dead zone, also for neutralizing the charge pump (CP) output currents; the high gain operational amplifier and miller capacitors are applied to the circuit. The frequency synthesizer is simulated in 0.18µm CMOS technology while it works at 1.8V supply voltage. The VCO has a phase noise of −136dBc/Hz at 1MHz offset. It has 10.2% tuning range. With existence of a frequency divider in the frequency synthesizer loop the output frequency of the VCO can be divided into the maximum ratio of 18. It is considered that the power consumption of the frequency synthesizer is 4mW and the chip area is 10,400µm2.