High-frequency Figures Of Merit Research Articles

Asymmetric trench SiC MOSFET with integrated channel accumulation diode for enhanced reverse conduction and switching characteristics

A novel asymmetric trench Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor (SiC MOSFET), featuring an integrated channel accumulation diode (CAD-MOS), has been proposed and investigated through numerical simulation. This innovative design aims to mitigate switching losses and eliminate the bipolar degradation of the body diode. The current spreading layer (CSL) channel, strategically positioned in the centre of the dummy gate, offers a low-barrier reverse conduction path. This represents a substantial advancement over the traditional PN body diode, significantly reducing the reverse conduction voltage drop from 2.84 V in the PN body diode to a mere 1.39 V in the CAD-MOS. Meanwhile, the reverse recovery charge of the CAD-MOS is reduced to 0.95 μC/cm2, and the peak reverse recovery current stands at 45 A/cm2. Compared to conventional asymmetrical trench SiC MOSFET (CON-MOS), the CAD-MOS exhibits a 68.1 % reduction in reverse recovery charge and a 63.4 % decrease in peak reverse recovery current. The split-gate design also reduces the device gate to source capacitance (CGS), resulting in a 17.4 % reduction in total switching losses to 3.64 mJ/cm2. CAD-MOS also exhibits a reduced gate turn-on charge and demonstrates an enhancement in high-frequency figure of merit (HF-FOM) by 8.1 %.

Simultaneous improvement of high-frequency and Baliga figures of merit of 1.7 kV 4H-SiC MOSFET with retrograded JFET doping

The 1.7 kV 4H-SiC MOSFET which features optimized retrograded-profile ion implantation in the JFET regions (RG-MOS) is proposed and fabricated on the 4 inch wafers. The measured results quantify the benefits of the RG-MOS structure: simultaneous improvement in high-frequency figures of merit (HF-FOM) (R on× C GD) by 1.5×, HF-FOM (R on × Q GD) by 1.5× and Baliga figure of merit (BFOM = 4BV2/R on,sp) by 1.6× compared with the conventional MOSFET (CON-MOS). Unlike other reported complicated structures which need high-precise fabricating process, the proposed RG-MOS structure is compatible with the prior planar 4H-SiC MOSFET process, and is favorable for large-scale production.

A novel 4H-SiC multiple stepped SGT MOSFET with improved high frequency figure of merit

A novel 4H-SiC Multiple Stepped SGT MOSFET (MSGT-MOSFET) is presented and investigated utilizing TCAD simulations in this paper. We have quantitatively studied the characteristics of the device through simulation modeling and physical model calculations, and comparatively analyzed the performance and application prospects of this novel device. The gate-to-drain capacitance (Cgd) and gate-to-drain charge (Qgd) of the MSGT-MOSFET are significantly reduced in comparison with the double trench MOSFET (DT-MOSFET) and the conventional SGT MOSFET (CSGT-MOSFET), due to the reduction of the overlapping area of the split gate (SG) structure and drift region. Therefore, the obtained high frequency figure of merit (HF-FOM) defined as [Ron × Cgd] reduced by 23.9% compared with DT-MOSFET and CSGT-MOSFET. And the HF-FOM [Ron × Qgd] for the MSGT-MOSFET significantly decreased by 71% and 50%, respectively, compared to that of the DT-MOSFET and CSGT-MOSFET. Furthermore, the switching loss is also simulated and calculated. And the total switching loss of the proposed MSGT-MOSFET realizes 42.9% and 21.7% reduction in comparison with the DT-MOSFET and CSGT-MOSFET. The overall enhanced performances suggest that the MSGT-MOSFET is an excellent choice for high frequency power electronic applications.

SiC trench MOSFET with dual shield gate and optimized JFET layer for improved dynamic performance and safe operating area capability

A novel silicon carbide (SiC) trench metal–oxide–semiconductor field-effect transistor (MOSFET) with a dual shield gate (DSG) and optimized junction field-effect transistor (JFET) layer (ODSG-TMOS) is proposed. The combination of the DSG and optimized JFET layer not only significantly improves the device’s dynamic performance but also greatly enhances the safe operating area (SOA). Numerical analysis is carried out with Silvaco TCAD to study the performance of the proposed structure. Simulation results show that comparing with the conventional asymmetric trench MOSFET (Con-ATMOS), the specific on-resistance (R on,sp) is significantly reduced at almost the same avalanche breakdown voltage (BV av). Moreover, the DSG structure brings about much smaller reverse transfer capacitance (C rss) and input capacitance (C iss), which helps to reduce the gate–drain charge (Q gd) and gate charge (Q g). Therefore, the high frequency figure of merit (HFFOM) of R on,sp ⋅ Q gd and R on,sp ⋅ Q g for the proposed ODSG-TMOS are improved by 83.5% and 76.4%, respectively. The switching power loss of the proposed ODSG-TMOS is 77.0% lower than that of the Con-ATMOS. In addition, the SOA of the proposed device is also enhanced. The saturation drain current (I d,sat) at a gate voltage (V gs) of 15 V for the ODSG-TMOS is reduced by 17.2% owing to the JFET effect provided by the lower shield gate (SG) at a large drain voltage. With the reduced I d,sat, the short-circuit withstand time is improved by 87.5% compared with the Con-ATMOS. The large-current turn-off capability is also improved, which is important for the widely used inductive load applications.

1.2 kV 4H–SiC Super Junction UMOSFET with a Low-K dielectric pillar

A 1.2 kV 4H–SiC Super Junction (SJ) UMOSFET with a Low-K (LK) dielectric pillar below the trench gate (LK-SJ-UMOSFET) is proposed in this paper. The device features a P-type doping pillar (P-pillar) at the source-side and a deep LK trench beneath the gate. Firstly, the gate-to-drain capacitance (Cgd) is greatly decreased by the LK dielectric pillar. Secondly, both the LK dielectric and the P-pillar cause the assistant depletion of the N-type doping pillar (N-pillar), resulting in an increased N-pillar doping concentration and a decreased specific on-resistance (Ron,sp). The proposed LK-SJ-UMOSFET is demonstrated to have a low high frequency Figure-Of-Merit (HF-FOM) Ron×Cgd = 28.628 mΩ pF and Ron × Qgd = 29.274 mΩ nC. The HF-FOM of the proposed 4H–SiC LK-SJ-UMOSFET is lower than that of the other 4H–SiC UMOSFET in recent simulation studies and reports.

A New Cell Topology for 4H-SiC Planar Power MOSFETs for High-Frequency Switching.

A new cell topology named the dodecagonal (a polygon with twelve sides, short for Dod) cell is proposed to optimize the gate-to-drain capacitance () and reduce the specific ON-resistance () of 4H-SiC planar power MOSFETs. The Dod and the octagonal (Oct) cells are used in the layout design of the 650 V SiC MOSFETs in this work. The experimental results confirm that the Dod-cell MOSFET achieves a 2.2× lower , 2.1× smaller high-frequency figure of merit (HF-FOM), higher turn on/off dv/dt, and 29% less switching loss than the fabricated Oct-cell MOSFET. The results demonstrate that the Dod cell is an attractive candidate for high-frequency power applications.

Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs.

650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal layout was used for the 650 V SiC MOSFETs to reduce the ON-resistance. The devices were packaged into open-cavity TO-247 packages for evaluation. Trade-off analysis of the static and dynamic performance of the 650 V SiC power MOSFETs was conducted. The measurement results show that a short JFET region with an enhanced JFET doping concentration reduces specific ON-resistance () and lowers the gate-drain capacitance (). It was experimentally shown that a thinner gate oxide further reduces , although with a penalty in terms of increased . A design with 0.5 m half JFET width, enhanced JFET doping concentration of cm−3, and thin gate oxide produces an excellent high-frequency figure of merit (HF-FOM) among recently published studies on 650 V SiC devices.

An enhanced high frequency performance SiC MOSFET with self-adjusting P-shield region potential

An enhanced high frequency (HF) performance SiC metal oxide semiconductor field effect transistor (MOSFET) with self-adjusting P-shield region potential (SA-MOS) is proposed and characterized in this paper. The potential of P-shield region (ground or floating potential) can be adjusted by a depletion P-channel metal oxide semiconductor field effect transistor (PMOS) structure integrated in the SA-MOS. During turn-on of SA-MOS, the channel of integrated PMOS is pinched off and the P-shield region can be at a floating potential. Therefore, SA-MOS shows about 21% specific on-resistance (R on,sp) reduction as compared to the conventional trench gate SiC MOSFET with grounded P-shield (GP-MOS) due to the retraction of depletion layer in drift region. During turn-off of SA-MOS, the integrated PMOS is turned on and the P-shield region is grounded to the source contact. Thus, the high on-state oxide electric field and slower switching speed caused by the floating P-shield region could be eliminated by SA-MOS structure. Furthermore, the gate-to-drain charge (Q gd) of SA-MOS is only 217 nC cm−2 owing to smaller overlap area between drift region and trench gate, which is about 40% lower than that of GP-MOS. The HF figures of merit (HF-FOM= R on,sp × Q gd) for SA-MOS can be as low as 50% or more of GP-MOS. Finally, an analytical model is also developed to describe the variation of P-shield potential in SA-MOS. With the overall improved performance, SA-MOS shows a significant advantage in HF field in comparison with the GP-MOS.

A comparative analysis and an optimized structure of vertical GaN floating gate trench MOSFET for high-frequency FOM

A vertical GaN floating gate trench MOSFET (FG-MOSFET) device structure has been optimized to obtain an enhanced high-frequency figure of merit (HF-FOM) than the conventional SGT- and TG-MOSFET. The floating gate (FG) electrode helps to reduce the surface electric field and binges in the middle of the drift layer. Using TCAD simulation, we demonstrate that with proper design of trench depth, drift doping, and field plate oxide thickness, the corresponding electric-field distribution for FG-MOSFET can be reduced to 2.3 MV cm−1. The proposed device has been designed for 600 V blocking voltage capability and with a specific on-resistance () as low as 0.73 mΩ cm2 due to the higher drift doping concentration. The HF-FOM () of FG-MOSFET shows a lower by two times and four times compared to SGT- and TG-MOSFET, due to FP oxide. Our results show that the FG-MOSFET device produces 15% and 47% reductions in the switching energy losses when compared with the similar current rated SGT- and TG-MOSFET devices, respectively.

A 1.2 kV SiC MOSFET with Integrated Heterojunction Diode and P-shield Region

A 1.2 kV SiC MOSFET with an integrated heterojunction diode and p-shield region (IHP-MOSFET) was proposed and compared to a conventional SiC MOSFET (C-MOSFET) using numerical TCAD simulation. Due to the heterojunction diode (HJD) located at the mesa region, the reverse recovery time and reverse recovery charge of the IHP-MOSFET decreased by 62.5% and 85.7%, respectively. In addition, a high breakdown voltage (BV) and low maximum oxide electric field (EMOX) could be achieved in the IHP-MOSFET by introducing a p-shield region (PSR) that effectively disperses the electric field in the off-state. The proposed device also exhibited 3.9 times lower gate-to-drain capacitance (CGD) than the C-MOSFET due to the split-gate structure and grounded PSR. As a result, the IHP-MOSFET had electrically excellent static and dynamic characteristics, and the Baliga’s figure of merit (BFOM) and high frequency figure of merit (HFFOM) were increased by 37.1% and 72.3%, respectively. Finally, the switching energy loss was decreased by 59.5% compared to the C-MOSFET.

3.3 kV 4H-SiC DMOSFET with a source-contacted dummy gate for high-frequency applications

In this paper, a 4H-SiC DMOSFET with a source-contacted dummy gate (DG-MOSFET) is proposed and analyzed through Sentaurus TCAD and PSIM simulations. The source-contacted MOS structure forms fewer depletion regions than the PN junction. Therefore, the overlapping region between the gate and the drain can be significantly reduced while limiting R ON degradation. As a result, the DG-MOSFET offers an improved high-frequency figure of merit (HF-FOM) over the conventional DMOSFET (C-MOSFET) and central-implant MOSFET (CI-MOSFET). The HF-FOM (R ON×Q GD) of the DG-MOSFET was improved by 59.2% and 22.2% compared with those of the C-MOSFET and CI-MOSFET, respectively. In a double-pulse test, the DG-MOSFET could save total power losses of 53.4% and 5.51%, respectively. Moreover, in a power circuit simulation, the switching power loss was reduced by 61.9% and 12.7% in a buck converter and 61% and 9.6% in a boost converter.

Numerical Simulation Analysis of Switching Characteristics in the Source-Trench MOSFET’s

In this paper, we compare the static and switching characteristics of the 4H-SiC conventional UMOSFET (C-UMOSFET), double trench MOSFET (DT-MOSFET) and source trench MOSFET (ST-MOSFET) through TCAD simulation. In particular, the effect of the trenched source region and the gate trench bottom P+ shielding region on the capacitance is analyzed, and the dynamic characteristics of the three structures are compared. The input capacitance is almost identical in all three structures. On the other hand, the reverse transfer capacitance of DT-MOSFET and ST-MOSFET is reduced by 44% and 24%, respectively, compared to C-UMOSFET. Since the reverse transfer capacitance of DT-MOSFET and ST-MOSFET is superior to that of C-UMOSFET, it improves high frequency figure of merit (HF-FOM: RON-SP × QGD). The HF-FOM of DT-MOSFET and ST-MOSFET is 289 mΩ∙nC, 224 mΩ∙nC, respectively, which is improved by 26% and 42% compared to C-UMOSFET. The switching speed of DT-MOSFET and ST-MOSFET are maintained at the same level as the C-UMOSFET. The switching energy loss and power loss of the DT-MOSFET and ST-MOSFET are slightly improved compared to C-UMOSFET.

A Novel SiC MOSFET Embedding Low Barrier Diode With Enhanced Third Quadrant and Switching Performance

A novel planar gate SiC MOSFET embedding low barrier diode (LBD-MOSFET) with improved third quadrant and switching performance is proposed and characterized in this letter. The LBD-MOSFET not only exhibits about 3 times lower diode turn on voltage than the body diode, but also successfully eliminates bipolar degradation phenomena. A low potential barrier for electrons transporting from JFET region to N+ source region is formed in LBD-MOSFET owing to the existence of the depletion charge in LBD base region. Meanwhile, the gate-to-drain charge ( ${Q}_{\text {gd}}){}$ and gate-to-drain capacitance ( ${C}_{\text {gd}}){}$ of LBD-MOSFET are significantly reduced by about $21\times $ and $15\times $ in comparison with the conventional MOSFET (C-MOSFET), due to the reduction of the overlapping area of the gate and drift region. Therefore, the obtained high frequency figures of merit (HF-FOM $1= {R}_{\text {on,sp}}\times {Q}_{\text {gd}}$ and HF-FOM $2= {R}_{\text {on,sp}}\times {C}_{\text {gd}}$ ) for the LBD-MOSFET are improved by about 13 times and 9 times compared with C-MOSFET. Furthermore, a compact potential barrier analytical model based on Poisson’s Law is developed to understand the origin of low potential barrier diode in SiC LBD-MOSFET. The overall enhanced performances suggest SiC LBD-MOSFET is an excellent choice for high frequency power electronic applications.

Comparative Study of SiC Planar MOSFETs With Different p-Body Designs

Silicon carbide MOSFET has been commercialized for many years. Its performance is still improving especially for high-frequency application. High-frequency figure-of-merit (HF-FOM) ${R}{ \mathrm{\scriptstyle ON}}^\ast {C}_{\text {GD}}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}}{}^\ast ~{Q}_{\text {GD}}$ were used for a comprehensive evaluation of the performance of MOSFET. In this article, SiC planar MOSFETs with different p-body designs were comparatively studied. A new planar MOSFET with buffered gate and thick central oxide gate structure (TCOX-MOS) was proposed to further improve the gate oxide electric field in OFF-state and HF-FOM. Compare to the conventional planar MOSFET (C-MOS), the maximum gate oxide electric field, gate–drain charge, and HF-FOM ( ${R}_{ \mathrm{\scriptscriptstyle ON}} {}^{\ast } {Q}_{\text {GD}}$ ) of TCOX-MOS are 32%, 83%, and 84% lower, respectively. Furthermore, TCOX-MOS shows less short-channel effects by better channel shielding structure. The results show that TCOX-MOS is a more attractive device structure.

2.3 kV 4H-SiC Accumulation-Channel Split-Gate Planar Power MOSFETs With Reduced Gate Charge

2.3 kV 4H-SiC split-gate (SG) planar accumulation-channel power MOSFETs have been successfully manufactured in a 6 inch commercial foundry with good parametric distributions. The measured electrical characteristics of these devices are compared with conventional ACCUFETs manufactured with the same cell-pitch and process to quantify the improved performance. The gate charge and high-frequency figures-of-merit (HF-FOM) of the 2.3 kV SG-MOSFETs were experimentally verified to be a factor of 1.8x better than that of the conventional MOSFETs with no difference in specific on-resistance.

Design and Optimization of 1.2-kV SiC Planar Inversion MOSFET Using Split Dummy Gate Concept for High-Frequency Applications

The gate architecture of a 1.2-kV SiC planar MOSFET is engineered to obtain the improved high-frequency figure of merit (HF-FOM) over the split-gate (SG) and planar-gate topology. In this article, we propose a device using the split dummy gate (SDG), which is in short with the source contact at zero potential. The device has a lower reverse transfer/feedback capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rss</sub> or C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) due to the formation of depletion width under SDG and lower gate-to-drain charge (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) due to reduced overlap with the substrate leading to excellent HF-FOM(R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> × C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> × Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ). The essential electrical characteristics (such as Ron,sp, breakdown voltage (BV), and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) remain almost similar compared to the device without the dummy gate. The obtained HF-FOM(R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> × Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) is 28.7× and 186× lower compared to the device with SG and planar-gate topology, respectively.Using calibrated Sentaurus TCAD simulations, the proposed SDG MOSFET has shown negligible Miller plateau (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ), reduced crowding of the electric field at the SG corner, and improved turn-on/off characteristics with a reduction in switching energies.

600 V 4H-SiC MOSFETs Fabricated in Commercial Foundry With Reduced Gate Oxide Thickness of 27 nm to Achieve IGBT-Compatible Gate Drive of 15 V

The measured electrical characteristics of 600 V planar-gate inversion-channel 4H-SiC power MOSFETs fabricated in a 6 inch commercial foundry with 27 nm gate oxide thickness are compared with 55 nm gate oxide devices. The High-Frequency Figures-of-Merit (HF-FOMs) of the SiC MOSFETs with 27 nm gate oxide were found to surpass that of commercially available 600 V P7 Si CoolMOS products for the first time. Statistical parametric distribution data and wafer-maps for the 27 nm devices are provided to demonstrate that excellent yield and uniformity can be achieved with the reduced gate oxide thickness. These devices can be operated at 15 V gate bias compatible with IGBT gate drivers.

1.2 kV SiC Trench-Gate MOSFETs with Dual Shielding Regions

This paper presents a study of the 1.2kV UMOSFETs with dual shielding regions. Numerical simulations demonstrate the importance of including dual shielding regions to achieve low specific on-resistance and high breakdown voltage. The optimized structure has a low specific on-resistance (Ron,sp) of 2.19 mΩ-cm2, high breakdown voltage of 1470 V, low specific reverse transfer capacitance (Cgd,sp) of 17 pF/cm2 and excellent high-frequency figure-of-merit (HF-FOM) of 37 fs.

Analysis and Experimental Quantification of 1.2-kV 4H-SiC Split-Gate Octagonal MOSFET

A1.2-kV rated 4H-SiC split-gate octagonal cell MOSFET (SG-OCTFET) is proposed and successfully fabricated in a 6-in foundry for the first time. The measured results quantify the benefits of the SG-OCTFET structure: improvement in high-frequency figures of merit (HF-FOM) (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> × C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) by 1.8×, HF-FOM (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> × Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) by 1.6×, and FOM (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">iss</sub> /C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) by 1.6× compared with the optimized compact OCTFET design due to the reduced gate-to-drain overlap area. An important conclusion of this letter is that unlike commercially available 1.2-kV SiC power MOSFETs with linear cell topology, the 1.2-kV SG-OCTFET design can outperform commercially available 600-V Si super-junction devices.

Impact of PZT gate‐stack induced negative capacitance on analogue/RF figures‐of‐merits of electrostatically‐doped ferroelectric Schottky‐barrier tunnel FET

In this work, the authors investigate analogue and radio-frequency (RF) figures-of-merit (FOM) of electrostatically-doped ferroelectric Schottky-barrier tunnel field-effect transistor (FET) (ED-FE-SBTFET) by deploying PZT (lead zirconium titanate) gate stack and dopant-free technology. This PZT gate stack results in negative capacitance behaviour as a result of the positive feedback among the electric dipoles within it. It realises an intrinsic amplifier to amplify the surface potential due to the applied gate bias and enhances the gate controllability significantly. As a result it facilitates lower ambipolar current, considerably high drive current and faster switching transitions. As the structure is realised by using dopant-free technique it ensures simplified fabrication process as it avoids the need of ion implantation and thermal annealing, reduces thermal budget. Here, a detailed comparison is carried-out between charge plasma Schottky-barrier tunnel FET and ED-FE-TFET for their high frequency FOMs such as cut-off frequency (), gain bandwidth product, transconductance generation factor and so on. The higher ratio of ED-FE-SBTFET reduces the static and dynamic both types of powers in digital circuits, while higher ratio ensures lower bias power of an amplifier.