1.2 kV 4H–SiC Super Junction UMOSFET with a Low-K dielectric pillar

Abstract

A 1.2 kV 4H–SiC Super Junction (SJ) UMOSFET with a Low-K (LK) dielectric pillar below the trench gate (LK-SJ-UMOSFET) is proposed in this paper. The device features a P-type doping pillar (P-pillar) at the source-side and a deep LK trench beneath the gate. Firstly, the gate-to-drain capacitance (Cgd) is greatly decreased by the LK dielectric pillar. Secondly, both the LK dielectric and the P-pillar cause the assistant depletion of the N-type doping pillar (N-pillar), resulting in an increased N-pillar doping concentration and a decreased specific on-resistance (Ron,sp). The proposed LK-SJ-UMOSFET is demonstrated to have a low high frequency Figure-Of-Merit (HF-FOM) Ron×Cgd = 28.628 mΩ pF and Ron × Qgd = 29.274 mΩ nC. The HF-FOM of the proposed 4H–SiC LK-SJ-UMOSFET is lower than that of the other 4H–SiC UMOSFET in recent simulation studies and reports.