High Clock Frequency Research Articles

Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for Spin Hall Effect MRAM Device

In this paper, various energy-efficient write schemes are proposed for switching operation of spin hall effect (SHE)-based magnetic tunnel junctions (MTJs). A transmission gate (TG)-based write scheme is proposed, which provides a symmetric and energy-efficient switching behavior. We have modeled an SHE-MTJ using precise physics equations, and then leveraged the model in SPICE circuit simulator to verify the functionality of our designs. Simulation results show the TG-based write scheme advantages in terms of device count and switching energy. In particular, it can operate at 12% higher clock frequency while realizing at least 13% reduction in energy consumption compared to the most energy-efficient write circuits. We have analyzed the performance of the implemented write circuits in presence of process variation (PV) in the transistors’ threshold voltage and SHE-MTJ dimensions. Results show that the proposed TG-based design is the second most PV-resilient write circuit scheme for SHE-MTJs among the implemented designs. Finally, we have proposed the 1TG-1T-1R SHE-based magnetic random access memory (MRAM) bit cell based on the TG-based write circuit. Comparisons with several of the most energy-efficient and variation-resilient SHE-MRAM cells indicate that 1TG-1T-1R delivers reduced energy consumption with 43.9% and 10.7% energy-delay product improvement, while incurring low area overhead.

A Generic Reconfigurable Mixed Time and Frequency Domain QAM Transmitter with Forward Error Correction

In the past three decades, Field Programmable Gate Arrays (FPGAs) have emerged to be the backbone of digital signal processing, especially in high-speed communication systems. However, today, these devices are clocked below 1GHz and improvement in performance stays a big challenge on all abstraction layers, right from system architecture down to physical technology. Far and wide, myriad number of researches are done on methodologies and techniques which can deliver higher throughput with lower operating frequencies. Towards this projected objective, in this paper an efficient modulation technique like Quadrature Amplitude Modulation (QAM) along with mixed time and frequency domain approach and Forward Error Correction (FEC) technique have been utilized to employ a generic scalable FPGA based QAM transmitter with filter parallelization being executed in mixed domain. The system developed in this paper achieves an effective throughput of 12.8Gb/s for 256-QAM with 16 parallel inputs having an operating frequency of 201.25MHz, while a 18.7Gb/s effective throughput is realized with 32 parallel inputs at 146MHz. Thereby, it paves down a promising methodology for applications where having higher clock frequencies is a hard limit.

Effects of Adaptive DC Biasing on Operational Margins in ERSFQ Circuits

Energy efficiency has become the primary parameter for the design of next-generation single flux quantum (SFQ) circuits. This, however, needs to be balanced with optimization for clock speed and bias margins. Here, we experimentally study the tradeoff between circuit activity, energy efficiency, and bias margins for zero static power dissipation ERSFQ circuits. For ERSFQ, dc power is provided by a Josephson transmission line (JTL) called a “feeding” JTL (FJTL), which acts as a voltage source. As a test case, shift registers and multiplexers were laid out and fabricated in both HYPRES's and MIT-LL's 10-kA/cm2 fabrication processes and tested at low (∼kHz) and high (∼GHz) clock frequencies. The functional bias margins for these circuits increase significantly from +/–4% to over +/–19% when the Josephson junction count in the FJTL was increased to ∼30% of total dc bias current of the circuit. Based on our findings, we discuss how to optimize ERSFQ circuits for both energy efficiency and dc bias margins.

Area-Time Efficient Architecture of FFT-Based Montgomery Multiplication

The modular multiplication operation is the most time-consuming operation for number-theoretic cryptographic algorithms involving large integers, such as RSA and Diffie-Hellman. Implementations reveal that more than 75 percent of the time is spent in the modular multiplication function within the RSA for more than 1,024-bit moduli. There are fast multiplier architectures to minimize the delay and increase the throughput using parallelism and pipelining. However such designs are large in terms of area and low in efficiency. In this paper, we integrate the fast Fourier transform (FFT) method into the McLaughlin’s framework, and present an improved FFT-based Montgomery modular multiplication (MMM) algorithm achieving high area-time efficiency. Compared to the previous FFT-based designs, we inhibit the zero-padding operation by computing the modular multiplication steps directly using cyclic and nega-cyclic convolutions. Thus, we reduce the convolution length by half. Furthermore, supported by the number-theoretic weighted transform, the FFT algorithm is used to provide fast convolution computation. We also introduce a general method for efficient parameter selection for the proposed algorithm. Architectures with single and double butterfly structures are designed obtaining low area-latency solutions, which we implemented on Xilinx Virtex-6 FPGAs. The results show that our work offers a better area-latency efficiency compared to the state-of-the-art FFT-based MMM architectures from and above 1,024-bit operand sizes. We have obtained area-latency efficiency improvements up to 50.9 percent for 1,024-bit, 41.9 percent for 2,048-bit, 37.8 percent for 4,096-bit and 103.2 percent for 7,680-bit operands. Furthermore, the operating latency is also outperformed with high clock frequency for length-64 transform and above.

Study of a M/T Method of Variable Sampling Period and its Implementation Based on STM32 MPUs

In this paper, a new M/T method of variable sampling period is introduced for speed measurements by optical incremental encoders. In this method, we estimated the number of encoder pulses to count in next counting interval at the end of every sample period, so the sampling intervals were variable. Both encoder pulse and high frequency clock pulse were counted in the variable intervals and the counting of clock pulses begins and ends at the exact rising age of the encoder pulse. Through this method, the error is only one clock pulse which is much shorter than encoder pulse, which guarantees a more accurate speed measurement and rapid response of motor system.

A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC

Generation of low jitter, high frequency clock from a low frequency reference clock using classical analog phaselocked loops (PLLs) requires large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. Specifically, their deterministic jitter (DJ), which is proportional to the loop update rate becomes prohibitively large at low reference clock frequencies. We propose a scrambling TDC (STDC) to improve DJ performance and a cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage to achieve low random jitter in a power efficient manner. Fabricated in a 90 nm CMOS process, the prototype frequency synthesizer consumes 4.76 mW power from a 1.0 V supply and generates 160 MHz and 2.56 GHz output clocks from a 1.25 MHz crystal reference frequency. The long-term absolute jitter of the 160 MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 psrms and 4.18 psrms, while the peak-to-peak jitter are 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz.

ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing

Scalable Network-on-Chip (NoC) architectures should achieve high-throughput and low-latency operation without exceeding the stringent area/energy constraints of modern Systems-on-Chip (SoC), even when operating under a high clock frequency. Such requirements directly impact the NoC routers and interfaces comprising the NoC architecture. This paper focuses on the micro-architecture of NoC routers and presents ShortPath , a pipelined router architecture that can achieve high-speed implementations by parallelizing as much as possible – and without resorting to speculation – the allocation steps involved in the operation of a VC-based router. Most importantly, ShortPath is augmented with a fine-grained pipeline bypassing mechanism, which skips all stages without contention and “fast-forwards” the flits to the first point of contention. Pipeline bypassing in ShortPath is always productive, and even if a flit loses in arbitration, it does not repeat any of the stages already bypassed. Extensive network simulations and hardware analysis – using standard-cell-based synthesis and placed-and-routed layout – corroborate the efficiency of ShortPath, in terms of both network performance and hardware complexity, as compared to the most relevant current state-of-the-art architecture.

An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box

In this paper an efficient structural architecture is proposed for AES Encryption process to achieve high throughput with less device utilization. Breakable and controllable structures for main AES blocks at the gate level are designed and used here. The control unit using high speed combinational logic circuit is designed to control the AES structural architecture. Modified MUX based S-Box is introduced in AES instead of S-Box to reduce the area without affecting the throughput. In addition Encryption process Mix-columns transformation is modified to reduce the hardware complexity. The five stage subpipelining is introduced in AES MUX based S-Box with six pipelining stages in AES encryption process to increase throughput further. The aim of this work is to investigate both the existing and new architectures. The modified MUX based S-Box for Rijndael algorithm has been used in the 128-bit AES encryption process. The role of five stage sub-pipelined MUX based S-Box of 128-bit pipelined AES is to reduce the critical path delay to minimum for achieving high clock frequency. The rows of multiplexer in AES architecture were used for the breaking and controlling of the design. The modified 128-bit encryption was implemented on Virtex-4, Virtex-5, and Spartan 3 FPGA Devices. The results of the proposed architecture are analysed, throughput and area for the implemented design are calculated. The calculated results are compared with other architecture (Liberatori et al. in 3rd southern proceedings of the IEEE conference on programmable logic, SPL'07, pp 195---198, 2007; Farashahi et al. in Microelectron J 45:1014---1025, 2014; Good and Benaissa in IET Inf Secur 1(1):1---10, 2007; Sireesha and Madhava Rao in Int J Sci Res 3(9):1---5, 2013; Gielata et al. in Proceedings of the international conference on signals and electronic systems (ICSES), pp 137---140, 2008; El Adib and Raissouni in Int J Inf Netw Secur 1(2):1---10, 2012; Good and Benaissa in Lecture Notes Computer Science, vol 3659, pp 427---440, 2005). From the results it is obtained that the proposed architecture gives 58 % improvement with 1.08 % reduction in area.

A High-Throughput and Multi-Parallel VLSI Architecture for HEVC Deblocking Filter

This paper presents a high-throughput and multi-parallel VLSI hardware architecture for the deblocking filter in the HEVC video coding standard. First, an implementation-friendly and fast boundary judgment method is proposed to avoid using the original recursion loop approach. Then a dedicated parallel VLSI architecture composed of four parallel filtering cores is presented based on the proposed boundary judgment method. With the parallel luma/chroma filtering and parallel vertical/horizontal edges filtering order, the proposed VLSI architecture can process filtering operations for one largest coding unit (LCU) with less filtering cycles than other conventional approaches. Furthermore, filtering efficiency is improved due to a novel ping-pang buffer architecture and the on-chip single-port SRAM with dedicated data arrangement in the memory modules. Experimental results demonstrate that the proposed deblocking filter architecture improves the performance by 28–89% at the expense of the slightly increased gate count compared to the previously known architecture in HEVC. The proposed architecture can reach a high operating clock frequency of 278 MHz with TSMC 90 nm library and meet the real time requirement of the deblocking filter for 8 K × 4 K video format at 123 frame/s.

On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines

Voltage droop is a major reliability concern in nano-scale very large-scale integration designs. Undesirable voltage droop is often a result of excessive IR drop. On the other hand, Ldi/dt -induced droop occurs when logic gates in the circuit draw high-switching current from the on-chip power supply network, and this problem is exacerbated at high-clock frequencies and smaller technology nodes. A consequence of voltage droop is usually an increase in path delays and the occurrence of intermittent faults during circuit operation. The addition of conservative timing margins, also known as guardbands, is a common practice to tackle the problem of voltage droop. However, such static and pessimistic guardbands, which are calculated at design time based on worst-case conditions, lead to significant performance loss. Dynamic frequency scaling is an alternative approach that enables the dynamic adjustment of clock frequency based on the actual voltage droop seen during runtime. For dynamic voltage-frequency to be effective, accurate and real-time prediction of voltage droop is essential. We propose a support-vector machine (SVM)-based regression method to predict voltage droop due to pattern-dependent IR drop based on inputs to the chip at runtime. Moreover, we reduce the amount of data needed for accurate prediction by using correlation-based feature selection. Several benchmarks from ITC’99 and International Work on Logic and Synthesis’05 highlight the effectiveness of the proposed method in terms of delay-prediction accuracy. Since real-time droop prediction requires hardware implementation of the predictor, we present the hardware design and synthesis results to demonstrate that the hardware overhead for the SVM predictor is negligible for large circuits.

All-optical high frequency clock pulse generator using the feedback mechanism in Toffoli gate with Kerr material

Optics is found as a potential information carrier in information processing because of its superfast speed of operation. For such operations, optical Kerr materials are highly sensitive for use as optical switches. In this paper, the authors for thr first time propose a new scheme of generation of an all-optical pulse train generator using the feedback mechanism in an all-optical Toffoli gate with Kerr material.

Design and simulation of a standing wave oscillator based PLL

A standing wave oscillator (SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor (IMOS) field-effect transistor as a varactor, and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO, a new phase locked loop (PLL) architecture is presented. This PLL can be used not only as a clock source, but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P9M complementary metal-oxide-semiconductor (CMOS) technology, and can be used directly in a high performance multi-core microprocessor.

Energy-Efficient Nonvolatile Reconfigurable Logic using Spin Hall Effect-based Lookup Tables

In this paper, we leverage magnetic tunnel junction (MTJ) devices to design an energy-efficient nonvolatile lookup table (LUT), which utilizes a spin Hall effect (SHE) assisted switching approach for MTJ storage cells. SHE–MTJ characteristics are modeled in Verilog-A based on precise physical equations. Functionality of the proposed SHE–MTJ-based LUT is validated using SPICE simulation. Our proposed SHE—MTJ-based LUT (SHE–LUT) is compared with the most energy-efficient MTJ-based LUT circuits. The obtained results show more than 6%, 37%, and 67% improvement over three previous MTJ-based designs in term of read energy consumption. Moreover, the reconfiguration delay and energy of the proposed design is compared with that of the MTJ-based LUTs which utilize the spin transfer torque (STT) switching approach for reconfiguration. The results exhibit that SHE–LUT can operate at 78% higher clock frequency while achieving at least 21% improvement in terms of reconfiguration energy consumption. The operation-specific clocking mechanisms for managing the SHE–LUT operations are introduced along with detailed analyses concerning tradeoffs. Results are extended to design a 6-input fracturable LUT using SHE–MTJs.

Optimization of Thermal Aware VLSI Non-Slicing Floorplanning Using Hybrid Particle Swarm Optimization Algorithm-Harmony Search Algorithm

Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimating the positions and shapes of the modules. A high packing density, small feature size and high clock frequency make the Integrated Circuit (IC) to dissipate large amount of heat. So, in this paper, a methodology is presented to distribute the temperature of the module on the layout while simultaneously optimizing the total area and wirelength by using a hybrid Particle Swarm Optimization-Harmony Search (HPSOHS) algorithm. This hybrid algorithm employs diversification technique (PSO) to obtain global optima and intensification strategy (HS) to achieve the best solution at the local level and Modified Corner List algorithm (MCL) for floorplan representation. A thermal modelling tool called hotspot tool is integrated with the proposed algorithm to obtain the temperature at the block level. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The results obtained are compared with the solutions derived from other stochastic algorithms and the proposed algorithm provides better solution.

DLL-based 4-phase duty-cycle and phase correction circuit for high frequency clock tree

In high-speed data transmission applications such as double data rate memory and double sampling ADCs, clock generation and distribution circuits must provide the clocks with precise duty cycle of 50% and sufficient timing margin. The proposed DLL-based 4-phase duty-cycle and phase correction circuit, consisting of delay-locked loop (DLL) and 45 phase clock generator (SR latch) corrects distorted duty-cycle clock to 50% duty-cycle. The distorted duty-cycle input clock passes through the DLL. After the DLL is locked, the delay of delay line is identical to the period of input clock. Lastly, 4-phase, 50% duty-cycle clocks is generated from the combination of rising edges of signals at each 1/4 points of delay line. The proposed circuit is implemented in 65nm CMOS. The simulation results shows that the frequency range of the proposed circuits is 550-1600MHz, the maximum duty cycle error of the output clock can be less than 1% with the input duty cycle correction ranging from 25% to 80%. The phase difference with the 4-phase output clock is 250±3ps at a frequency of 1GHz. The measured power dissipation is 4.3mW.

KM3NeT Neutrino Telescope 1-ns Resolution Time To Digital Converters

The KM3NeT collaboration aims the construction of a multi-km3 high- energy neutrino telescope in the Mediterranean sea consisting of thousands of glass spheres, each of them containing 31 photomultiplier of small photocathode area. The main digitization system is composed by 31 Time to Digital Converter channels with 1-ns resolution embedded in a Field Programmable Gate Array. An architecture with low resource occupancy has been chosen allowing the implementation of other instrumentation, communication and synchronization systems on the same device. The 4-oversampling technique with two high frequency clocks working in opposed phases has been used together with an asymmetric FIFO memory. In the present article the architecture and the first results obtained with the Time to Digital Converters are presented.

Smart Capture Modules for Direct Sensor-to-FPGA Interfaces.

Direct sensor–digital device interfaces measure time dependent variables of simple circuits to implement analog-to-digital conversion. Field Programmable Gate Arrays (FPGAs) are devices whose hardware can be reconfigured to work in parallel. They usually do not have analog-to-digital converters, but have many general purpose I/O pins. Therefore, direct sensor-FPGA connection is a good choice in complex systems with many sensors because several capture modules can be implemented to perform parallel analog data acquisition. The possibility to work in parallel and with high frequency clock signals improves the bandwidth compared to sequential devices such as conventional microcontrollers. The price to pay is usually the resolution of measurements. This paper proposes capture modules implemented in an FPGA which are able to perform smart acquisition that filter noise and achieve high precision. A calibration technique is also proposed to improve accuracy. Resolutions of 12 effective number of bits are obtained for the reading of resistors in the range of an example piezoresistive tactile sensor.

Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations

Dynamic flip-flop (FF) conversion is a method of time borrowing (TB) for improving the performance of digital systems prone to variations. The first type of this method (Type A), which was previously presented, suffers from a large inefficient transparency window. In this brief, we present an improved structure for this method (Type B) that mitigates this problem by automatically closing the window after the arrival of late data at timing critical FFs. This method was compared with soft edge FF and dynamic clock stretching through simulations on different ITC’99 benchmarks. We defined a parameter called improvement efficiency, which is the ratio of the timing yield improvement to the power overhead of TB. According to the simulation results, the efficiency of Type A is on average 269% more than the best results of other methods when considering only the setup time violations. But, when taking both the setup time and the hold time violations into account, Type B is on average 46% more efficient than the best results of other methods. The simulations also show that the yield improvement of this method increases in higher clock frequencies and it remains the most efficient method when reducing the voltage down to near-threshold region.

보정기법 없이 채널 간 오프셋 부정합을 최소화한 2x Interleaved 10비트 120MS/s 파이프라인 SAR ADC

본 논문에서는 특별한 보정기법 없이 채널 간 오프셋 부정합 문제를 최소화한 2채널 time-interleaved (T-I ) 구조의 10비트 120MS/s 파이프라인 SAR ADC를 제안한다. 제안하는 ADC는 4비트-7비트 기반의 2단 파이프라인 구조 및 2채널 T-I 구조를 동시에 적용하여 전력소모를 최소화하면서 빠른 변환속도를 구현하였다. 채널 간에 비교기 및 잔류전압 증폭기 등 아날로그 회로를 공유함으로써 일반적인 T-I 구조에서 선형성을 제한하는 채널 간 오프셋 부정합 문제를 추가적인 보정기법 없이 최소화할 뿐만 아니라 전력소모 및 면적을 감소시켰다. 고속 동작을 위해 SAR 로직에는 범용 D 플립플롭 대신 TSPC D 플립플롭을 사용하여 SAR 로직에서의 지연시간을 최소화하면서 사용되는 트랜지스터의 수도 절반 수준으로 줄임으로써 전력소모 및 면적을 최소화하였다. 한편 제안하는 ADC는 기준전압 구동회로를 3가지로 분리하여, 4비트 및 7비트 기반의 SAR 동작, 잔류전압 증폭 등 서로 다른 스위칭 동작으로 인해 발생하는 기준전압 간섭 및 채널 간 이득 부정합 문제를 최소화하였다. 시제품 ADC는 고속 SAR 동작을 위한 높은 주파수의 클록을 온-칩 클록 생성회로를 통해 생성하였으며, 외부에서 duty cycle을 조절할 수 있도록 설계하였다. 시제품 ADC는 45nm CMOS 공정으로 제작되었으며, 측정된 DNL 및 INL은 10비트 해상도에서 각각 최대 0.69LSB, 0.77LSB이며, 120MS/s 동작속도에서 동적 성능은 최대 50.9dB의 SNDR 및 59.7dB의 SFDR을 보여준다. 시제품 ADC의 칩 면적은 0.36mm2이며, 1.1V 전원전압에서 8.8mW의 전력을 소모한다.

Revisiting Clustered Microarchitecture for Future Superscalar Cores

During the past 10 years, the clock frequency of high-end superscalar processors has not increased. Performance keeps growing mainly by integrating more cores on the same chip and by introducing new instruction set extensions. However, this benefits only some applications and requires rewriting and/or recompiling these applications. A more general way to accelerate applications is to increase the IPC, the number of instructions executed per cycle. Although the focus of academic microarchitecture research moved away from IPC techniques, the IPC of commercial processors was continuously improved during these years. We argue that some of the benefits of technology scaling should be used to raise the IPC of future superscalar cores further. Starting from microarchitecture parameters similar to recent commercial high-end cores, we show that an effective way to increase the IPC is to allow the out-of-order engine to issue more micro-ops per cycle. But this must be done without impacting the clock cycle. We propose combining two techniques: clustering and register write specialization. Past research on clustered microarchitectures focused on narrow issue clusters, as the emphasis at that time was on allowing high clock frequencies. Instead, in this study, we consider wide issue clusters, with the goal of increasing the IPC under a constant clock frequency. We show that on a wide issue dual cluster, a very simple steering policy that sends 64 consecutive instructions to the same cluster, the next 64 instructions to the other cluster, and so forth, permits tolerating an intercluster delay of three cycles. We also propose a method for decreasing the energy cost of sending results from one cluster to the other cluster.