Abstract
In high-speed data transmission applications such as double data rate memory and double sampling ADCs, clock generation and distribution circuits must provide the clocks with precise duty cycle of 50% and sufficient timing margin. The proposed DLL-based 4-phase duty-cycle and phase correction circuit, consisting of delay-locked loop (DLL) and 45 phase clock generator (SR latch) corrects distorted duty-cycle clock to 50% duty-cycle. The distorted duty-cycle input clock passes through the DLL. After the DLL is locked, the delay of delay line is identical to the period of input clock. Lastly, 4-phase, 50% duty-cycle clocks is generated from the combination of rising edges of signals at each 1/4 points of delay line. The proposed circuit is implemented in 65nm CMOS. The simulation results shows that the frequency range of the proposed circuits is 550-1600MHz, the maximum duty cycle error of the output clock can be less than 1% with the input duty cycle correction ranging from 25% to 80%. The phase difference with the 4-phase output clock is 250±3ps at a frequency of 1GHz. The measured power dissipation is 4.3mW.
Highlights
Game consoles or high-performance TVs are need to high frequency bandwidth DRAM for improving the processing speed
The to-digital converter (TDC)-based duty-cycle correction (DCC) [6]-[8] quantize a period of input clock into a digital code, and generate halfcycle delay time using this digital code
The delay-locked loop (DLL) is comprised of a phase and frequency detector (PFD), a voltage controlled delay line (VCDL), a charge pump (CP) and a loop filter (LF)
Summary
Game consoles or high-performance TVs are need to high frequency bandwidth DRAM for improving the processing speed. There are some unwanted factors such as jitter, skew, and PVT variations that make distortion of duty-cycle and/or a phase-skew between multi-phase clocks. The TDC-based DCCs [6]-[8] quantize a period of input clock into a digital code, and generate halfcycle delay time using this digital code. The DCCs can make a 50% duty-cycle output clock, phases of the input and output clock are misaligned To solve this problem, the DCC with DLL is proposed [9]. A DLL-based 4-phase DCC and PC circuit for multi-phase interface is proposed. This scheme uses DLL to detecting the input clock period. Due to the using of analog type DLL, proposed design can achieve relatively precise duty-cycle correction and phase correction.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have