HEMT Research Articles

Study of the spatial measurement of electron density in the EAST discharge using a multichannel terahertz solid-source interferometer

Abstract A vertical single-channel 0.65-THz solid-source interferometer (SSI) has been established at Experimental Advanced Superconducting Tokamak (EAST) for real-time electron density measurements and feedback. A line array detection scheme was proposed and successfully deployed on EAST to enhance the spatial resolution of the SSI system. The scheme utilizes an AlGaN/GaN line array High Electron Mobility Transistor (HEMT) detector, and three channels of line-integrated electron density signals were measured. A representative density measurement was conducted with an Intermediate Frequency (IF) of 850 kHz in a discharge with a current (Ip) of 400 kA and Electron Cyclotron Resonance Heating Power (PECRH) of 1.1 MW on EAST. Additionally, the detection of density perturbations by the SSI system during plasma discharges demonstrates its capability to study small-scale spatial magnetohydrodynamic (MHD) phenomena. Further optical refinements and the development of advanced data processing algorithms are anticipated to enhance the measurement accuracy and overall performance of the line array detection scheme.

Hetero dielectric based dual material gate AlGaN channel MISHEMT for enhanced electrical characteristics

Herein, we report an AlGaN channel metal insulator semiconductor high electron mobility transistor (MISHEMT) in dual material gate (DMG) architecture with two different dielectrics as gate insulator for enhancing the DC performance of the device. The use of a high-k dielectric material as gate insulator below gate metal 1 and a low-k dielectric below gate metal 2 results in significant threshold voltage variation along the channel. This contributes to improved average carrier velocity which in turn results in better current drive. The proposed device exhibits a peak current of 162 mA/mm at zero gate bias, whereas, the DMG and single material gate (SMG) AlGaN channel HEMTs offer currents of 137 mA/mm and 125 mA/mm respectively. The peak transconductances are about 24.66 mS/mm, 23.68 mS/mm and 22.71 mS/mm respectively for the proposed device, DMG and SMG HEMTs. The proposed device reduces the OFF current by an order of 106 compared to that of DMG HEMT.

253 GHz fT Graded‐Channel AlGaN/GaN High‐Electron‐Mobility Transistors with New Cliff Barrier for Millimeter Wave High‐Frequency Applications

In this research work, a graded‐channel AlGaN/GaN high‐electron‐mobility transistor (HEMT) featuring a cliff AlGaN barrier with a gate length of 60 nm is investigated. The inclusion of a foot cliff barrier layer confines the 3DEG distribution, thereby reducing electron scattering and potentially improving carrier mobility. The cliff‐graded‐channel device shows a peak cutoff frequency fT of 253 GHz and power‐added efficiency of 68% at 30 GHz, which represents a significant 60% improvement in comparison with conventional graded‐channel devices. These results clearly indicate that the graded‐channel AlGaN/GaN HEMT with a new cliff barrier design has great potential for mmW applications.

Enhancing power density in D-mode GaN HEMT direct-current triboelectric nanogenerators through ICP-etched surface engineering

In the evolving landscape of energy harvesting, the refinement of friction properties in metal-semiconductor direct current triboelectric nanogenerators (MSDC TENGs) has garnered significant attention. While prior research predominantly concentrated on achieving superior performance in MSDC TENGs through material manipulation, structural adjustments, and friction mode optimization, there has been a noticeable dearth of investigations into surface engineering or modification of semiconductor materials. In this paper, the surface patterning of depletion mode GaN-based high electron mobility transistor (D-GaN HEMT) as friction materials is done by inductively coupled plasma etching method, involving both mechanism analysis and experimental exploration. Through modulation of etching depth and pattern density, a systematically arranged diamond pattern is created on the surface, augmenting surface roughness and charge density. Consequently, the surface-patterned D-GaN HEMT TENG achieves a maximum short-circuit current of 60 µA and a peak power density of 4.05 W/m², which is about 2.8 times greater than the pristine D-GaN HEMT TENG. Furthermore, the power supply capabilities of the surface-patterned D-GaN HEMT TENG are scrutinized, revealing its proficiency in capacitive charging and discharging. The successful activation of a deep ultraviolet LED underscores its potential applications in ultraviolet disinfection. This research holds substantial significance in optimizing the power generation efficiency and performance of MSDC TENGs employing D-GaN HEMT.

Ultrafast carrier dynamics in InGaN quantum well channel based high electron mobility transistor structure

Ultrafast pump probe measurements on InGaN quantum well (QW) channel based high electron mobility transistor (HEMT) structure enable a direct measurement of the transit/capture time of electrons from GaN buffer layer to InGaN channel layer. Carrier capture time of 75 ± 10 fs is measured and the same is found to be independent of excitation wavelength. However, the capture process is delayed by 160 ± 5 fs when carriers are excited in GaN buffer layer. This happens due to the inclusion of transit time of carriers in GaN layer. It is confirmed by varying the wavelength of excitation where a delay in carrier transit is seen at longer wavelength. It is also seen that the strength of a feature associated with the carriers excited in GaN layer and captured by InGaN QW channel layer mimics the absorption spectrum of GaN, which also confirms that the delay in capture process is caused by the carriers excited in GaN layer. It is found that the capture process can be delayed even up to 240 ± 5 fs when the pump wavelength is kept at 390 nm. It is explained by considering the absorption in a deeper part of GaN layer and via the shallow defect states. Further, it is found that the localization of carriers in InGaN QW channel layer occurs at the time scales of 85 ± 10 fs. The transit/capture/localization time parameters reported in this work provide a crucial set of information, which is essential for modulating the carrier dynamics in InGaN/GaN based HEMTs and other high speed optoelectronic devices.

Effect of temperature on the performance of ScAlN/GaN high-electron mobility transistor

We have studied the operation of the ScAlN/GaN high-electron mobility transistor (HEMT) at high temperatures up to 700 K (423 °C). A maximum drain current density of ∼2 A/mm and an on-resistance of ∼1.5 Ω·mm was measured at room temperature (RT). The epi-structure exhibited a very high two-dimensional electron gas (2DEG) density of 6 × 1013 cm−2 at RT using Hall measurement. The Sc0.15Al0.85N barrier, nearly lattice matched to the GaN channel, showed a drain current reduction of ∼50% at 700 K. The decrease in 2DEG mobility, which leads to an increase in sheet resistance, is mostly responsible for this reduction in drain current. However, an excellent electrostatic control was achieved at 700 K with the drain current value exceeding 1 A/mm, which is 2 times higher compared to that of AlGaN/GaN HEMTs reported previously. These results indicate that ScAlN/GaN HEMTs are a promising candidate for high-temperature and high-power electronic applications.

A Review of Ku-Band GaN HEMT Power Amplifiers Development.

This review article investigates the current status and advances in Ku-band gallium nitride (GaN) high-electron mobility transistor (HEMT) high-power amplifiers (HPAs), which are critical for satellite communications, unmanned aerial vehicle (UAV) systems, and military radar applications. The demand for high-frequency, high-power amplifiers is growing, driven by the global expansion of high-speed data communication and enhanced national security requirements. First, we compare the main GaN HEMT process technologies employed in Ku-band HPA development, categorizing the HPAs into monolithic microwave integrated circuits (MMICs) and internally matched power amplifier modules (IM-PAMs) and examining their respective characteristics. Then, by reviewing the literature, we explore design topologies, major issues like oscillation prevention and bias circuits, and heat sink technologies for thermal management. Our findings indicate that silicon carbide (SiC) substrates with gate lengths of 0.25 μm and 0.15 μm are predominantly used, with ongoing developments enabling MMICs and IM-PAMs to achieve up to 100 W output power and 30% power-added efficiency. Notably, the performance of MMIC power amplifiers is advancing more rapidly than that of IM-PAMs, highlighting MMICs as a promising direction for achieving higher efficiency and integration in future Ku-band applications. This paper can provide insights into the overall key technologies for Ku-band GaN HPA design and future development directions.

Polycrystalline Diamond Film Growth on Gallium Nitride with Low Boundary Thermal Resistance

As the demand for high-frequency and high-power electronic devices has increased, gallium nitride (GaN), particularly in the context of high-electron mobility transistors (HEMTs), has attracted considerable attention. However, the ‘self-heating effect’ of GaN HEMTs represents a significant limitation regarding both performance and reliability. Diamond, renowned for its exceptional thermal conductivity, represents an optimal material for thermal management in HEMTs. This paper proposes a novel method for directly depositing diamond films onto N-polar GaN (NP-GaN) epitaxial layers. This eliminates the complexities of the traditional diamond growth process and the need for temporary substrate steps. Given the relative lag in the development of N-polar material growth technologies, which are marked by surface roughness issues, and the recognition that the thermal boundary resistance (TBRGaN/diamond) represents a critical factor constraining efficient heat transfer, our study has introduced a series of optimizations to enhance the quality of the diamond nucleation layer while ensuring that the integrity of the GaN buffer layer remains intact. Moreover, chemical mechanical polishing (CMP) technology was employed to effectively reduce the surface roughness of the NP-GaN base, thereby providing a more favorable foundation for diamond growth. The optimization trends observed in the thermal performance test results are encouraging. Integrating diamond films onto highly smooth NP-GaN epitaxial layers demonstrates a reduction in TBRGaN/diamond compared to that of diamond layers deposited onto NP-GaN with higher surface roughness that had undergone no prior process treatment.

Suppression of Short-Channel Effects in AlGaN/GaN HEMTs Using SiNx Stress-Engineered Technique.

In this work, we present the novel application of SiNx stress-engineering techniques for the suppression of short-channel effects in AlGaN/GaN high-electron-mobility transistors (HEMTs), accompanied by a comprehensive analysis of the underlying mechanisms. The compressive stress SiNx passivation significantly enhances the barrier height at the heterojunction beneath the gate, maintaining it above the quasi-Fermi level even as Vds rises to 20 V. As a result, in GaN devices with a gate length of 160 nm, the devices with compressive stress SiNx passivation exhibit significantly lower drain-induced barrier lowering (DIBL) factors of 2.25 mV/V, 2.56 mV/V, 4.71 mV/V, and 3.84 mV/V corresponding to drain bias voltages of 5 V, 10 V, 15 V, and 20 V, respectively. Furthermore, as Vds increases, there is an insignificant degradation in transconductance, subthreshold swing, leakage current, or output conductance. In contrast, the devices with stress-free passivation show relatively higher DIBL factors (greater than 20 mV/V) and substantial degradation in pinch-off performance and output characteristics. These results demonstrate that the SiNx stress-engineering technique is an attractive technique to facilitate high-performance and high-reliability GaN-based HEMTs for radio frequency (RF) electronics applications.

A computational approach to optimize the linearity in dual-gate InAlGaN/AlN/GaN HEMTs

Abstract This paper investigates the effect of the proposed dual gate structures in enhancing the linearity of InAlGaN/AlN/GaN high-electron-mobility transistors (HEMTs) using TCAD analysis. Through the comprehensive analysis of the dual gate structure with the additional gate placed between the gate–source (DG-GS) and gate–drain (DG-GD) regions, the impact on the linearity performance has been compared with that of a standard single gate (SG) structure. The dual gate configuration exhibits a flatter and broader transconductance (g m) profile than the SG configuration. The reduction in the third-order intermodulation levels is confirmed with the polynomial fitting method. The f T/f max of the DG-GS case is simulated to be 52/102 GHz, which shows that such configuration does not deteriorate the RF performance. Comprehensive simulations are carried out to study the device physics and assess the mechanism behind the linearity improvement. The large signal model has been developed to examine the large signal RF performance as well as linearity performance metrics. An improvement of 9.6 dB in the carrier-to-intermodulation (C/I) ratio and that of 2.4 degrees in the amplitude-to-phase modulation at 6 dB backoff from P sat have been observed as compared to the SG configuration. Such characteristics have evidenced that the optimized dual-gate configuration with the second gate placed between the source and gate can effectively improve the linearity performance of the InAlGaN/AlN/GaN HEMT configurations.

Improved breakdown voltage and dynamic Ron characteristics in normally-off GaN-based HEMTs featuring fully-recessed and bilayer-dielectric gate structure

Abstract The degradation of dynamic on-resistance (Ron) is a major challenge in GaN-based high electron mobility transistors (HEMTs), which seriously affects their performance and reliability. The degradation area of dynamic Ron mainly comes from two aspects. One is the region below the gate that also affects the threshold voltage (Vth) of the devices. And the other one is the interface region of the gate to drain access. The optimal device exhibits a Vth of 0.97 V, a small Vth hysteresis of only 20 mV, a high current density of 723 mA/mm, and a breakdown voltage (BV) of 760 V which could be further boosted when additional field plate design is employed. It is found that when high voltage drain stress is applied, a positive Vth shift is induced, leading to the decrease of the effective gate driving voltage, and thus the dynamic Ron of the devices is increased. Of particular concern is the effects of dielectric layer and/or interface of the access region on the dynamic Ron degradation, which can be alleviated by removing the dielectric layer of the access region.

Role of mechanical stress localizations on the radiation hardness of AlGaN/GaN high electron mobility transistors

Abstract Multi-material, multi-layered systems such as AlGaN/GaN high electron mobility transistors (HEMTs) contain residual mechanical stresses that arise from sharp contrasts in device geometry and materials parameters. These stresses, which can be either tensile or compressive, are difficult to detect and eliminate because of their highly localized nature. We propose that their high-stored internal energy makes potential sites for defect nucleation sites under radiation, particularly if their locations coincide with the electrically sensitive regions of a transistor. In this study, we validate this hypothesis with molecular dynamic simulation and experiments exposing both pristine and annealed HEMTS to 2.8 MeV Au+3 irradiation. Our unique annealing process uses mechanical momentum of electrons, also known as the electron wind force (EWF) to mitigate the residual stress at room temperature. High-resolution transmission electron microscopy and cathodoluminescence spectra reveal the reduction of point defects and dislocations near the two-dimensional electron gas region of EWF-treated devices compared to pristine devices. The EWF-treated HEMTs showed relatively higher resilience with approximately 10% less degradation of drain saturation current and ON-resistance and 5% less degradation of peak transconductance. Both mobility and carrier concentration of the EWF-treated devices were less impacted compared to the pristine devices. Our results suggest that the lower density of nanoscale stress localization contributed to the improved radiation tolerance of the EWF-treated devices. Intriguingly, the EWF is found to modulate the defect distribution by moving the defects to electrically less sensitive regions in the form of dislocation networks, which act as sinks for the radiation induced defects and this assisted faster dynamic annealing.

K/Ka‐Band–GaN–High‐Electron‐Mobility Transistors Technology with 700 mS mm−1 Extrinsic Transconductance

In this study, the impacts of fabrication technology and epitaxial layer design on the transconductance (gm) of radio frequency AlGaN/GaN high‐electron‐mobility transistors (HEMTs) are examined. Optimization of the SiNx passivation and AlGaN barrier design of 150 nm gate HEMTs enhances the extrinsic (at Vds = 10 V) and intrinsic (at Vds = 15 V) transconductance from ≈0.47/0.65 to ≈0.62/1.1 S mm−1. Notably, an extrinsic gm of 0.70 S mm−1 at Vds = 5 V is achieved, setting a new benchmark for the extrinsic transconductance of AlGaN/GaN HEMTs designed for the K/Ka frequency range with a breakdown voltage exceeding 100 V.

Internally Harmonic Matched Compact GaN Power Amplifier with 78.5% PAE for 2.45 GHz Wireless Power Transfer Systems.

In this paper, a high-efficiency compact power amplifier is designed and fabricated with a 0.25 μm GaN high electron mobility transistor (HEMT) to meet the demands of a high integration level and high efficiency for microwave wireless power transfer (WPT) systems. The proposed power amplifier (PA) is implemented using an internally matched method to achieve a compact circuit size. The output second and third harmonic impedances can be optimized through output matching circuits, eliminating the need for additional harmonic matching networks. This approach simplifies the design of matching circuits and reduces the circuit size. Furthermore, the input third harmonic has been controled for improving the efficiency of DC-to-RF conversion. The total size of the proposed PA is 13.4 × 13.5 mm2. The test results obtained from the continuous wave (CW) testing indicate that the output power of the power amplifier at 2.45 GHz reaches 43.75 dBm. Additionally, the large-signal gain is measured at 15.75 dB, and the power-added efficiency (PAE) achieves a value of 78.5%.

Device structural engineering and modelling of emerging III-nitride/β-Ga2O3 nano-HEMT for high-power and THz electronics

Abstract III-nitrides, such as gallium nitride (GaN) and aluminium nitride (AlN), possess a wide bandgap, a high breakdown voltage, and a high thermal conductivity, making them an attractive choice for high frequency and high-power applications. A further benefit of III-nitride-based HEMTs is their high current density, low noise figure, and higher electron mobility, which enable efficient radio-frequency signal amplification. In this research work, the polarization induced graded buffer technique and improved lattice matched β-Ga2O3 substrate is employed to minimize the buffer-related issues in III-Nitride Nano-HEMTs (high electron mobility transistors), such as reduction in the buffer leakage current losses. The polarization-induced doping in buffer region can considerably reduce the buffer leakage current, enhance breakdown voltage and RF characteristics, and bend the conduction band upwardly convex, improving two-dimensional electron gas (2DEG) confinement. A detailed comparison between the graded buffer technique of the HEMT and the HEMT having normal buffer has been conducted. The results demonstrated that the suggested HEMT demonstrated better DC and RF characteristics up to the Tera (1012) hertz range of frequencies. The improved characteristics of the proposed HEMT allow it to be a feasible solution for emerging technologies and cutting-edge communication systems that require efficient signal processing at very high frequencies.

Theoretical studies of the bipolar properties of ScAlN/AlGaN/GaN heterostructures for enhanced device applications

Here, we describe a systematic theoretical study of ScAlN/AlGaN/GaN heterostructures for enhanced high-electron-mobility transistors (HEMTs). We have investigated the carrier distributions and energy-band diagrams by solving the coupled Schrödinger and Poisson equations self-consistently. When the heterostructure is in the “off” state, the two-dimensional electron gas (2DEG) becomes increasingly depleted as the ScAlN thickness is increased to the critical thickness, at which point the two-dimensional hole gas (2DHG) appears. This critical thickness depends on the Sc content. Increasing the AlGaN thickness or Al content causes a simultaneous increase in the 2DEG and 2DHG sheet densities. In addition, when the HEMT is in the “on” state, 2DEG sheet density increases as ScAlN thickness increases, so long as the Sc content is less than 0.3; when the Sc content exceeds 0.4, this trend is reversed. For a given Sc content, double channels are produced when the ScAlN thickness exceeds the critical thickness.

Analysis of On-Resistance in 650-V Enhancement-Mode Active-Passivation p-GaN Gate HEMT

This work investigates the resistance distribution of the E-mode GaN-on-Si active-passivation (AP) p-GaN gate high-electron-mobility transistor (HEMT) using the transfer length method (TLM). The AP-HEMT has a unique active-passivation layer that is electrically connected to the p-GaN gate and covers most area of the device. The active-passivation layer changes the way the 2DEG is generated in the device, so the constitution of the device R ON is expected to differ from the conventional p-GaN gate HEMT (Conv-HEMT). According to our study, the sheet resistance of the 2DEG under the active-passivation layer is lower than that of the access region, leading to the reduced R ON in AP-HEMT compared to Conv-HEMT. The temperature dependence of the resistance is also investigated. Additionally, AP-HEMT exhibits an improved reverse conduction performance across the temperature range of 25 °C to 150 °C, due to the reduced gate-to-drain resistance in the device.

NPDC structure double-channel N-polar E-mode GaN HEMTs: Innovations in enhancing RF and DC performance and mitigating trap effects

—High-electron-mobility transistors (HEMTs) based on gallium nitride (GaN) are favored for their exceptional performance in high-power and high-frequency applications. However, developing dual-channel HEMTs presents challenges due to spontaneous polarization effects and design complexities. This study introduces a novel N-polar E-mode GaN HEMT with a dual-channel structure, featuring recessed drain-source regions and non-alloyed ohmic contacts. TCAD simulations provide theoretical insights and optimization strategies for these structures, focusing on the combination of N-polar GaN and ultra-wide bandgap AlN barrier layers. The optimized device demonstrates a threshold voltage of +1.08 V and a 45.9 % increase in current density. The N-polar double-channel HEMT (NPDC-HEMT) exhibited a 55.75 % improvement in peak transconductance, with Ft increasing from 13.3 GHz to 30.1 GHz and Fmax from 63.7 GHz to 65.9 GHz. Further enhancement was achieved in the T-gate variant (NPDC-T-HEMT), with Ft reaching 52.6 GHz and Fmax 94.4 GHz. The dual-channel design effectively mitigated short-channel effects and current collapse, demonstrating the potential for high-power RF applications.

High-Temperature Characterization of AlGaN Channel High Electron Mobility Transistor Based on Silicon Substrate.

In this paper, it is demonstrated that the AlGaN high electron mobility transistor (HEMT) based on silicon wafer exhibits excellent high-temperature performance. First, the output characteristics show that the ratio of on-resistance (RON) only reaches 1.55 when the working temperature increases from 25 °C to 150 °C. This increase in RON is caused by a reduction in optical phonon scattering-limited mobility (μOP) in the AlGaN material. Moreover, the device also displays great high-performance stability in that the variation of the threshold voltage (ΔVTH) is only 0.1 V, and the off-state leakage current (ID,off-state) is simply increased from 2.87 × 10-5 to 1.85 × 10-4 mA/mm, under the operating temperature variation from 25 °C to 200 °C. It is found that the two trap states are induced at high temperatures, and the trap state densities (DT) of 4.09 × 1012~5.95 × 1012 and 7.58 × 1012~1.53 × 1013 cm-2 eV-1 are located at ET in a range of 0.46~0.48 eV and 0.57~0.61 eV, respectively, which lead to the slight performance degeneration of AlGaN HEMT. Therefore, this work provides experimental and theoretical evidence of AlGaN HEMT for high-temperature applications, pushing the development of ultra-wide gap semiconductors greatly.

Thermal modelling and layout optimization of GaN half-bridge IC with integrated drivers and power HEMTs

The paper presents the results of thermal modeling of a half-bridge monolithic integrated circuit (IC) with integrated drivers and enhanced mode power high electron mobility transistors, based on a GaN-on-SOI heterostructure. It had been established that the main heat sources in the IC were the half-bridge GaN HEMTs. The heat from the half-bridge GaN HEMTs propagates in the chip and leads to heating of the logic block and gate drivers. Heating of half-bridge GaN HEMTs leads to increased channel resistance and IC output current drop. Heating of the gate drivers reduces driving current, as a result, increases the switching time of the half-bridge GaN HEMTs. Heating of the logic block increases the rise and fall times of the generated control signals, which worsens the dynamic characteristics of the IC. A comparative analysis of heat propagation for IC dies based on GaN-on-SOI and GaN-on-Si heterostructures showed that GaN-on-SOI structure has a 40% greater junction-to-backside thermal resistivity compared to GaN-on-Si structure. In this case, the specific thermal resistance in the direction of heat propagation from the hotspot of the transistor to the backside of the die for the GaN-on-SOI structure is almost two orders of magnitude greater than in the direction of its propagation to the frontside of the chip. The results obtained were used for IC layout optimization. The rearrangement of GaN-on-SOI IC functional blocks, as well as to introduction of additional heat-spreading elements on the frontside of chip were carried out during the optimization.