High Drain-source Voltage Research Articles

Distinct Contact Scaling Effects in MoS2 Transistors Revealed with Asymmetrical Contact Measurements.

2D semiconducting materials have immense potential for future electronics due to their atomically thin nature, whichenables better scalability. While the channel scalability of 2D materials has been extensively studied, the current understanding of contact scaling in 2D devices is inconsistent andoversimplified. Here physically scaled contacts and asymmetrical contact measurements (ACMs) are combined to investigate the contact scaling behavior in 2D field-effect transistors. The ACMs directly compare electron injection at different contact lengths while using the exact same MoS2 channel, eliminating channel-to-channel variations.Theresults show that scaled source contacts can limit the drain current, whereas scaled drain contacts do not. Compared to devices with long contact lengths, devices with short contact lengths (scaled contacts) exhibit larger variations, 15% lower drain currents at high drain-source voltages, and a higher chance ofearly saturation and negative differential resistance. Quantum transport simulations reveal that the transfer length of Ni-MoS2 contacts can be as short as 5nm. Furthermore,it isclearly identified that the actual transfer length depends on the quality of the metal-2D interface. The ACMs demonstrated here will enable further understanding of contact scaling behavior at various interfaces.

Investigation of Electrical and Mechanical Reliability of Inkjet-Printed 4-Terminal Microelectromechanical Relays

We investigate the mechanical and electrical reliability of inkjet-printed 4-terminal (4T) microelectromechanical (MEM) relays in various failure modes. Since an inkjet-printed mechanical relay exhibits an extremely low on-resistance (~4 Ω), the endurance of MEM relays can be limited dominantly by Joule heating from the high current density at the contacting asperities, which eventually leads to welding-induced and electromigration failures. Therefore, high drain-source voltage can reduce the mean number of cycles to failure (MCTF). In addition, the endurance also depends on the structural fatigue of the floated beams, where the mechanical strain is concentrated near the junction area of the two floated beams. Thermal and mechanical stress distributions of the suggested printed 4T MEM relay are analyzed by 3-dimensional affected significantly by charging of the dielectric or oxidation of the contacting surface which can degrade a pull-in voltage and on-current, respectively.

Repetitive short circuit capability of SiC MOSFET at specific low gate-source voltage bias for more robust extreme operation

This paper presents short-circuit (SC) performance of a commercial silicon-carbide (SiC) MOSFET device under repetitive SC stress at high drain source voltage. Two protocols are investigated to evaluate the impact of gate-source voltage (VGS) depolarization and SC duration (TSC) reduction. The VGS depolarisation provides a power density reduction and allows to preserve a secure failure mode (FTO: Fail To Open) with an increase of the short circuit duration TSCmax. The results demonstrate that SiC MOSFET VGS depolarization does not reduce SC cycling capability at TSCmax. However, using VGS depolarization allows to get performance close to IGBT robustness levels with almost 1000 cycles @TSC = 10 μs. The simulation of the chip temperature evolution during SC tests suggests that the degradations stay attributed to the increase of junction temperature (TJ) during the SC cycles, which leads to the fusion of the top Al inducing cracks into the thick oxide.

Simulation Study of A 1200V 4H-SiC Lateral MOSFET With Reduced Saturation Current

A 1200V 4H-SiC lateral double-diffused MOSFET (LDMOS) featuring a lightly doped P-top layer at the source side, and a high-doped N-well layer arranged between the channel and P-top layer is proposed. In order to promote the simulation accuracy, Sentaurus Process Tool that can simulate the oxidation, ion implantation, annealing, diffusion, etc. is used for structure establishment in this letter. In the ON-state, the electric potential at the end of the channel can be modulated and lowered due to the existence of P-top layer. The P-top layer can shield the voltage from the drain side, which results in the reduced saturation current ( $\text{I}_{\text {dsat}}$ ), especially at high drain-source voltage ( $\text{V}_{\text {DS}}$ ). The introduction of the N-well layer ensures that the P-top layer has almost no impact on the linear current ( $\text{I}_{\text {dlin}}$ ). Compared with the conventional SiC LDMOS, the $\text{I}_{\text {dsat}}$ at $\text{V}_{\text {DS}}\,\,=400\text{V}$ of the proposed LDMOS decreases by 24.2% with no degradation in the $\text{I}_{\text {dlin}}$ and the OFF-state breakdown voltage (BV). Benefiting from the suppressed $\text{I}_{\text {dsat}}$ , the proposed SiC LDMOS achieves a ON-state BV 366V higher than that of the conventional SiC LDMOS at the gate-source voltage of 20V. Since the short-circuit capability of the SiC power devices is much sensitive to the $\text{I}_{\text {dsat}}$ , the 24.2% reduction in $\text{I}_{\text {dsat}}$ can predict a considerable enhanced short-circuit capability. Simulation results show that the short-circuit withstand time can be improved by 105%.

High-Efficiency High Voltage Hybrid Charge Pump Design With an Improved Chip Area

A hybrid charge pump was developed in a 0.13- μm Bipolar-CMOS-DMOS (BCD) process which utilised high drain-source voltage MOS devices and low-voltage integrated metal-insulator-metal (MIM) capacitors. The design consisted of a zero-reversion loss cross-coupled stage and a new self-biased serial-parallel charge pump design. The latter has been shown to have an area reduction of 60% in comparison to a Schottky diode-based Dickson charge pump operating at the same frequency. Post-layout simulations were carried out which demonstrated a peak efficiency of 38% at the output voltage of 18.5 V; the maximum specified output voltage of 27 V was also achieved. A standalone serial-parallel charge pump was shown to have a better transient response and a flatter efficiency curve; these are preferable for time-sensitive applications with a requirement of a broader range of output currents. These findings have significant implications for reducing the total area of implantable high-voltage devices without sacrificing charge pump efficiency or maximum output voltage.

The Role of Carbon Doping on Breakdown, Current Collapse, and Dynamic On‐Resistance Recovery in AlGaN/GaN High Electron Mobility Transistors on Semi‐Insulating SiC Substrates

Herein, the critical role of carbon doping in the electrical behavior of AlGaN/GaN high electron mobility transistors (HEMTs) on semi‐insulating SiC substrates is assessed by investigating the off‐state three‐terminal breakdown, current collapse, and dynamic on‐resistance recovery at high drain–source voltages. Extensive device simulations of typical GaN HEMT structures are conducted and compared with experimental data from published, state‐of‐the‐art technologies to 1) explain the slope of the breakdown voltage as a function of the gate‐to‐drain spacing lower than GaN critical electric field as a result of the nonuniform electrical field distribution in the gate–drain access region; 2) attribute the drain current collapse to trapping in deep acceptor states in the buffer associated with carbon doping; and 3) interpret the partial dynamic on‐resistance recovery after off‐state stress at high drain–source voltages as a consequence of hole generation and trapping.

Formation of a functional homo-junction interface through ZnO atomic layer passivation: Enhancement of carrier mobility and threshold voltage in a ZnO nanocrystal field effect transistor

We report enhancement of mobility and increase in mobile carrier concentration in zinc oxide (ZnO) nanocrystal (NC) field effect transistors (FETs) through the formation of a homo-junction interface using atomic layer deposition (ALD) passivation. An ultrathin ALD-ZnO passivation film deposited on a ZnO NC film not only increased the FET mobility from 4.6ⅹ10−6 to 1.4ⅹ10−4 cm2/V but also caused earlier turn-on of the ZnO NC FETs, shifting the threshold voltage from 18.9 to −4.6 V. The enhanced FET mobility and earlier turn-on in the FET are attributed to reduced localized state density on the ZnO NC surface through ALD-ZnO passivation. Passivation of the surface states mitigates carrier depletion in the ZnO NC film through oxygen adsorption on the ZnO surface. We also observed that the presence of saturation of the drain in a high drain-source voltage region depends on the ALD-ZnO passivation and its origin is discussed.

Anomalous Conductance near Percolative Metal-Insulator Transition in Monolayer MoS2 at Low Voltage Regime.

Conductivity of the insulating phase increases generally at an elevated drain-source voltage due to the field-enhanced hopping or heating effect. Meanwhile, a transport mechanism governed by percolation in a low compensated semiconductor gives rise to the reduced conductivity at a low-field regime. Here, in addition to this behavior, we report the anomalous conductivity behavior to transform from a percolative metallic to an insulating phase at the low voltage regime in monolayer molybdenum disulfide (MoS2). Percolation transport at low source-drain voltage is governed by inhomogeneously distributed potential in strongly interacting monolayer MoS2 with a substrate, distinct from the quantum phase transition in multilayer MoS2. At a high source-drain voltage regime, the insulating phase is transformed further to a metallic phase, exhibiting multiphases of metallic-insulating-metallic transitions in monolayer MoS2. These behaviors highlight MoS2 as a model system to study various classical and quantum transports as well as metal-insulator transition in two-dimensional systems.

High-Source–Drain Voltage-Induced Reliability Issues of Sub-28-nm Node MOSFET’s Application in Resistive-Type Nonvolatile Memory Array

In this brief, we investigate the reliability issues of MOSFETs with bulk 28-nm technology for its possible application in resistive-type nonvolatile memory (RNVM). The impact of electrical stress on transistors when working in the 1T1R array cells is discussed. It is found that the high source-drain voltage bias during the 1T1R array operation is the main reason causing the MOSFET degradation. Furthermore, by comparing the electrical characteristics of MOSFETs with different channel lengths, it is confirmed that the degradation is caused by high-energy electrons drifting from the source side to the drain end under a high electric field. As a result, this issue will be more serious as the gate length continues to scale down. An ultralow operation voltage RNVM is required for a better lifetime if RNVM is embedded in sub-28-nm technologies.

On-wafer RF stress and trapping kinetics of Fe-doped AlGaN/GaN HEMTs

In this paper, we investigate the trapping effects, of iron doped AlGaN/GaN HEMTs, before and after on-wafer 24 hour RF stress test. First, we study the trap centers responsible of the current collapse at different on-state bias and temperature conditions. Second, we investigate 24 hour RF stress effect on the trapping kinetics.By filling traps under off-state condition with high drain-source voltage, we have identified two prominent traps labelled E1 and E2 with activation energies of 0.7 eV and 0.6 eV under the conduction band, respectively. An increase of the amplitude of the trap centers E1 and E2 by 22.9% and 15.8% respectively is noticed during the RF stress. This result suggests that the degradation observed during RF stress might have induced a density increase of the traps involved in the E1 and E2 trap signatures responsible on the current collapse.

Suppression of drain-induced barrier lowering by double-recess overlapped gate structure in normally-off AlGaN-GaN MOSFETs

We investigated drain-induced barrier lowering (DIBL) in normally-off AlGaN-GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with a double-recess overlapped gate structure. It is found that the double-recess overlapped gate structure can suppress DIBL; the threshold voltage is constant without lowering for high drain-source voltages, and sub-threshold characteristics remains excellent. We elucidate the mechanism of the DIBL suppression by considering a local potential in the MOSFETs. In addition, it is also found that the double-recess overlapped gate structure is beneficial for current collapse suppression.

Ambipolar conductivity in organic field-effect transistors based on 1,7-bis(9-ethyl-3-carbazolyl) N,N′-2-ethyl hexyl perylene bisimide under the light illumination

The occurrence of light induced ambipolar conductivity in organic transistors based on 1,7-bis(9-ethyl-3-carbazolyl) N,N′-2-ethyl hexyl perylene bisimide (BCEHPB) was studied. It is shown that under illumination the output characteristics are transformed into superposition of standard saturated behavior for one carrier at high gate voltage and a superlinear current increase at low gate voltage and high source–drain voltage due to injection of the opposite (hole) carrier. The influence of injection of holes from metal electrodes by impedance spectroscopy barrier structure BCEHPB/Ag was studied to explain this effect. Increasing the injection of holes in the transistor under illumination can be interpreted as a result of the devastation of the interface trap states.

Pseudodiffusive conductance, quantum-limited shot noise, and Landau-level hierarchy in a biased graphene bilayer

We discuss, by means of mode-matching analysis for the Dirac equation, how splittings of the Landau-level (LL) degeneracies associated with spin, valley, and layer degrees of freedom affect the ballistic conductance of graphene bilayer. The results show that for wide samples ($W\gg{}L$) the Landauer-B\"{u}ttiker conductance reaches the maximum $G\simeq{}se^2/(\pi{h})\times{}W/L$ at the resonance via each LL, with the prefactor varying from $s=8$ if all three degeneracies are preserved, to $s=1$ if all the degeneracies are split. In the absence of bias between the layers, the degeneracies associated with spin and layer degrees of freedom may be split by manipulating the doping and magnetic field; the conductance at the zeroth LL is twice as large, while the conductance at any other LL equals to the corresponding conductance of graphene monolayer. The presence of bias potential allows one also to split the valley degeneracy. Our results show that the charge transfer at each LL has pseudodiffusive character, with the second and third cumulant quantified by ${\cal F}=1/3$ and ${\cal R}=1/15$ (respectively). In case the electrochemical potential is allowed to slowly fluctuate in a finite vicinity of LL, the resulting charge-transfer characteristics are still quantum-limited, with ${\cal F}\simeq{}0.7$ and ${\cal R}\simeq{}0.5$ in the limit of large fluctuations. The above values of ${\cal F}$ and ${\cal R}$ are also predicted to be approached in the limit of high source-drain voltage difference applied. The possible effects of indirect interlayer hopping integrals are also briefly discussed.

Kink effect in current—voltage characteristics of a GaN-based high electron mobility transistor with an AlGaN back barrier

The kink effect in current—voltage (IV) characteristic s seriously deteriorates the performance of a GaN-based HEMT. Based on a series of direct current (DC) IV measurements in a GaN-based HEMT with an AlGaN back barrier, a possible mechanism with electron-trapping and detrapping processes is proposed. Kink-related deep levels are activated by a high drain source voltage (Vds) and located in a GaN channel layer. Both electron trapping and detrapping processes are accomplished with the help of hot electrons from the channel by impact ionization. Moreover, the mechanism is verified by two other DC IV measurements and a model with an expression of the kink current.

Non-ohmic behavior of carrier transport in highly disordered graphene

We report measurements of disordered graphene probed by both a high electric field and a high magnetic field. By applying a high source–drain voltage, Vsd, we are able to study the current–voltage relation I–Vsd of our device. With increasing Vsd, a crossover from the linear I–Vsd regime to the non-linear one, and eventually to activationless-hopping transport occurs. In the activationless-hopping regime, the importance of Coulomb interactions between charged carriers is demonstrated. Moreover, we show that delocalization of carriers which are strongly localized at low T and at small Vsd occurs in the presence of high electric field and perpendicular magnetic field.

DC characteristics of lattice-matched InAlN/AlN/GaN high electron mobility transistors

Lattice-matched InAlN/AlN/GaN high electron mobility transistors (HEMTs) grown on sapphire substrate by using low-pressure metallorganic chemical vapor deposition were prepared, and the comprehensive DC characteristics were implemented by Keithley 4200 Semiconductor Characterization System. The experimental results indicated that a maximum drain current over 400 mA/mm and a peak external transconductance of 215 mS/mm can be achieved in the initial HEMTs. However, after the devices endured a 10-h thermal aging in furnace under nitrogen condition at 300 °C, the maximum reduction of saturation drain current and external transconductance at high gate-source voltage and drain-source voltage were 30% and 35%, respectively. Additionally, an increased drain-source leakage current was observed at three-terminal off-state. It was inferred that the degradation was mainly related to electron-trapping defects in the InAlN barrier layer.

690V, 1.00 mΩcm<sup>2</sup> 4H-SiC Double-Trench MOSFETs

The trench gate structure MOSFET, with its lack of JFET resistance, is one of the structures able to achieve low on-state resistance [1,2]. In 2008, this group succeeded in fabricating 790V SiC trench MOSFETs with the lowest Ron,sp (1.7 mΩcm2) at room temperature. However these devices had issues regarding oxide destruction at the trench bottom during high drain-source voltage application. In order to improve this problem, this group developed the double-trench MOSFET structure. This structure has both source trenches and gate trenches. This paper compares two kinds of trench MOSFETs: the conventional, single trench structure and a double-trench structure. Also, the latest characteristics are presented.

Unipolar transport in bilayer graphene controlled by multiple p-n interfaces

Unipolar transport is demonstrated in a bilayer graphene with a series of p-n junctions and is controlled by electrostatic biasing by a comb-shaped top gate. The OFF state is induced by multiple barriers in the p-n junctions, where the band gap is generated by applying a perpendicular electric field to the bilayer graphene, and the ON state is induced by the p-p or n-n configurations of the junctions. As the number of the junction increases, current suppression in the OFF state is pronounced. The multiple p-n junctions also realize the saturation of the drain current under relatively high source-drain voltages.

Floating electrode transistor based on purified semiconducting carbon nanotubes for high source–drain voltage operation

We report floating-electrode-based thin-film transistors (F-TFTs) based on a purified semiconducting single-walled carbon nanotube (swCNT) network for a high source–drain voltage operation. At a high source–drain voltage, a conventional swCNT-TFT exhibited poor transistor performance with a small on–off ratio, which was attributed to the reduced Schottky barrier modulation at a large bias. In the F-TFT device, an swCNT network channel was separated into a number of channels connected by floating electrodes. The F-TFTs exhibited a much higher on–off ratio than a conventional swCNT-TFT with a single channel. This work should provide an important guideline in designing swCNT-TFTs for high voltage applications such as displays.

Power SiC DMOSFET Model Accounting for Nonuniform Current Distribution in JFET Region

The main goal of this paper is development of a new circuit-based silicon carbide (SiC) DMOSFET model which physically represents the mechanism of current saturation in power SiC DMOSFET. Finite-element simulations show that current saturation for a typical device geometry is due to 2-D carrier distribution effects in the JFET region caused by current spreading from the channel to the JFET region. For high drain-source voltages, most of the voltage drop occurs in the current spreading region located in the JFET region close to the channel. A new model is proposed that represents the nonuniform current distribution in the JFET region using a nonlinear voltage source and a resistance network. Advantages of the proposed model are that a single set of equations describes operation in both the linear and saturation regions, and that it provides a more physical description of MOSFET operation.