High Density Through Silicon Via Research Articles

Low Stress TSV Arrays for High-Density Interconnection

In three-dimensional (3D) stacking, the thermal stress of through-silicon via (TSV) has a significant influence on chip performance and reliability, and this problem is exacerbated in high-density TSV arrays. In this study, a novel hollow tungsten TSV (W–TSV) is presented and developed. The hollow structure provides space for the release of thermal stress. Simulation results showed that the hollow W-TSV structure can release 60.3% of thermal stress within the top 2 μm from the surface, and thermal stress can be decreased to less than 20 MPa in the radial area of 3 μm. The ultra-high-density (1600 TSV∙mm−2) TSV array with a size of 640 × 512, a pitch of 25 μm, and an aspect ratio of 20.3 was fabricated, and the test results demonstrated that the proposed TSV has excellent electrical and reliability performances. The average resistance of the TSV was 1.21 Ω. The leakage current was 643 pA and the breakdown voltage was greater than 100 V. The resistance change is less than 2% after 100 temperature cycles from −40 °C to 125 °C. Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W-TSV was 31.02 MPa, which means that there was no keep-out zone (KOZ) caused by the TSV array. These results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.

DUV-LED packaging using high density TSV in silicon cavity and laser-glass-frit-bonded UV transmitting glass cap

This paper reports an improved deep ultraviolet LED (DUV-LED) packaging based on Si Micro-Electro-Mechanical Systems (MEMS) process technology. The Si package (Si-PKG) consists of a cavity formed by Si crystalline anisotropic wet etching and through-silicon vias (TSVs) filled with electroplated Cu. The Si-PKG is hermetically sealed by laser local heating of screen-printed glass frit. This technology allows for the use of a DUV-transparent glass substrate, which has an unmatched coefficient of thermal expansion (CTE). Using a high-density array of TSV capped with AuSn solder bumps, the cooling performance of the DUV-LED has been greatly improved. And the contribution by the Si (111) side reflection of Si-PKG to the total light output was confirmed 13 %. As a result, an optical output of 114 % (50 mW) and a volumetric light power density of 380 % (14 mW/mm3) were recorded compared with the conventional AlN-packaged device. The developed compact low-cost Si-PKG is promising for wider applications of the DUV-LED including the disinfection of the new coronaviruses.

Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube.

Area-Efficient Extended 3-D Inductor Based on TSV Technology for RF Applications

An extended model of through-silicon via (TSV)-based solenoid inductor is proposed to save on-chip areas for 3-D radio frequency (RF) ICs and package integration. To achieve a high inductance density, the nested topology consists of high-density TSVs in high-resistivity silicon substrate and multilayers of metals in compatible CMOS process. Then, an analytical inductance model, considering the mutual inductance of TSVs and complicated metal traces, is established and verified. The inductance variation in physical dimensions is studied based on the modeled and simulated results of a TSV solenoid inductor in single tier. The proposed TSV solenoid typology gets better performance at inductance density and quality factor around some frequencies through analytical model and full-wave simulations. Further studies are directed toward RF application overview according to broadband and low power consumption.

Bottom-up Copper Electrodeposition in 20:1 Aspect Ratio, 20 Μm Pitch through Silicon Vias

Heterogeneous integration (HI) offers a path to increase bandwidth density and reducing power consumption per area for advanced microelectronic systems by minimizing fan-in/out structures and reducing parasitics. To achieve state-of-the-art areal bandwidth density, 3D HI is required with through silicon vias (TSVs) with extremely tight interconnect pitches (< 50 µm) and high aspect ratios. Fabrication and fill of these proposed TSVs pose significant challenges including substrate thinning, high aspect ratio deep reactive ion etching (DRIE), conformal thin film deposition to deposit insulating layers as well as seed metals for electrodeposition, and void-free fill of the TSVs. Here, we target an interconnect pitch of 20 µm and TSV diameter of 5 µm. At these dimensions, DRIE lag limits the TSV depth to 100 µm. The TSVs are integrated using a via-last scheme with atomic layer deposition (ALD) Al2O3 as the insulating liner and ALD Pt serving as both the barrier and electrochemical deposition (ECD) seed liner. In this work, we describe the integration scheme for these high density TSVs and focus on the ECD process for achieving a void-free fill with Cu as well as characterization approaches using focus ion beam (FIB) cross sectioning.Recent work on Cu ECD has demonstrated the efficacy of a two-additive acid sulfate electrolyte system based on a chemistry exhibiting a S-shaped negative differential resistance voltammogram1. The electrodeposition system presented is a 1.0 mol/L CuSO4 – 0.5 mol/L H2SO4 acid sulfate electrolyte containing a polyether surfactant and halide additive which promotes a bottom-up Cu growth profile via positive feedback between localized disruption of adsorbed polyether-halide layer and metal deposition. This electrolyte has been applied to potentiostatic filling of a variety of geometries with both micro-scale1 and mm-scale2 TSVs as well as current controlled bottom-up filling from a conformally conductive seed metal3. This system relies on fine tuning of applied bias, adsorbate concentrations, convection, and deposition time to ensure a bottom-up deposition regime is maintained in a particular via geometry.Previous work developed parameters for filling 600 µm deep 5:1 aspect ratio TSVs and the same parameters were applied to 600 µm deep 10:1 aspect ratio TSVs with drastically different filling results.2 In this work, we further adjust the relevant ECD parameters to fill 20:1 aspect ratio TSVs that are 100 µm deep.In fine pitch, high aspect ratio ECD, characterization of the deposited fill profile is important and is difficult to obtain using mechanical cross-sectioning. Here, we use a characterization approach which relies on focused ion beam (FIB) cross-sectioning rather physical grinding and polishing. The FIB mills into the surface of the sample at a 38º angle with respect to the surface of the sample while the electron beam collects a series of images looking down at the sample, as shown in Figure 1.The series of images collected throughout the FIB milling process are then reconstructed to generate a cross-sectional image. FIB cross-sectioning is also used to provide granular detail about deposition morphology and grain size of the ECD Cu that can be lost during mechanical cross-sectioning. Figure 2, shows a top down scanning electron microscopy image of the TSV sample after milling at 38º and the resulting reconstructed cross-sectional image. T. P. Moffat and D. Josell, J. Electrochem. Soc., 159, D208 (2012).L. A. Menk, D. Josell, T. P. Moffat, E. Baca, M. G. Blain, A. Smith, J. Dominguez, J. McClain, P. D. Yeh, and A. E. Hollowell, Journal of the Electrochemical Society, 166 (1) D3066-D3071 (2019).L. A. Menk, E. Baca, M. G. Blain, J. McClain, J. Dominguez, A. Smith, and A. E. Hollowell, Journal of the Electrochemical Society, 166 (1) D3226-D3231 (2019) Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. This work was funded by the DARPA Photonics in the Package for Extreme Scalability (PIPES) program under award number HR001119S0004. The views, opinions, and/or findings expressed are those of the author(s) and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government. Figure 1

Power Delivery Network Modeling and Benchmarking for Emerging Heterogeneous Integration Technologies

In this article, a power delivery network (PDN) modeling framework for heterogeneous integration platforms is presented, which includes both IR-drop and transient analysis. The model is validated using IBM power grid benchmarks, and maximum relative errors are less than 7.3%. To evaluate interposer and bridge-chip-based integration platforms, we assume a field-programmable gate array (FPGA)-CPU 2.5-D integration platform, of which the FPGA consumes 45 W and the CPU consumes 75 W. The simulation results show that an interposer with dense power/ground grid and microbumps can suppress power supply noise (PSN) by a small margin with the requirement of high-density through-silicon vias (TSVs). For bridge-chip-based integration, under the assumption that the active dice above the bridge-chips are not connected to the package power/ground planes, some PDN challenges are evaluated. Using multiple bridge-chips and smaller overlap areas between the bridge-chips and the active dice, the worst-case PSN in bridge-chip-based integration is minimized. Next, we perform parametric studies for these 2.5-D integration platforms as a function of C4 bump pitch and metal layers. Lastly, we propose to use TSVs in the bridge-chip to reduce PSN. With nine bundled TSVs of $8~\mu \text{m}$ diameter, the IR-drop of bridge-chip-based integration technologies is only 1% higher than the standalone case.

Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer

We combined a “via-last through-silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer” with the solder bonding process using Ar fast atom beam (FAB), and realized the fabrication and three-dimensional (3D) stacking of a high-density TSV array chip. The size of the TSV array was 76 × 500. The diameter and length of the TSV were 6 and 21–22 μm, respectively. As the TSV array chip was very thin (approximately 26 μm) and had a strip-like shape, it was fragile and warped by approximately 90 μm. Hence, an electrostatic chuck was introduced and the TSV array chip was stacked by using a soft material (Cu–Ni–Sn based solder) as a bump and performing low-pressing-load low-temperature bonding with Ar FAB. As a result, the warpage of TSV array chip was suppressed and the TSV array chip was stacked without causing damage to the TSV and Si region. In addition, it was confirmed that the (i) leakage current between TSV-bump pairs is small, (ii) multilayer wiring + TSV + bump connection exhibit low resistance, and (iii) daisy chain is perfectly connected to up to 38 000 TSVs. These results are due to the effects of notchless Si etching, wet cleaning of the first metal layer, introduction of an electrostatic chuck, low-pressing-load low-temperature bonding with a soft material, and Ar FAB. This process will facilitate the development of face-up type 3D stacked sensor systems.

High-Resolution E-Jet Enhanced MEMS Packaging

High-resolution electrohydrodynamic inkjet printing has potential to simplify the existing MEMS package fabrication through its additive and digital properties without sacrifices in the I/O density of the package. Initially, the replacement of certain lithographic process steps would lead to decreased material consumption and increased cost-effectiveness of the package fabrication; in long term, the large-scale adoption of additive process steps would enable increasing device customizability and lead to cost-effective fabrication of small batches and even fully tailored device specific MEMS packages. In our work, we have demonstrated the feasibility of this approach by replacing selected lithographic process steps by using high-resolution inkjet technology (Super Inkjet, SIJ Tech.) for metallization of high-density redistribution layers (RDL), metallization of through-silicon-vias (TSV) and fabrication of under bump metallization (UBM). Fully printed high-density redistribution layer (RDL) A fully printed high density RDL in two metallization layers was demonstrated with a combination of Super Inkjet (SIJ) and conventional inkjet printing (DMP-2831). The SIJ was used for the metallization of 5/5 µm W/S high-density circuitry in MET1 and MET2 and DMP for the dielectric layer separating the metallization layers. In order to achieve low resistance conductors with minimal footprint, multilayer printing was employed resulting in a high aspect ratio of over one. The MET1 to MET2 microvia was also additively fabricated by first printing a narrow ~10µm pillar in MET1 with SIJ, then surrounding the pillar with DMP printed dielectric layer and finally connecting the top of the pillar with SIJ printed MET2 conductors. [1] A fully printed RDL increases the customizability of the package fabrication process to a level where each individual interposer on wafer could be fitted with customized RDL to accommodate a specific MEMS device. In addition, the material consumption is reduced significantly since the fully printed RDL does away with global deposition of metal, masking and etching required in standard lithography based metallization. It is also important to notice that these advantages are achieved without sacrificing the density the RDL: the 5/5µm width and spacing for conductors and 10µm microvia diameter are similar to what is achieved with current lithographic processes. Additive metallization of high-density through-silicon-vias (TSV) The sub-femtoliter droplet size of the SIJ and concomitant fast evaporation rate was utilized in rapid metallization of high-density TSVs with top diameter of 23µm and spacing of 10µm. In standard practice CVD, PVD, electroplating or electroless deposition are utilized for metallization of high density TSVs leading to long process time and low level of customizability. The conventional inkjet printing could be used for over 50µm TSV diameters, but it is difficult to achieve stable operation with a 1pl cartridge which could produce small diameter droplets for filling the high density TSVs of 20µm diameter; also the low evaporation rate of the relatively large droplets would prolong the process time since evaporation step would need to be included in the process; in addition, the positioning accuracy of the conventional inkjet printer (e.g. DMP) might not be sufficient for this application. In this regard it was noticed that the SIJ printing has many advantages: first, the sub-femtoliter droplet size leads to fast evaporation rate enabling the metallization of the vias at room temperature without substrate heating or evaporation steps; second, the positioning accuracy of the SIJ stage is under 1µm enabling accurate deposition of the ink in to the TSV; third, since most of the solvent in the droplets is already evaporated during the flight, the chances for creating gas pockets in the filling are reduced. [2] High-resolution inkjet printing for creating smooth UBM The previously discussed approaches for utilizing the high-resolution Super Inkjet printing were restricted to features inside the interposer. However, this fabrication technology also finds utility on the outside of the package, which does not necessarily need such high-density features, but where low surface roughness is important. Highlighting this advantage, a smooth under bump metallization has been fabricated with SIJ on top of a large diameter partially metallized TSV; the TSV has been filled with SIJ printed polymer dielectric. [3] References Laurila et al, “Combination of E-jet and inkjet printing in additive fabrication of multilayer high-density RDL of silicon interposer”, IEEE Trans. Electr. Dev., vol. 64, no. 3, pp. 1217-1224, March 2017 Khorramdel et al, “Metallization of high-density TSVs using Super Inkjet technology”, 2015 IEEE 65th ECTC conf., San Diego, 2015, pp. 41-45 Khorramdel et al, “Inkjet printing technology for increasing the I/O density of 3D TSV interposers”, Microsystems & Nanoengineering, vol. 3, 17002, Apr. 2017

Polymer-Based Liner TSV Fabrication Scheme and Its Resistance Variation

In this paper, a process scheme for polymer TSV fabrication is proposed to solve the difficulty of polymer liner formation in TSV technology. By using ring trench etching and BCB deposition in a vacuum environment, uniform BCB liner can be successfully fabricated. Electrical measurement by using Kelvin structure is completed to ensure the performance of fabrication. However, a new phenomenon causing tiny resistance changes with the arrangement of TSV is discovered during the measurement of TSV chain. In this research, this effect is discussed in detail by designing different design of experiment (DOE) to pursue good electrical connection and reduce the variance of delay property of each TSV. Based on statistical results, impacts of TSV manufacturing process variance are discussed and the guideline in high density TSV design is found.

Innovative polyimide liner deposition method for high-aspect-ratio and high-density through-silicon-vias (TSVs)

In three-dimensional (3D) integration, liner deposition technique with excellent step coverage is a challenge to realize through-silicon-vias (TSVs), especially for TSVs with high-aspect-ratio and high-density. This paper proposes an innovative polyimide liner deposition method, which utilizes the vacuum-assisted polymer filling and spin-coating processes, for TSV applications. The experimental SEM images and EDX analyses show that, a high-density TSV array, with a diameter of 8μm and depth of 60μm (corresponding aspect-ratio as high as 7.5:1), has been successfully deposited with uniform polyimide liner with the proposed method. Besides, the impacts of polyimide viscosity on the liner deposition characteristics have been investigated and detailed in this paper to get an optimization. The proposed polymer liner deposition approach involves simple and feasible process. It is not only versatile to polymers but also it is completely compatible to CMOS technology. It puts little limit on thermal budget of subsequent process and is valid for “via-middle” and “via-last” three-dimensional integration applications.

3D Wafer Level Heterogeneous Integration

3D integration is worldwide considered as one of the most important key technology for microelectronics to meet the growing demands regarding more functionality with concurrent increase in performance as well as miniaturization and cost reduction. So 3D integration is of main relevance for application areas e.g. cyber physical systems, internet of things, ambient assisted living (AAL) as well as information & communication, logistics, security, automotive, health care and industrial electronics. Besides following “More Moore”, Europe is pursuing a strategy on heterogeneous integration approaches following “More than Moore”. In this context, individual and different 3D integration approaches are adapted to the specific application scenarios.Interposers with Through Silicon Vias (TSV) are becoming a very important element for the realization of 3D System in Packages (SiPs). Main advantages of silicon interposers are the decoupling of front end/back end processing for the implementation of TSVs, redistribution layers (RDL) and the integration of active and passive devices. Besides independent manufacturing, interposers can be realized in short time-to-market time frame and in a cost effective way. TSV interposers are designed and manufactured for the different application areas which results also in different technical specifications ranging from high density TSV integration and high density RDL for digital applications to interposers for RF application as well as MEMS integration and optical interconnects.The presentation will highlight results and technical achievements for 3D integration using TSV interposer and addresses as well the broad spectrum of topics from design, technology and reliability related to 3D systems.Concerning technical features, interposers deal with high density wiring redistribution layers (RDL), TSVs and top/bottom side interconnect formation (bumping). This allows the electrical signal routing across the top side and to the interposer back side. Some new applications appear to require up to 4 layers RDL of less than 1μm line/space and silicon oxide/nitride dielectric layer.Silicon interposers with TSVs provide additional features to address 3D-SiP for heterogeneous integration. These include:Device carrier for stacked devices,High density wiring between (stacked) components,3D device stacking using TSVs,Integrated passive devicesEmbedding of active devices into the IP,Functional layer integration (actors, sensors, antennas),Modularization,Integrated test features For the assembly and 3D stack formation of the devices, different interconnection technologies, e.g. micro solder bumps (SnAg) and copper pillars, are used to deal especially with surface topography of the devices and warpage of the board/substrate.Beside silicon interposer, also glass interposers are emerging elements for specific applications. Compared to silicon interposers, glass interposer currently have only limited via dimension and cannot deal with high density TSVs, e.g. <5µm diameter and 10µm pitch. For this, the supply chain is still emerging. The metallization process for silicon interposers is commonly established in wafer fabs. However, most of these facilities do not possess via-last or bumping capability. SUMMARY 3D integration technology is one of the main drivers in packaging and system integration to meet the requirements for high functionality, highly miniaturized smart systems.Future advanced 3D systems will result in complex 3D stacking approaches using the TSV technology. Silicon interposers with TSVs are an important element to combine different advanced devices into one miniaturized system (SiP) with high functionality and to overcome currently existing issues regarding TSV integration into active devices. One important task is the supply chain between e.g. IDMs, OSAT or packing houses.Another crucial aspect is the balance between performance improvement and 3D manufacturing cost (TSV & packaging). So the implementation of 3D integration using TSV and interposer is very product specific. 3D integration requires, beside the technology approaches, also an overall SiP process integration approach which addresses design, technology and reliability.Fraunhofer IZM’s center “All Silicon System Integration Dresden - ASSID” and the Fraunhofer Cluster 3D Integration (http://www.3d-integration.fraunhofer.de/en.html) are focusing on the development and prototyping of 3D systems using Cu-TSVs in active devices (via middle, via last) and silicon interposers as well.

In-line through silicon vias etching depths inspection by spectroscopic reflectometry

Through-silicon via (TSV) technology is a key feature for 3D circuit integration. The nondestructive metrology of deep-etched structures with aspect ratio of >10 and patterns with lateral dimensions in the range up to 5μm remains an challenge and can be overcome by destructive control. In this paper the inspection of TSV depth and critical dimensions (CD) of their opening were performed nondestructively by an industrial thickness measurement tool (UV–VIS spectral reflectometer). The possibilities and limits of in-line optical tools for the characterization of the high density TSV array of high aspect-ratio square vias with tapered profile in Si were examined. TSV with CD from 3 up to 7μm, pitch in the range of 7–11μm, and etch depth of 50–70μm were investigated. The TSV depth was determined using the interference effect between reflected waves from the top and bottom surfaces of the TSV structures. The rigorous coupled wave analysis (RCWA) is successfully applied to the analysis of the spectral reflectance for the determination of the TSV top and bottom CD and profile evaluation. It was shown that this method can be used for the monitoring of geometrical parameters of TSVs with dimensions from 3μm and aspect ratios up to 17:1. The non-destructive measurement data provide excellent correlation with SEM results.

Spectral reflectometry for metrology of three-dimensional through-silicon vias

The technology for semiconductor device packaging is rapidly advancing in response to increasing demand for smaller and thinner electronic devices. Three-dimensional chip stacking that uses through-silicon vias (TSVs) is a key area of technical focus, and the high-density TSV (HDTSV) is a major enabler of three-dimensional (3-D) integrated circuit technology. The ongoing development of this novel technology has created a need for noncontact characterization. One of the main challenges for 3-D TSV metrology is measuring high aspect ratio features that limit conventional optical microscopy techniques. We demonstrate the use and enhancement of an existing wafer metrology tool, a spectral reflectometer, by developing and implementing theoretical models and measurement algorithms for inspection of HDTSVs. It is capable of measuring the depth of vias, and can also be used for the estimation of bottom roughness and bottom shapes of vias through the model fitting. Our nondestructive solution has measured TSV diameters as small as 3 μm and aspect ratios >16.5∶1 . Submicron depth measurement accuracy has been verified in the range of 30 to 60 μm on via depth. Metrology results from actual wafers formed from 3-D interconnect processing are presented.

Thermal reliability analysis and optimization of polymer insulating through-silicon-vias (TSVs) for 3D integration

Polymer insulating through-silicon-vias (TSVs) is an attractive approach for high-performance 3D integration systems. To further demonstrate the polymer insulating TSVs, this paper investigates the thermal stability by measuring the leakage current under bias-temperature condition, studies the thermal stress characteristics with Finite Element Analysis (FEA), and tries to improve the thermal mechanical reliability of high-density TSVs array by optimizing the geometry parameters of pitch, liner and redistribution layer (RDL). The electrical measurements show the polymer insulating TSVs can maintain good insulation capability (less than 2×10−11 A) under challenging bias-temperature conditions of 20 V and 200°C, despite the leakage degradation observation. The FEA results show that the thermal stress is significantly reduced at the sidewall, but highly concentrates at the surface, which is the potential location of mechanical failure. And, the analysis results indicate that the polymer insulating TSVs (diameter of 10 μm, depth of 50 μm) array with a pitch of 20 μm, liner thickness of 1 μm and RDL radius of 9 μm has an optimized thermal-mechanical reliability for application.

(Invited) Technologies and Challenges of Fine Pitch Backside Via-Last TSV Process Integration for 3DIC Applications

TSV based 3D stacking IC technology has been aggressively studied recently because of strong benefits in terms of significantly form factor shrinkage, superior system performance (bandwidth & speed), great power reduction, and heterogeneous integration capability. According to different applications, there are different integration options for TSV processing. For high performance 3D system applications which required fine TSV pitch and massive IO connections, how to establish a proper TSV integration scheme became a key importance of enabling 3D IC commercialization. In additional to common foundry used via-middle (VM) process, two another via last approaches, either forming TSV form front-side or backside were also been considered as major TSV process schemes. Although front-side via last (FVL) TSV is widely adopted by OSATs, this scheme is inherently not suitable for fine pitch and high density TSV applications because of significant area penalty and wire routing constraint comparing to VM TSV process. Another backside via last (BVL) TSV process, however, showed many advantages over common VM TSV process while achieving same TSV scalability/density and routing flexibility. For examples: (1) Cu TSVs of BVL were formed after completely CMOS FEOL+BEOL processes, thus it is naturally much less or no Cu pumping out induced yield loss issues comparing to VM process; (2) BVL TSV etching can be stopped on front-side metal 1 layer instead of time etching in blind TSV of VM scheme; (3) No complicated and yield sensitive backside Cu reveal issue were involved; (4) TSV & RDL can be formed together via dual-damascene like processing to simplify process flow and reduce cost of ownership; (5) BVL process can be adopted by either foundry or OSAT manufacturers resulting in most flexible business model in 3DIC supply chain. Despite of the vantage of backside via-last scheme, many process challenges still need to be solved. In this paper, key issues of via middle integration were briefly reviewed. A capable of high aspect ratio and fine pitch TSV (CD … 5um) manufacture scheme was proposed via backside via last integration scheme. Key process technologies and challenges of this BVL scheme, such as temporary bonding, glue material selection, wafer thinning, backside TSV formation, CMP planarization as well as cost reduced TSV/RDL dual damascene flow are investigated.

Impact of high density TSVs on the assembly of 3D-ICs packaging

Multi-scale modeling construction and subsequent stress analysis for the mechanical reliability estimation of three-dimensional (3D) integrated circuit (IC) packages is challenging. This paper presents a simulation-based methodology to calculate the equivalent mechanical properties of 3D-ICs through-silicon via (TSV) interposer composed of silicon chip and copper (Cu)-filled metal to resolve this difficulty. The obtained material properties can be utilized in non-concerned regions of analytic structure to reduce modeling complexity significantly and preserve the predicted accuracy in critical locations of 3D-IC packaging simultaneously. The verification of the corresponding analytical solutions ascertains the high reliability of the results predicted by the proposed approach. The results indicate that TSV pitch is a key design factor that dominates the characteristic of a silicon interposer with array-type Cu-filled TSV. The effect resulting from TSV can be ignored as the pitch exceeds 40@mm, and pure silicon interposer is assumed to exhibit an isotropic behavior in the related stress assessment using finite element analysis.

Low Temperature Bonding with Thin Wafers for 3D Integration

The ITRS roadmap for high-density TSV interconnects specifies maximum layer thicknesses of 5-15 µm in 2013 with a sub-micron layer-to-layer alignment accuracy. For 3D chip stacks with multiple layers it is not only necessary to handle and process such thin layers, but later on these thin layers have to be stacked and bonded. When it comes to wafer bonding for high-density TSV integration, most efforts have been given to developing Cu-Cu thermo-compression bonding and direct oxide bonding. Stacking of thin wafers can be performed either after the thin wafer is debonded or while the thin wafer is still bonded onto a carrier wafer. Bonding of the thin wafer while still mounted to the carrier wafer allows comfortable and safe wafer handling, but adds some complexity to the wafer bonding process.

Characterization of high density through silicon vias with spectral reflectometry

Measurement and control is an important step for production-worthy through silicon vias etch. We demonstrate the use and enhancement of an existing wafer metrology tool, spectral reflectometer by implementing novel theoretical model and measurement algorithm for high density through-silicon via (HDTSV) inspection. It is capable of measuring depth and depth variations of array vias by Discrete Fourier Transform (DFT) analysis in one shot measurement. Surface roughness of via bottom can also be extracted by scattering model fitting. Our non-destructive solution can measure TSV profile diameters as small as 5 μm and aspect ratios greater than 13:1. The measurement precision is in the range of 0.02 μm. Metrology results from actual 3D interconnect processing wafers are presented.