High-density Plasma Chemical Vapor Deposition Research Articles

Artificial-Neural-Network-Driven Innovations in Time-Varying Process Diagnosis of Low-K Oxide Deposition.

To address the challenges in real-time process diagnosis within the semiconductor manufacturing industry, this paper presents a novel machine learning approach for analyzing the time-varying 10th harmonics during the deposition of low-k oxide (SiOF) on a 600 Å undoped silicate glass thin liner using a high-density plasma chemical vapor deposition system. The 10th harmonics, which are high-frequency components 10 times the fundamental frequency, are generated in the plasma sheath because of their nonlinear nature. An artificial neural network with a three-hidden-layer architecture was applied and optimized using k-fold cross-validation to analyze the harmonics generated in the plasma sheath during the deposition process. The model exhibited a binary cross-entropy loss of 0.1277 and achieved an accuracy of 0.9461. This approach enables the accurate prediction of process performance, resulting in significant cost reduction and enhancement of semiconductor manufacturing processes. This model has the potential to improve defect control and yield, thereby benefiting the semiconductor industry. Despite the limitations imposed by the limited dataset, the model demonstrated promising results, and further performance improvements are anticipated with the inclusion of additional data in future studies.

Diagnosing Time-Varying Harmonics in Low-k Oxide Thin Film (SiOF) Deposition by Using HDP CVD.

This study identified time-varying harmonic characteristics in a high-density plasma (HDP) chemical vapor deposition (CVD) chamber by depositing low-k oxide (SiOF). The characteristics of harmonics are caused by the nonlinear Lorentz force and the nonlinear nature of the sheath. In this study, a noninvasive directional coupler was used to collect harmonic power in the forward and reverse directions, which were low frequency (LF) and high bias radio frequency (RF). The intensity of the 2nd and 3rd harmonics responded to the LF power, pressure, and gas flow rate introduced for plasma generation. Meanwhile, the intensity of the 6th harmonic responded to the oxygen fraction in the transition step. The intensity of the 7th (forward) and 10th (in reverse) harmonic of the bias RF power depended on the underlying layers (silicon rich oxide (SRO) and undoped silicate glass (USG)) and the deposition of the SiOF layer. In particular, the 10th (reverse) harmonic of the bias RF power was identified using electrodynamics in a double capacitor model of the plasma sheath and the deposited dielectric material. The plasma-induced electronic charging effect on the deposited film resulted in the time-varying characteristic of the 10th harmonic (in reverse) of the bias RF power. The wafer-to-wafer consistency and stability of the time-varying characteristic were investigated. The findings of this study can be applied to in situ diagnosis of SiOF thin film deposition and optimization of the deposition process.

Hydrogen-modulated Ar/CH4 HWP-CVD for fast preparation of multi-wall carbon nanotube arrays with high specific capacitance

Two-dimensional Multiwalled Carbon Nanotube arrays (MWCNTs) were prepared by a novel high-density helicon wave plasma chemical vapor deposition (HWP-CVD) at room temperature. Preliminary studies show that the MWCNTs prepared by this method has strong orientation and is perpendicular to the substrate surface, and exhibit a highly ordered array distribution. The addition of hydrogen can effectively improve the growth rate of MWCNTs and increase the aspect ratio. The height and aspect ratio of MWCNTs can be effectively increased with the increase of growth time. Electrochemical investigation indicated that MWCNTs have high specific capacitance (1.96 mF/cm−2) and excellent rate capability (81.6%).

Application of Neural Network-Based Oxide Deposition Models to CMP Modeling

Numerous deposition processes are used in modern semiconductor manufacturing, including high-density plasma chemical vapor deposition (HDP-CVD), spin-on dielectric (SOD), flowable CVD (FCVD), and enhanced high aspect ratio processes (eHARP). Generation of high quality post-deposition surface profiles is crucial for chemical-mechanical planarization (CMP) model building, due to the complex nature of the CMP process and long-range effects in CMP. Measurements show complicated post-deposition surface profile height dependence on the underlying pattern for these deposition processes. While high-quality compact models exist for HDP-CVD and SOD processes, building compact models for FCVD and eHARP is a challenge, since they include several deposition and annealing steps, and show complicated behavior width respect to the underlying pattern. In this paper, we present the application of neural networks (NNs) to post-deposition surface profiles modeling for the above-mentioned deposition processes. Experiments showed that NNs should have at least two hidden layers and 6–10 neurons per hidden layer to capture the complexity of deposited surface profiles. The application of NNs to modeling surface profiles of deposition processes has shown that NNs provide a general approach for modeling surface profiles of deposition processes without long-range effects for CMP modeling, irrespective of the complexity of the deposition process.

In-Situ Detection Method of Abnormal Plasma Discharge in Plasma-Assisted Deposition Processes

Arc is an abnormal discharge in a plasma-processing chamber that results in high current discharge marks and particles on wafers. However, it is difficult to identify or observe it during an ongoing process. In this study, we report on the observations of plasma arcs during various plasma processes through a non-invasive optical plasma monitoring system devised for the in situ detection of abnormal discharge. The employed optical monitoring based arc detection system provides valuable indications of particle generation resulting from a charge imbalance in the chamber. The devised non-invasive and real-time method can detect such disturbances down to the order of tens of microseconds. Successful monitoring of arcs that appear in various types of plasma-assisted deposition processes are presented in this paper. We also present examples of detected arcs in various plasma processes, such as plasma-enhanced chemical vapor deposition, high density plasma-chemical vapor deposition, amorphous carbon layer deposition, and plasma-enhanced atomic layer deposition. The suggested method plays an important role for the next level of arc-detection research and plasma diagnostics applications.

The improvement of MOSFET performance by the optimization of STI HDP-CVD integration process

The integration process of shallow trench isolation (STI) deposition was systematically investigated by using high-density plasma chemical vapor deposition (HDP-CVD). Two sputtering agents, Ar and H2, were utilized with various plasma RF power conditions. The STI HDP-CVD process consisted of two steps, including liner oxide and main gap-fill depositions. For the liner oxide deposition, the usage of Ar plasma was more favorable than H2 plasma because the drift of hydrogen-ions was detrimental for the electrical property of gate oxide. In the gap-fill process, H2 plasma with high bias RF power efficiently reduced plasma charging damage (PCD) on gate oxide due to its low sputtering rate and densely filled STI. The gap-fill capability and PCD were improved by the optimized condition of STI HDP-CVD process.

Impact of hydrogen dilution on optical properties of intrinsic hydrogenated amorphous silicon films prepared by high density plasma chemical vapor deposition for solar cell applications

P-i-n single-junction hydrogenated amorphous silicon (a-Si:H) thin film solar cells were successfully fabricated in this study on a glass substrate by high density plasma chemical vapor deposition (HDP-CVD) at low power of 50 W, low temperature of 200°C and various hydrogen dilution ratios (R). The open circuit voltage (Voc ), short circuit current density (Jsc ), fill factor (FF) and conversion efficiency (η) of the solar cell as well as the refractive index (n) and absorption coefficient (α) of the i-layer at 600 nm wavelength rise with increasing R until an abrupt drop at high hydrogen dilution, i.e. R > 0.95. However, the optical energy bandgap (Eg ) of the i-layer decreases with the R increase. Voc and α are inversely correlated with Eg . The hydrogen content affects the i-layer and p/i interface quality of the a-Si:H thin film solar cell with an optimal value of R = 0.95, which corresponds to solar cell conversion efficiency of 3.85%. The proposed a-Si:H thin film solar cell is expected to be improved in performance.

Stability of polymer-dielectric bi-layers for athermal silicon photonics

Temperature sensitivity of Si based rings can be nullified by the use of polymer over-cladding. Integration of athermal passive rings in an electronic-photonic architecture requires the possibility of multi-layer depositions with patterned structures. This requires establishing UV, thermal and plasma stability of the polymer during multi-layer stacking. UV stability is enhanced by UV curing to saturation levels. However, thermal stability is limited by the decomposition temperature of the polymer. Further, robust performance in oxidizing atmosphere and plasma exposure requires a SiO(2)/SiN(x) based dielectric coatings on the polymer. This communication uses a low temperature (130°C) High Density Plasma Chemical Vapor Deposition (HDPCVD) for dielectric encapsulation of polymer cladded Si rings to make them suitable for device layer deposition. UV induced cross-linking and annealing under vacuum make polymer robust and stable for Electron Cyclotron Resonance (ECR)-PECVD deposition of 500nm SiO(2)/SiN(x). The thermo-optic (TO) properties of the polymer cladded athermal rings do not change after dielectric cap deposition opening up possibilities of device deposition on top of the passive athermal rings. Back-end CMOS compatibility requires polymer materials with high decomposition temperature (> 400°C) that have low TO coefficients. This encourages the use of SiN(x) core waveguides in the back-end architecture for athermal applications.

Measurement of mechanical stresses induced by hybrid shallow-trench-isolation for dynamic random access memory using recess channel array transistor structure

Methods of measuring mechanical stresses which are induced by hybrid shallow-trench-isolation (STI) for dynamic random access memories (DRAMs) using recess channel array transistor (RCAT) structure, are investigated. The STI was fabricated using high-density-plasma chemical-vapor-deposition (HDP-CVD) and spin-on-glass (SOG) processes. The mechanical stress at the channel region was evaluated using the subthreshold current method, and mechanical stress at the drain region was evaluated using the gate induced drain leakage current method which is proposed in this paper. Experimental results show that the SOG bottom layer induced a biaxial tensile stress in the range of 70.26-399.2MPa, while the HDP-CVD SiO2 top layer induced a biaxial compressive stress in the range of 0.220-7.291GPa. The mechanical stress varied the data retention time tret for the RCAT-structure DRAM by ~67.1%. tret had a strong correlation with the biaxial tensile stress, but had little correlation with the biaxial compressive stress.

High-Performance N2O Plasma Treated Multiwall Carbon Nanotubes Grown by Thermal Chemical Vapor Deposition

A N2O plasma post-treatment process was performed to etch the surface of MWCNTs and modify the density of MWCNTs and dope nitrogen atoms into MWCNTs in high density plasma chemical vapor deposition (HDPCVD) system. The experimental results show improved field emission properties under proper plasma conditions. The turn-on electric field decreased from 2.5 to 1.7 V/μm, and the emission current density increased from 200 to 889 μA/cm2 at an applied field of 4.8 V/μm.

Multiple-inputs Dual-outputs Process Characterization and Optimization of HDP-CVD SiO2Deposition

Accurate process characterization and optimization are the first step for a successful advanced process control (APC), and they should be followed by continuous monitoring and control in order to run manufacturing processes most efficiently. In this paper, process characterization and recipe optimization methods with multiple outputs are presented in high density plasma-chemical vapor deposition (HDP-CVD) silicon dioxide deposition process. Five controllable process variables of Top SiH<SUB>4</SUB>, Bottom SiH<SUB>4</SUB>, O<SUB>2</SUB>, Top RF Power, and Bottom RF Power, and two responses of interest, such as deposition rate and uniformity, are simultaneously considered employing both statistical response surface methodology (RSM) and neural networks (NNs) based genetic algorithm (GA). Statistically, two phases of experimental design was performed, and the established statistical models were optimized using performance index (PI). Artificial intelligently, NN process model with two outputs were established, and recipe synthesis was performed employing GA. Statistical RSM offers minimum numbers of experiment to build regression models and response surface models, but the analysis of the data need to satisfy underlying assumption and statistical data analysis capability. NN based-GA does not require any underlying assumption for data modeling; however, the selection of the input data for the model establishment is important for accurate model construction. Both statistical and artificial intelligent methods suggest competitive characterization and optimization results in HDP-CVD SiD2 deposition process, and the NN based-GA method showed 26% uniformity improvement with 36% less SiH4 gas usage yielding 20.8 Å/sec deposition rate.

Evolution of STI Gap Fill Technology

As the IC industry progresses along the ITRS roadmap, continually producing more demanding devices at each technology node, new processes are required to realize yields necessary for success. In this paper, we present and review the evolution of STI (Shallow Trench Isolation) application, and recent developments in the High-Density Plasma Chemical Vapor Deposition (HDP CVD) process and High Aspect Ratio Process(HARP) CVD process. Aspects relevant to the HDP CVD process and using different process to achieve gap filling, and planarization are discussed.

Micro-fabricated perforated polymer devices for long-term drug delivery

Fabrication techniques have been developed to produce a perforated polymer microtube as a drug delivery device. The technique consists of first forming a silicon platform with trenches and alignment marks to hold the tubes for subsequent processing. Photolithography and reactive ion etching with an inductively coupled plasma source were used to fabricate micro holes on the surface of polyimide tubes. Several materials have been used to form the etching mask, including titanium film deposited by e-beam evaporation and SiO(2) and SiN(x) films deposited by high-density plasma chemical vapor deposition (HDPCVD). Three equidistant holes of 20μm in diameter were fabricated on polyimide tubes (I.D. = 125μm). The perforated tubes were loaded with ethinyl estradiol and tested for drug release in phosphate buffered saline (pH = 7.1) at 37°C. Zero order release was observed over a period of 30days with a potential to be extended to 4years.

Micropatterning of single-walled carbon nanotube forest

In this work, high-aligned single-walled carbon nanotube (SWCNT) forest have been grown using a high-density plasma chemical vapor deposition technique (at room temperature) and patterned into micro-structures by photolithographic techniques, that are commonly used for silicon integrated circuit fabrication. The SWCNTs were obtained using pure methane plasma and iron as precursor material (seed). For the growth carbon SWCNT forest the process pressure was 15 mTorr, the RF power was 250 W and the total time of the deposition process was 3 h. The micropatterning processes of the SWCNT forest included conventional photolithography and magnetron sputtering for growing an iron layer (precursor material). In this situation, the iron layer is patterned and high-aligned SWCNTs are grown in the where iron is present, and DLC is formed in the regions where the iron precursor is not present. The results can be proven by Scanning Electronic Microscopy and Raman Spectroscopy. Thus, it is possible to fabricate SWCNT forest-based electronic and optoelectronic devices.

Advanced HDP STI Gap-Fill Development in 65nm Logic Device

High density plasma chemical vapor deposition (HDP-CVD) has been proven to be a sucessful process for shallow trench isolation (STI) gap fill in advanced CMOS device fabrication. As CMOS technology nodes continue to shrink, STI gap-fill requirement become more and more challenging. To keep pace with the stringent requirements, a novel HDP gap-fill process - Integrated Proess Modulation (IPM) has been developed to fill these aggressive structures. IPM process, which is extending from Deposition - Etch - Deposition (DED) process, is made of a serial of deposition/etch cycles, which is one of techniques to keep trench open by using NF3-based plasma dry etch before the trench nearly closed by film deposition. Based on this process model, HDP gap-fill capability has been greatly extended to 65nm and beyond. This paper summarizes the STI gap-fill development and optimization work of IPM processes

Oxide HDP-CVD Modeling for Shallow Trench Isolation

A method is proposed to model the high-density plasma chemical vapor deposition step within the shallow trench isolation module in the CMOS technology. To model a process is the first step in the design of a run-to-run system in order to reduce the lot-to-lot variability (a lot equals 25 wafers). A model is developed to control the MeanThickness and the Range of the MeanThickness (uniformity). A satisfactory model was obtained through a design of experiments.

A New Non-PRM Bumping Process by Electroplating on Si Die for Three Dimensional Packaging

A new bumping process on a Si die by electroplating without a photo-resist-mold (PRM) was assessed for the three dimensional (3D) stacking of Si dice. In this process, solder bumps were deposited selectively onto the surface of a Cu plugged-through silicon-via (TSV) in a Si die. Since lithography related processes to make a PRM for solder bumping were omitted, it can reduce the production time and cost for bumping. The substrate was a Si wafer, and TSVs were produced by deep-ion-reactive-etching (DRIE). As an insulation layer, SiO2 was formed by high-density-plasma-chemical-vapor-deposition (HDPCVD) or wet oxidation method. A Ti adhesion and an Au seed layers were deposited by sputtering. Cu was plugged into the vias by pulsed direct-current (DC) electroplating. The backside of the Si wafer was ground by chemicalmechanical-polishing (CMP). Sn bumps were electroplated on the Cu plugged vias by a current supplied through a Cu-overplated layer (COL) on the vias surface. As experimental results, wet oxidation provided a uniform SiO2 thickness through the via depth, whereas the SiO2 thickness by HDPCVD decreased with the via depth. The Ti and Au thicknesses also decreased along the via depth. In electroplating for Cu plugging,

Nanostructured diamond-like carbon films characterization

In this work, we have studied the influence of the substrate surface condition on the roughness and the structure of the nanostructured DLC films deposited by high-density plasma chemical vapor deposition. Four methods were used to modify the silicon wafers surface before starting the deposition processes of the nanostructured DLC films: micro-diamond powder dispersion, micro-graphite powder dispersion, and roughness generation by wet chemical etching and roughness generation by plasma etching. The reference wafer was only submitted to a chemical cleaning. It was possible to see that the final roughness and the sp 3 hybridization degree (that is related with the structure and chemical composition) strongly depend on the substrate surface conditions. The surface roughness was observed by AFM and SEM and the hybridization degree of the DLC films was analyzed by Raman Spectroscopy. Thus, the effects of the substrate surface on the DLC film structure were confirmed. These phenomena can be explained by the fact that the locally higher surface energy and the sharp edges may induce local defects promoting the nanostructured characteristics in the DLC films.

Multi-scale Simulations for Plasma Processing of Thin Films

An inherent challenge to achieving improvements in thin film deposition processes is that requirements at the feature scale have to be somehow "tuned in" by modifying reactor scale geometry and process parameters. The simulation approach described allows for the solution of species fluxes and energies at the wafer surface as a function of process parameters. The reactor scale model addresses coupled flow, chemistry and plasma physics such as power deposition, volumetric reactions, species transport and deposition on chamber walls. The feature scale model computes growth of the film inside a trench. The objective of this work is to develop a comprehensive model for the high-density plasma chemical vapor deposition of silicon dioxide films in an inductively coupled plasma reactor. Using gas phase and surface reaction mechanisms from literature, trends in deposition characteristics with process variables such as inductive power are compared to experimental data in a commercial reactor.

Mechanism and CHARM2 Evaluation of P-Channel Metal Oxide Semiconductor Threshold Voltage Drop during High Density Plasma Heat-up Process

Plasma damage during the plasma deposition process is one of the most critical device characteristic issues facing complementary metal oxide semiconductor field effect transistor (CMOSFET) technology. In this paper, the CHARM2 monitoring system is used to evaluate UV damage and plasma charging damage during a high density plasma chemical vapor deposition (HDP-CVD) heat-up process. As a result, the amount of UV damage and negative charging damage is increased as the HDP-CVD heat-up process source power is increased. The main cause of P-channel metal oxide semiconductor field effect transistor (PMOSFET) threshold voltage drop is UV photon facilitated gate oxide electron trapping at the gate oxide and substrate P-channel interface during the HDP-CVD heat-up process. In N-channel metal oxide semiconductor field effect transistor (NMOSFET), when negative gate voltage stress is increased, gate oxide energy bend is flattened. Electrons cannot be trapped at the gate oxide and substrate N-channel interface. Therefore, the NMOSFET threshold voltage is constant during the HDP-CVD heat-up plasma process.