High Density DRAM Research Articles

Effect of gate hard mask and sidewall spacer structures on the gate oxide reliability of W∕WNx∕poly-Si gate MOSFET for high density DRAM applications

We have studied the effects of the gate hard mask and the gate spacer nitride film on the reliability of W∕WNx∕poly-Si gated devices. When the gate hard mask nitride film is used, severe degradation of the stress-induced leakage current (SILC) and the interface trap density (Dit) characteristics are observed in the large metal-oxide-semiconductor (MOS) capacitors. On the other hand, as the devices become smaller, the effects of the hard mask nitride film are relieved. The gate spacer stack plays a more critical role in the reliability of smaller devices. The oxide∕nitride (ON) spacered devices exhibit better reliability in terms of SILC, Dit, threshold voltage (Vth) shift, and transconductance (Gm) compared to those of the nitride∕oxide∕nitride (NON) spacered ones. These behaviors are explained by the mechanical stress of the nitride films.

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer

This paper describes three circuit techniques for a DDR1/DDR2-compatible chip architecture designed for both high-speed and high-density DRAMs: 1) a dual-clock input-latch scheme, which reduces the excessive timing margin for random input commands by using a pair of latch circuits controlled by dual-phase one-shot clock signals, achieves a 0.9-ns reduction in cycle time from 3.05 to 2.15 ns; 2) a hybrid multi-oxide output buffer reduces the area penalty of the output buffer caused by compatible chip design from 1.35% to 0.3%; and 3) a quasi-shielded distributed data transfer scheme enables a 2.6-ns reduction in access time to 10.25 ns in both 2-b and 4-b prefetch operations. By using these techniques, we developed a 175.3-mm/sup 2/ 1-Gb SDRAM that operates as an 800-Mb/s/pin DDR2 or 400-Mb/s/pin DDR1.

Design and optimization of large size and low overhead off-chip caches

Large off-chip L3 caches can significantly improve the performance of memory-intensive applications. However, conventional L3 SRAM caches are facing two issues as those applications require increasingly large caches. First, an SRAM cache has a limited size due to the low density and high cost of SRAM and, thus, cannot hold the working sets of many memory-intensive applications. Second, since the tag checking overhead of large caches is nontrivial, the existence of L3 caches increases the cache miss penalty and may even harm the performance of some memory-intensive applications. To address these two issues, we present a new memory hierarchy design that uses cached DRAM to construct a large size and low overhead off-chip cache. The high density DRAM portion in the cached DRAM can hold large working sets, while the small SRAM portion exploits the spatial locality appearing in L2 miss streams to reduce the access latency. The L3 tag array is placed off-chip with the data array, minimizing the area overhead on the processor for L3 cache, while a small tag cache is placed on-chip, effectively removing the off-chip tag access overhead. A prediction technique accurately predicts the hit/miss status of an access to the cached DRAM, further reducing the access latency. Conducting execution-driven simulations for a 2 GHz 4-way issue processor and with 11 memory-intensive programs from the SPEC 2000 benchmark, we show that a system with a cached DRAM of 64 MB DRAM and 128 KB on-chip SRAM cache as the off-chip cache outperforms the same system with an 8 MB SRAM L3 off-chip cache by up to 78 percent measured by the total execution time. The average speedup of the system with the cached-DRAM off-chip cache is 25 percent over the system with the L3 SRAM cache.

Novel NAND DRAM with surrounding gate transistor (SGT)‐type gain cell

AbstractA novel NAND DRAM with SGT‐type gain cell is proposed. This SGT‐type gain cell structure is composed of an SGT and SGT‐type capacitor stacked vertically on a planar read transistor. Its cell size can be reduced to 4F2 since it can be arranged to have the cross‐point configuration. Therefore, high‐density DRAM is achieved. Since it operates as a gain cell, it is possible to obtain sufficient signal charge regardless of the stored amount. Therefore, the proposed DRAM operates at low supply voltages, where it is difficult to obtain sufficient read‐out voltage in conventional DRAM. It is shown that the novel NAND DRAM with SGT‐type gain cell achieves high‐density and low‐voltage operation. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 87(7): 1–8, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10198

New design method for tapered buffer circuit with TIS (Trench‐Isolated Transistor using sidewall gate) and its application to high‐density DRAMs

AbstractA new design method has been conceived for a buffer circuit using TIS. In the buffer circuit of a taper type with a fan‐out of 3 intended for driving a large load capacitance, a new design procedure is conceived that minimizes the pattern area without sacrificing characteristics such as power consumption. In the new design method, the “planar+TIS” method is employed, in which planar‐type transistors are used in the front stage of the buffer circuit while TIS‐type transistors are used in the latter stage. This design method is applied to a large‐capacity DRAM. Relative to the case in which conventional planar transistors are used, the chip area can be reduced by about 8% without sacrificing characteristics such as power consumption. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 87(4): 9–15, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10152

Effect of different annealing procedures on the microstructure and the electrical properties of CSD derived (Ba,Sr)TiO3 thin films.

ABSTRACTProcessing of BST thin films is becoming more and more important for microwave electronics and for its probable incorporation in future high density DRAM's. A co-relation between processing and final device characteristics is of utmost importance. Differences in microstructure and electrical properties were observed when chemical solution deposited thin films were annealed using a conventional diffusion furnace, rapid thermal annealing furnace with different heating ramps, and a hot plate for pyrolysis prior crystallization. The solution was made with the propionate route and then deposited on Pt coated silicon wafers. Cross-sectional SEM's were performed on the different films. It was found that the microstructure depended on the annealing method of the film. The electrical properties of the films were also found to vary considerably. Frequency dependence of the dielectric constant was studied. The leakage study on different films was performed at different temperatures.

Numerical analysis of alpha-particle-induced soft errors in floating channel type surrounding gate transistor (FC-SGT) DRAM Cell

This paper clarifies alpha-particle-induced soft error mechanisms in floating channel type surrounding gate transistor (FC-SGT) DRAM cells. One FC-SGT DRAM cell consists of an FC-SGT and a three-dimensional (3-D) storage capacitor. The cell itself arranges bit line (BL), storage node and body region in a silicon pillar vertically and achieves cell area of 4F/sup 2/ (F: feature size) per bit. In FC-SGT DRAM cells, the parasitic bipolar current is a major factor to cause soft errors. When an alpha particle penetrates the silicon pillar, generated electrons are collected to the storage node or BL due to the tunneling and diffusion mechanisms. On the other hand, holes are swept into the body region and accumulated. Consequently, the current flows not only in the surface but also in the entire body region due to the floating body effect. This parasitic bipolar current becomes the largest when an alpha particle penetrates the silicon pillar along the vertical axis. However, in case of FC-SGT DRAM cells, the surrounding gate structure can suppress the floating body effect compared with floating channel type SOI DRAM cells. As a result, the loss of the stored charge in the storage capacitor can be drastically decreased by using FC-SGT DRAM cell. Therefore, FC-SGT DRAM is a promising candidate for future high-density DRAMs having high soft-error immunity.

Current instabilities in dynamic random access memory storage capacitor formed with electron beam deposited Y 2 O 3 dielectric

Metal-oxide-semiconductor (MOS) storage capacitors based on electron beam deposited Y2O3 extrinsic dielectric on Si show changes in capacitance density depending on the amorphous and crystalline phases. Bias stress cycle-dependent changes in capacitance density occur due to the non-equilibrium nature of defect states at the Y2O3/Si interface after O2 annealing as a result of the emergence of a 4–8 nm thick SiO2 film at the interface. Leakage currents show instability under repeated dc bias stress, the nature and extent of which depend upon the structure of the Y2O3 gate dielectric and the polarity of dc bias. With amorphous Y2O3, leakage currents drift to lower values under gate injection due to electron trapping, and to higher values under Si-injection due to the generation of holes. Though leakage current drift is minimal for crystalline Y2O3, its magnitude increases as the energy of injected electrons from mid-gap states is low and the local field due to asperity is high. The emergence of interfacial SiO2 reduces the magnitude of Si-injection leakage current substantially, but causes transient changes resulting in switching to higher values at a threshold dc bias. Thermal detrapping of holes and reverse bias stress studies confirm that the instability of current is caused by an increase in the cathodic field from hole trapping at interface states. Leakage current instability limits the application of extrinsic high dielectric constant dielectrics in a high density DRAM storage capacitor, unless a new interface layer scheme other than SiO2 and a method to form a defect-free dielectric layer can be implemented.

Thermal Ta 2O 5––alternative to SiO 2 for storage capacitor application

Tantalum pentoxide thin layers (10–100 nm) obtained by thermal oxidation of rf sputtered Ta films on Si have been investigated with respect of their dielectric, structural and electric properties. It is established that stoichiometric Ta 2O 5 detected at the surface of the layers is reduced to tantalum suboxides in their depth. The oxide parameters are discussed in terms of a presence of an unavoidable ultrathin SiO 2 between Si and Ta 2O 5 and bond defects in both the oxide and the interface transition region. Conditions which guarantee obtaining high quality tantalum oxide with a dielectric constant of 32–35 and a leakage current less than 10 −7–10 −8 A/cm 2 at 1.5 V (SiO 2 equivalent thickness of 2.5–3 nm) are established. These specifications make the layers obtained suitable alternative to SiO 2 for high density DRAMs application.

Surface roughness reducing effect of iodine sources (CH 3I, C 2H 5I) on Ru and RuO 2 composite films grown by MOCVD

Ru and RuO 2 composite films were deposited on TiN/Ti/Si substrate by metal–organic chemical vapor deposition (MOCVD) for application as the bottom electrode of a high density DRAM capacitor. The effects of iodine sources (CH 3I, C 2H 5I) on composite films deposited at 300 °C were investigated. Iodine sources enhanced nucleation dramatically at the initial deposition stage, and the surface roughness of the films was reduced considerably. The root-mean-square (r.m.s.) surface roughness of composite films that were grown up to 1000 Å with no addition, CH 3I and C 2H 5I were 162, 48 and 38 Å, respectively. Moreover, iodine sources did not affect the orientation or deposition rate of films.

A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs

A bipolar-voltage programmable antifuse circuit scheme and bit-repair scheme are newly proposed for post package repair. For fail-bit repair, the antifuses in the proposed scheme are programmed by bipolar voltages of V/sub CC/ and -V/sub CC/, alleviating high-voltage problems such as permanent device breakdown and achieving a smaller layout area for the antifuse circuit than the previous scheme. In addition, an efficient bit-repair scheme is used instead of the conventional line-repair scheme, reducing the layout area for the redundancy bits. Also, using static latches instead of dynamic memory cells for the redundancy bits eliminates possible defects in the redundancy area, making this bit-repair scheme robust and avoiding burn-in stress issues. Through manufacturing commercial DRAM products, the yield improvement by the one-bit post-package repair reaches as much as 2.4% for 0.16-/spl mu/m triple-well 256-M SDRAM.

Characteristics of BST Thin Film Prepared by Novel Chemical Solution Deposition Method for High-Density DRAM Application

Characteristics of BST Thin Film Prepared by Novel Chemical Solution Deposition Method for High-Density DRAM Application

Characteristics of BST Thin Film Prepared by Novel Chemical Solution Deposition Method for High-Density DRAM Application

Batium strontium titanate (BST) is an important material for dynamic random access memory capacitor applications. In this work, BST thin films are prepared by the MOD method and metal-BST-metal capacitors are fabricated. The DTA and TGA analysis and FTIR analysis are carried out to study reactions of precusor during the heat-treated process. The increase of the crystallinity of films improves the dielectric constant. A 420nm BST thin film annealed at 750 obtains pure perovskite phase and has a maximum dielectric constant of 628 (at 100 kHz). The relative dielectric permittivity of (Ba x Sr 1- x )TiO 3 with various Ba/Sr ratio is measured and the optimum value of x seems to be 0.6. The leakage current density of the BST thin film is about 0.03 uA/cm 2 at 3V applied voltage.

Breakdown fields and conduction mechanisms in thin Ta 2O 5 layers on Si for high density DRAMs

The conduction mechanisms and the microstructure of rf sputtered Ta 2O 5 on Si, before and after oxygen annealing at high temperatures (873, 1123 K; 30 min) have been investigated. The as-deposited and annealed at 873 K layers are amorphous whereas crystalline Ta 2O 5 (orthorhombic β-Ta 2O 5 phase) was obtained after O 2 treatment at 1123 K. The results (electrical, X-ray diffraction, transmission electron microscopy) reveal the formation of an interfacial ultrathin SiO 2 layer under all technological regimes used. The higher (493 K) substrate temperature during deposition stimulates the formation of amorphous rather than crystalline SiO 2. It is found that the oxygen heating significantly reduces the oxide charge ( Q f <10 10 cm −2 ) and improves the breakdown characteristics (the effect is more pronounced for the higher annealing temperature). It is accompanied by an increase of the effective dielectric constant (up to 37 after 1123 K treatment). It is established that the influence of the oxygen treatment on the leakage current is different depending on the film thickness, namely: a beneficial effect for the thinner and a deterioration of leakage characteristics for thicker (80 nm) films. A leakage current density as low as 10 −7 A/cm 2 at 1 MV/cm applied field for 26 nm annealed layers has been obtained. The current reduction is considered to be due to a removal by annealing of certain structural nonperfections present in the initial layers. Generally, the results are discussed in terms of simultaneous action of two opposite and competing processes taking place at high temperatures––a real annealing of defects and an appearance of a crystal phase and/or a neutral traps generation. The contribution of the neutral traps also is involved to explain the observed weaker charge trapping in the as-fabricated films compared to the annealed ones. The conduction mechanism of the as-deposited films is found to be of Poole–Frenkel (PF) type for a wide range of applied fields. A change of the conduction mechanism for the annealed films at medium fields (0.8–1.3 MV/cm) is established. This transition from PF process to the Schottky emission limited current is explained with an annealing of bulk traps (oxygen vacancies and nonperfect bonds). It is concluded that the dominant conduction mechanism in the intermediate fields can be effectively controlled by appropriate technological steps.

Analysis of retention tail distribution induced by scaled shallow trench isolation for high densityDRAMs

Analysis of retention tail distribution induced by scaled shallow trench isolation for high densityDRAMs

Photo-induced growth of dielectrics with excimer lamps

The underlying principles and properties of vacuum ultraviolet (VUV) and ultraviolet (UV) radiation (excimer lamps), generated by a dielectric barrier discharge in a rare-gas (Rg) or a mixture of Rg and halogen, are discussed. Compared with conventional sources, these excimer lamps offer narrow-band radiation at various wavelengths from 108–354 nm and over large areas with high efficiencies and high power densities. The variety of available wavelengths offers an enormous potential for new industrial applications in materials processing. Previously, photo-oxidation of silicon, germanium and silicon–germanium and photo-deposition of single- and multi-layered films of silicon oxide, silicon nitride, and silicon oxynitride have been demonstrated by using excimer lamps. This paper reviews the progress on excimer lamp-assisted growth of high dielectric constant (Ta2O5, TiO2 and PZT) and low dielectric constant (polyimide and porous silica) thin films by photo-CVD and sol–gel processing, summarizes the properties of photo-induced growth of Ta2O5 films and discusses the effect and mechanism of low temperature UV annealing with 172 nm radiation. Metal oxide semiconductor capacitors based on the photo-induced Ta2O5 films grown directly on Si at low temperatures exhibit excellent electrical properties. Leakage current densities as low as 5.2×10−7 Acm−2 and 2.41×10−7 Acm−2 at 1 MVcm−1 have been achieved for the as-grown Ta2O5 films deposited by photo-induced sol–gel processing and photo-CVD, respectively-several orders of magnitude lower than for any other as-grown films prepared by any other technique. A subsequent low temperature (400°C) UV annealing step improves these to 10−8 Acm−2. These values are comparable to those only previously achieved for films annealed at high temperatures between 600°C and 1000°C. These properties make the photo-induced growth of Ta2O5 layers suitable alternative to SiO2 for high density DRAM application.

A high-density DRAM cell with built-in gain stage

A high-density DRAM cell is proposed with a built-in vertical gain device topology. Due to the vertical built-in gain device, this cell exhibits increased reading speed, elongated refresh period, low-power oriented operation, and minor layout area penalty.

Junction leakage current degradation under the off-state bias-temperature stress: a new reliability assessment method for high-density DRAMs

A new reliability assessment method on retention time failure for high-density DRAMs under off-state bias-temperature (B-T) stress was suggested and investigated using the well-known gated-diode test pattern. The transistor junction leakage current degradation, total junction leakage current especially including gate-induced drain leakage (GIDL) component, under the off-state B-T stress was found to be more sensitive than widely-used gate-oxide degradation under the Fowler-Nordheim (F-N) tunneling stress. The off-state bias stress also gives significantly higher degradation on the gate-oxide stress-induced leakage current (SILC) than F-N tunneling current stress. The features of the off-state B-T stress which gives stress to almost all transistor leakage components and the mechanism of the junction leakage current degradation under the off-state bias condition were discussed.

Channel engineering using RTA prior to the gate oxidation for high density DRAM with single gate CMOS technology

A non-uniform lateral boron profile along the channel width is observed in a buried-channel p-MOSFET and a memory cell transistor when BF 2 implantation is applied at the dose of ∼10 13 cm −2 to form a channel. SIMS profile analysis and two-dimensional simulation results show that this abnormal profile is formed by transient enhanced diffusion (TED) due to BF 2 implantation damage during gate oxidation process. It is found that RTA process just prior to the gate oxidation is useful to eliminate the TED of boron so that inverse narrow width effect, short channel effect and threshold voltage fluctuation are remarkably improved in a buried-channel p-MOSFET. In addition, the RTA process can also reduce BF 2 implantation dose without decreasing threshold voltage by the suppression of boron diffusion in a cell transistor. Therefore, the retention time of DRAM can be enhanced by reducing space charge region field in a cell transistor due to lower boron concentration compared with a conventional device.

2.4F/sup 2/ memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM

This paper proposes 2.4F/sup 2/ memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM. One unit of the S-SGT DRAM is formed by stacking several SGT-type cells in series vertically. The SGT-type cell itself arranges gate, source, drain and plate on a silicon pillar vertically. Both gate and plate electrode surround the silicon pillar. Subsequently applied trench etching and sidewall spacer formation during S-SGT DRAM formation causes a step-like silicon pillar structure. Due to these steps, gate, plate and diffusion layer in one S-SGT DRAM unit are fabricated vertically by a self-aligned process. The cell size dependence of the self-aligned-type S-SGT DRAM was analyzed with regard to the above step widths and the number of cells in one unit. As a result, the cell design for minimizing the cell size of this device has been formulated. By using the proposed cell design, it is demonstrated by process simulation that the S-SGT DRAM in 0.5 /spl mu/m design rule can achieve a cell size of 2.4F/sup 2/, which is half of the cell size of a conventional SGT DRAM cell (4.8F/sup 2/). Therefore, the S-SGT DRAM is a promising candidate for future ultra high density DRAMs.