High Current Drivability Research Articles

Performance Comparison of Ultrathin Fully Depleted Silicon-on-Insulator Inversion-, Intrinsic-, and Accumulation-Mode Metal–Oxide–Semiconductor Field-Effect Transistors

This work demonstrates the performance comparison of ultrathin fully depleted (FD) silicon on insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) with various structures. The current drivability and immunity to the short channel effect are analyzed for FD-SOI n-channel MOSFETs (nMOSFETs) with various SOI layer thickness and SOI layer dopant concentrations based on the device simulation study. The SOI layer dopant concentrations are widely varied from conventional inversion-mode MOSFET, undoped-mode (intrinsic-mode) to the accumulation-mode MOSFET, where the accumulation-mode MOSFETs has the same dopant type in SOI layer as those of the source and the drain regions. The results suggest that the short channel effect immunity becomes comparable among various SOI layer dopant concentrations when SOI layer thickness is less than 10 nm. The current drivability is higher in the order of accumulation-, intrinsic-, and inversion-mode MOSFETs, and the mechanism of the current drivability increase is explained. In addition, accumulation-mode MOSFETs with polycrystalline silicon (poly-Si) gate electrode can maintain their high current drivability even for short channel generation because the gate capacitance decrease due to the poly-Si depletion effect does not arise. Thus, accumulation-mode MOSFETs can maximize the performance of the ultrathin FD-SOI MOSFETs.

Recessed Channel Fin Field-Effect Transistor Cell Technology for Future-Generation Dynamic Random Access Memories

A new bulk fin field-effect transistor (bulk FinFET) with a recessed channel structure is proposed as a future dynamic random access memory (DRAM) cell transistor following the recess-channel-array transistor (RCAT). An enlarged effective channel length improves the relationship between off-state channel leakage (Ioff) and gate-induced drain leakage (GIDL) current, which correspond to the static and dynamic retention characteristics of a DRAM chip. The high current drivability of FinFET is maintained even with a recessed channel. A recessed-channel FinFET (RC-FinFET) shows excellent DC characteristics (subthreshold swing, drain-induced barrier lowering and body-bias effect) and longer retention time than a conventional local-damascene FinFET (LD-FinFET).

High-performance top and bottom double-gate low-temperature poly-silicon thin film transistors fabricated by excimer laser crystallization

In this work, high-performance low-temperature poly-silicon (LTPS) thin film transistors (TFTs) with double-gate (DG) structure and lateral grain growth have been demonstrated by excimer laser crystallization (ELC). Therefore, the DG TFTs with lateral silicon grains in the channel regions exhibited better current–voltage characteristics as compared with the conventional solid-phase crystallized (SPC) poly-Si double-gate TFTs or conventional ELC top-gate (TG) TFTs. The proposed ELC DG TFTs ( W/ L = 1.5/1.5 μm) had the field-effect-mobility exceeding 400 cm 2/V s, on/off current ratio higher than 10 8, superior short-channel characteristics and higher current drivability.

High-Performance Short-Channel Double-Gate Low-Temperature Polysilicon Thin-Film Transistors Using Excimer Laser Crystallization

In this letter, high-performance low-temperature polysilicon thin-film transistors (TFTs) with double-gate (DG) structure and controlled lateral grain growth have been demonstrated by excimer laser crystallization. Via a proper excimer laser condition, along with the a-Si step height beside the bottom gate, a superlateral growth of Si was formed in the channel length plateau. Therefore, the DG TFTs with lateral silicon grains in the channel regions exhibited better current-voltage characteristics, as compared with the conventional top-gate ones. The proposed DG TFTs ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> = 1/1 mum) had the field-effect mobility exceeding 550 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vmiddots, an on/off current ratio that is higher than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> , superior short-channel characteristics, and higher current drivability. In addition, the device-to-device uniformity could be improved since grain growth could be artificially controlled by the spatial plateau structure.

High-Gain Arsenic-Rich n-p-n InP/GaAsSb DHBTs With $F_{T} ≫ \hbox{420}\ \hbox{GHz}$

Type-II n-p-n InP/GaAsSb/InP double heterostructure bipolar transistors (DHBTs) that are fabricated by optical lithography with a 0.6 times 5 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> emitter on a 20-nm compositionally uniform GaAsSb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> Sb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> , carbon-doped base with x = 0.60 and a 75-nm InP collector show current-gain cutoff frequencies as high as 423 GHz at 10 mA/mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and feature a BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEO</sub> = 4 V. The pseudomorphic As-rich InP/GaAsSb DHBTs feature a high maximum dc current gain of > 160, owing to the reduction of the type-II conduction band discontinuity DeltaE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> and the associated recombination at the InP/GaAsSb emitter-base interface. This brief demonstrates that the InP/GaAsSb DHBT technology can combine high gain, wide bandwidths, high-current drivability, and structural simplicity.

Performance Boost Using a New Device Structure Design for SOI MOSFETs Beyond 25nm Node

We demonstrate that very high performance ultra short-channel MOS transistors can be realized in accumulation mode SOI MOSFETs benefited from device structure with higher current drivability and a good suppression of degradation resulted from the gate electrode depletion. Furthermore, we reveal that the short channel effect is suppressed in accumulation mode devices by thinning the SOI layer and BOX thicknesses with both the polysilicon gate electrode and metal gate.

43.3: Integration of Reliability with High Current Drivability by using SELAX Technology for High-Resolution (&gt;300 ppi) System-in-Displays

High-resolution (>300 ppi) system-in-displays have been developed by using mixed low-voltage/high-voltage poly-silicon TFTs. That is, ELC TFTs are used for the display circuits with high-voltage endurance, and SELAX TFTs are used for the low-power, high-performance display circuits. In this hybrid TFT, the SELAX TFTs successfully integrate reliability with high current drivability.

MOSFETs with ultrashallow junction and minimum drain area formed by using solid-phase diffusion from SiGe

An advanced CMOS structure, in which a raised source/drain and contact windows formed over the field oxide, was fabricated. Ultrashallow junction formation using solid-phase diffusion from doped SiGe layers was used to fabricate MOSFETs. These MOSFETs demonstrated excellent short-channel characteristics and 70%-80%-reduced parasitic drain-junction capacitance. They have ultrashallow junctions with a depth of 25 nm and a low source/drain extension (SDE) resistance: 350 /spl Omega//sq (NMOSFETs) and 390 /spl Omega//sq (PMOSFETs). The isotropic diffused SDE structure was formed by using solid-phase diffusion, which could effectively form a shallow junction and a suitable overlap between gate and SDE. This structure results in good short-channel characteristics and high current drivability.

Ga 0.51 In 0.49 P/In x Ga 1−x As/GaAs lattice-matched and strained doped-channel field-effect transistors grown by gas source molecular beam epitaxy

Recently, it was demonstrated that doped-channel field-effect-transistor (DCFET) structure has the advantages of high breakdown voltage, high current drivability, and high turn on voltage. Therefore, a series of lattice-matched and strained Ga0.51In0.49P/InxGa1−xAs/GaAs (0⩽x⩽0.22) DCFETs were studied in order to find the optimized structure. Through dc and microwave measurements, we observed that the introduction of a 150-Å-thick strained InxGa1−xAs (0.15⩽x⩽0.22) channel can enhance device performance, compared to the lattice-matched one (x=0). The optimized performance of transconductance (gm), current-gain cutoff frequency (ft) and maximum oscillation frequency (fmax) all occurred when indium content x was between 0.15 and 0.20 for devices with 1-μm-long gate and these optimized results are comparable to those state-of-the-art results of pseudomorphic high electron mobility transistors. We also found that DCFETs are very ideal for single-voltage-supply operation. Degradation of device performance was observed for larger indium content (x=0.22), which is associated with strain relaxation in this highly strained channel. Experimental results showed that Ga0.51In0.49P/InxGa1−xAs/GaAs DCFETs with indium content x between 0.15 and 0.20 were very suitable for microwave high power device applications.

Subquarter-micrometer Dual Gate Complementary Metal Oxide Semiconductor Field Effect Transistor with Ultrathin Gate Oxide of 2 nm

The high performance of 0.25 µm dual gate complementary metal oxide semiconductor with an ultrathin gate oxide of 2 nm is demonstrated for low-voltage logic applications. Boron penetration can be effectively suppressed by the nitrogen implantation technique, even if the gate oxide film is reduced to 2 nm. It is confirmed that N-channel and P-channel metal oxide semiconductor field effect transistors (MOSFETs) with high current drivability can be realized by the thin gate oxide, although the transconductance is not inversely proportional to the gate oxide thickness due to the increase in the effect of the inversion capacitance and the gate depletion. The inverter delay time with the aluminum interconnect load is markedly improved by the highly drivable MOSFETs with thin gate oxide, especially at low-voltage operation. Furthermore, hot carrier degradation of N-channel MOSFETs can be suppressed by reducing the gate oxide thickness. However, it was found that the hot carrier degradation of P-channel MOSFETs is enhanced in the thin gate oxide region under channel hot hole injection.

Counter-Doped Surface Channel Metal-Oxide-Semiconductor Field-Effect Transistor with High Current Drivability and Steep Subthreshold Slope

A metal-oxide-semiconductor field-effect transistor (MOSFET) with a novel channel structure called a counter-doped surface channel (CDSC) is proposed. A unique characteristic of the CDSC MOSFET is that the channel current still exists at the surface, even though the counter-doped layer is formed. Experimental results confirm that the CDSC pMOSFET using an n+ poly-Si gate has the highest current drivability and the steepest subthreshold slope while maintaining a good short-channel-effect immunity compared with the surface channel (SC) and buried channel (BC) pMOSFET. The delay time with the CDSC pMOSFET represents 1.34-fold improvement in comparison to that with the SC pMOSFET.

Fabrication of gate-all-around MOSFET by silicon anisotropic etching technique

A novel fabrication process of gate-all-around (GAA) MOSFETs using an anisotropic etching technique has been proposed. In this technology, the channel width of the GAA device is not limited by the lithography resolution and the density of the wire channel is doubled. The two-dimensional device simulation shows much better short channel immunity of GAA devices than that of single gate and double gate SOI MOSFETs. The simulation also shows that the new GAA devices we have proposed have higher current drivability than the conventional GAA and single gate SOI devices.

High Performance 0.2 µm Dual Gate Complementary MOS Technologies by Suppression of Transient-Enhanced-Diffusion using Rapid Thermal Annealing

Rapid thermal annealing (RTA) before the low temperature process is introduced in the 0.2 µm dual gate complementary metal oxide semiconductor (CMOS) process and its effect has been systematically investigated. Channel profiles of boron and phosphorus remain steep by the additional RTA process before gate oxidation, as seen by using secondary ion mass spectrometry and a simulation with the point defect based diffusion model. The most effective temperature to suppress transient-enhanced-diffusion (TED) is 900–1000°C, which can be remarkably suppressed by a 30 s treatment in the case of 900°C RTA. A steep channel profile decreases the threshold voltage and increases the transconductance. Shallow source/drain extension profiles of BF2 and phosphorus can be fabricated by an additional RTA process before sidewall spacer film deposition, which can improve the threshold voltage lowering. Consequently, a high current drivability of a 0.2 µm CMOS has been achieved by the suppression of TED using two additional RTA processes.

A new field-effect transistor based on the metal–insulator transition

We propose a field-effect tunnel transistor based on the metal–insulator transition. The principle of the switching is the metal–insulator transition, which occurs at the sheet resistance RQ (∼h/e2=25.8 kΩ). The modulation of the sheet resistance around RQ by the control gates can be magnified by the phase transition. As a result, high transconductance and high current drivability more than 10 times greater than the ultimate silicon metal-oxide-semiconductor transistors are obtained. The device is a thin-film silicon-on-insulator structure with dual gates, one on each side of the channel. A very thin granular metal film is deposited on the Si layer. Each metal island forms a Schottky contact with the Si layer, which is completely depleted. The electrons in the metal tunnel between the islands through the Si. The metal film can have a higher Coulomb gap and current drivability than is obtained with a single tunnel junction. A temperature of less than 1/20 of the Coulomb gap energy is required to reduce the leakage current by three orders of magnitude with the Coulomb blockade mechanism. Using the Wentzel–Kramers–Brillouin approximation, we calculated the tunneling probability between the islands and evaluated the sheet resistance of the metal film. Changing the gate voltage can modulate the sheet resistance in spite of the very narrow spacing between the islands. In the high resistance regime, the Coulomb blockade can operate and the resistance is three orders of magnitude higher than the bare tunnel resistance. In the ‘‘on’’ state, on the other hand, a very low sheet resistance of less than 1 kΩ per square is obtained.

0.3-μm mixed analog/digital CMOS technology for low-voltage operation

A 0.3-/spl mu/m mixed analog/digital CMOS technology for low-voltage operation has been demonstrated, including a new MOSFET structure with laterally doped buried layer (LDB) and a double-polysilicon capacitor with low voltage coefficient. The LDB-structure MOSFET provides constant threshold voltage which is independent of channel length, high current drivability 10% over that of a conventional structure, and low junction capacitance which is less than 1/2 that of the conventional structure. The double-polysilicon capacitor achieves a voltage coefficient of 1/10 that of a conventional capacitor by introducing arsenic ion implantation to the top polysilicon plate and a Si/sub 3/N/sub 4/ capacitor-insulator, despite the insulator thickness being scaled down to oxide-equivalent 20 nm.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Sub-half-micrometer concave MOSFET with double LDD structure

The double lightly doped drain concave (DLC) MOSFET has been developed for sub-half-micrometer MOSFETs which can operate at a 5-V supply voltage. This structure has an impurity profile of n/sup +/-n/sup -/-p/sup -/-p along the sidewall of the groove. It is found that the DLC MOSFET has excellent characteristics, such as high drain sustaining voltage, less short-channel effect, high current drivability, and high reliability, due to the double LDD concave structure. The DLC MOSFET is one of the most promising device structures for sub-half-micrometer MOSFETs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Source-to-drain nonuniformly doped channel (NUDC) MOSFET structures for high current drivability and threshold voltage controllability

The source-to-drain nonuniformly doped channel (NUDC) MOSFET has been investigated to improve the aggravation of the V/sub th/ lowering characteristics and to prevent the degradation of the current drivability. The basic concept is to change the impurity ions to control the threshold voltage, which are doped uniformly along the channel in the conventional channel MOSFET, to a nonuniform profile of concentration. The MOSFET was fabricated by using the oblique rotating ion implantation technique. As a result, the V/sub th/ lowering at 0.4- mu m gate length of the NUDC MOSFET is drastically suppressed both in the linear region and in the saturation region as compared with that of the conventional channel MOSFET. Also, the maximum carrier mobility at 0.4- mu m gate length is improved by about 20.0%. Furthermore, the drain current is increased by about 20.0% at 0.4- mu m gate length. >

High performance characteristics in trench dual-gate MOSFET (TDMOS)

It is experimentally shown that there is high current drivability and high reliability in a TDMOS, compared with those in the conventional trench transistor. The authors explain the high performance mechanism of TDMOS by using experimental data and two-dimensional device simulation. It has recently been observed that drain currents of the TDMOS are enhanced compared to those of a conventional trench transistor. The higher current in TDMOS is due to the increase of electron charge density in the inversion layer, resulting from reduced depletion layer charge caused by the gate bias. However, impact ionization of the TDMOS is much smaller than that of a single-gate trench transistor, resulting in a higher reliability in the TDMOS. Moreover, the substrate bias sensitivity of V/sub th/ is very low in the TDMOS structure. These effects are caused by the reduction in the depletion layer charge in the TDMOS, compared to that in the single-gate trench transistor.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Small-signal impedance of GaAs-AlxGa1−x as resonant tunnelling heterostructures at microwave frequency

The microwave impedance of high current drivability GaAs-AlxGa1−x As resonant tunnelling heterostructures in negative differential resistance conditions is measured. Using an equivalent circuit model that accounts for the frequency variation of the impedance, circuit elements corresponding to physical phenomena present in the device are identified.

IVA-6 New high current drivability MIS-like FET's utilizing a highly doped thin GaAs channel

IVA-6 New high current drivability MIS-like FET's utilizing a highly doped thin GaAs channel