High Breakdown Electric Field Research Articles

Atomic layer deposition of Y2O3 as high-k dielectrics by using a heteroleptic yttrium precursor and water

Atomic layer deposition (ALD) of Y2O3 thin films was performed on Si substrate by pulsing an unconventional heteroleptic yttrium precursor Y(MeCp)2(Me2Pz) and H2O alternatively. The thin film grew 0.26–0.28 Å per cycle at relatively low temperature of 195–225 °C in a self-limiting manner with negligible nucleation delay, and is close to stoichiometric (O/Y = 1.48, C, 2.56 at%; N, 1.81 at%) in as-deposited form. Integration of the post-annealed ALD Y2O3 film in a metal oxide semiconductor (MOS) capacitor structure exhibits representative electrical properties including a high dielectric constant k of 11.4, high electrical breakdown field of 6.1 MV cm−1 and low leakage current density of 9.1 × 10−8 A cm−2 at − 2 MV cm−1.

High Energy Density in All-Organic Polyimide-Based Composite Film by Doping of Polyvinylidene Fluoride-Based Relaxor Ferroelectrics.

Recently, due to the advantages of superior compatibility, fewer interface defects, and a high electric breakdown field, all-organic dielectric composites have attracted significant research interest. In this investigation, we produced all-organic P(VDF-TrFE-CFE) terpolymer/PI (terp/PI) composite films by incorporating a small amount of terpolymer into PI substrates for high energy density capacitor applications. The resulting terp/PI-5 (5% terpolymer) composite films exhibit a permittivity of 3.81 at 1 kHz, which is 18.7% greater than that of pristine PI (3.21). Furthermore, the terp/PI-5 film exhibited the highest energy density (9.67 J/cm3) and a relatively high charge-discharge efficiency (84.7%) among the terp/PI composite films. The energy density of the terp/PI-5 film was increased by 59.8% compared to that of the pristine PI film. The TSDC results and band structure analysis revealed the presence of deeper traps in the terp/PI composites, contributing to the suppression of leakage current and improved charge-discharge efficiency. Furthermore, durability tests confirm the stability of the composite films under extended high-temperature exposure and cycling, establishing their viability for practical applications.

Ultrahigh breakdown strength of NaNbO3‐based dielectric ceramics for high‐voltage capacitor application

AbstractDielectric ceramics have attracted significant attention in power electronic systems, owing to their exceptional charging and discharging speeds, as well as their high power density. However, simultaneously achieving a high recoverable energy density (Wrec) and high efficiency (η) in high‐voltage dielectric ceramics remains a challenge for applications where a high breakdown electric field (Eb) is required. In this study, high‐quality (1 – x)NaNbO3–xSr0.7Bi0.2(Mg1/3Nb2/3)O3 [(1 – x)NN–xSBMN] ceramics were prepared based on an optimization strategy combining phase structure with microstructural regulation. A quasilinear P–E loop with negligible hysteresis was realized in the ceramic with x = 0.4, excellent Wrec of 5.61 J/cm3, and high η of 85.1% obtained at a largely improved Eb of 710 kV/cm. To the best of our knowledge, the Eb of 710 kV/cm is one of the highest values achieved in dielectric ceramics to date. The noticeable reduction in grain size (∼0.95 µm) and increased bandgap improve the Eb to an ultra‐high level, which is a crucial factor in high energy storage density. The coexistence of a few antiferroelectric phases and the dominant paraelectric phase is the structural origin of the comprehensive energy‐storage performance improvement. Therefore, our research develops a unique approach to unleash the potential in NaNbO3‐based ceramics, holding great promise for application in high‐voltage dielectric capacitors.

Remarkable energy-storage density together with efficiency of above 92% in high-entropy ferroelectric ceramics

Recently, the use of “entropy engineering” to form high-entropy ceramic dielectric materials is considered to be an effective means to break through the traditional doping which modified local structures. However, the low energy storage efficiency (η) of most high-entropy ceramics cannot match their excellent energy storage density (Wrec). This work is the first to combine scheelite structure (SmTaO4) with high-entropy perovskite structure ((NaBiBaSrCa)0.2TiO3). On the one hand, the superposition of multiple structures makes the inherent lattice distortion and sluggish diffusion of high-entropy materials more obvious, thus playing a role in refining grains, reducing leakage current density, and obtaining a high breakdown electric field (Eb). On the other hand, the introduction of donor elements inhibits the generation and migration of oxygen vacancies, reducing losses to improve η and Eb. Ultimately, the goal of obtaining a remarkable Wrec (5.6 J/cm3) and η (92.2%) at 445 kV/cm was successfully achieved. This work offers a practical approach to attain superior overall performances in high-entropy ceramics.

Interface-engineering-enhanced energy storage performance of (Na0.8K0.2)0.5Bi4.5Ti4O15/Bi4LaTi3.5Mg0.5O15 multilayer film capacitors

Dielectric capacitors are vital components in advanced electrical power systems due to their high power density. However, how to improve their comparatively low energy density is still a major challenge. In this work, we designed a dielectric capacitor with a multilayer structure by inserting different numbers of ferroelectric (Na0.8K0.2)0.5Bi4.5Ti4O15 (NKBT) layers into relaxor ferroelectric Bi4LaTi3.5Mg0.5O15 (BLTM). Through the regulation of interface engineering, that is, the joint effects of electrical field amplifying, interlayer coupling, and block layer at the interface, enhancing the energy storage density and breakdown field in (NKBT/BLTM)N capacitors. A giant energy density (Wrec) of 81.2 J/cm3 and a high breakdown electric field of 4074 kV/cm are achieved in capacitors with N = 4. Consequently, interface engineering can be promoted as a universal route to optimize the energy storage performance of dielectric capacitors.

Facile synthesis of β-Ga2O3 based high-performance electronic devices via direct oxidation of solution-processed transition metal dichalcogenides

Gallium oxide (Ga2O3) is a promising wide bandgap semiconductor that is viewed as a contender for the next generation of high-power electronics due to its high theoretical breakdown electric field and large Baliga’s figure of merit. Here, we report a facile route of synthesizing β-Ga2O3 via direct oxidation conversion using solution-processed two-dimensional (2D) GaS semiconducting nanomaterial. Higher order of crystallinity in x-ray diffraction patterns and full surface coverage formation in scanning electron microscopy images after annealing were achieved. A direct and wide bandgap of 5 eV was calculated, and the synthesized β-Ga2O3 was fabricated as thin film transistors (TFT). The β-Ga2O3 TFT fabricated exhibits remarkable electron mobility (1.28 cm2 Vs−1) and a good current ratio (I on/I off) of 2.06 × 105. To further boost the electrical performance and solve the structural imperfections resulting from the exfoliation process of the 2D nanoflakes, we also introduced and doped graphene in β-Ga2O3 TFT devices, increasing the electrical device mobility by ∼8-fold and thereby promoting percolation pathways for the charge transport. We found that electron mobility and conductivity increase directly with the graphene doping concentration. From these results, it can be proved that the β-Ga2O3 networks have excellent carrier transport properties. The facile and convenient synthesis method successfully developed in this paper makes an outstanding contribution to applying 2D oxide materials in different and emerging optoelectronic applications.

A Two-Dimensional Computer-Aided Design Study of Unclamped Inductive Switching in an Improved 4H-SiC VDMOSFET.

Due to its high thermal conductivity, high critical breakdown electric field, and high power, the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has been generally used in industry. In industrial applications, a common reliability problem in SiC MOSFET is avalanche failure. For applications in an avalanche environment, an improved, vertical, double-diffused MOSFET (VDMOSFET) device has been proposed. In this article, an unclamped inductive switching (UIS) test circuit has been built using the Mixed-Mode simulator in the TCAD simulation software, and the simulation results for UIS are introduced for a proposed SiC-power VDMOSFET by using Sentaurus TCAD simulation software. The simulation results imply that the improved VDMOSFET has realized a better UIS performance compared with the conventional VDMOSFET with a buffer layer (B-VDMOSFET) in the same conditions. Meanwhile, at room temperature, the modified VDMOSFET has a smaller on-resistance (Ron,sp) than B-VDMOSFET. This study can provide a reference for SiC VDMOSFET in scenarios which have high avalanche reliability requirements.

Impact of Parasitic Gate Capacitance on RF Performance in GaN-Based HEMTs for X-Band Applications

GaN-based high-electron-mobility transistors (HEMTs) are intensively researched for high-power radio frequency (RF), low noise, and aerospace applications, thanks to their high breakdown electric field, high carrier mobility and density at the hetero-interface, and wide bandgap [1-2]. For the improvement of RF performance, various approaches have been reported, including T-gate structure [3-4], surface passivation [5], n+-regrown source and drain contact [6], thin barrier structure [7], and graded-channel [8]. Among them, the T-gate structure has been extensively employed for the reduction of the gate resistance (Rg ) and thereby improvement of the RF performance. However, the usage of the wide T-gate structure enlarges parasitic gate capacitance components, which deteriorates the RF performance. As a result, one should pay careful attention to the dimension of the wide T-gate structure to reduce Rg as much as possible, not to enlarge the parasitic gate capacitance components. This motivates us to explore the optimum dimension of the wide T-gate structure in GaN-based HEMTs for X-band RF applications.To investigate the detailed impact of the gate resistance and parasitic gate capacitance components, we fabricated LG = 0.15 μm GaN-based HEMTs with various dimensions of the T-gate head from 0.5 to 0.8 μm during an e-beam lithography process step. The unit gate width (WG ) and number of gate finger (NF ) were 100 μm and 2, respectively.For comparison of the device characteristics with respect to the dimension of the gate head, DC and RF measurements were conducted for the fabricated GaN-based HEMTs with various dimensions of T-gate head. The DC characteristics in terms of the threshold voltage (VTH ), the maximum transconductance (gm,max ), and the saturation drain current (Id,sat ) were almost identical, regardless of the dimension of the T-gate head. On the contrary, the current-gain cut-off frequency (fT ) and maximum oscillation frequency (fMAX ) were improved by 26.5% and 21.0%, respectively, when the T-gate head size was reduced from 0.8 to 0.5 μm.In an effort of explore the origin of the dependence of the T-gate head on the RF performance, we have carried out small-signal modeling to extract the parasitic gate capacitance and gate resistance components from the measured RF data. As the T-gate head size was reduced from 0.8 to 0.5 μm, the gate-source parasitic capacitance component (Cgs_par ) was reduced by 19%, while the gate resistance component was increased by 32%. In our device design and fabrication, it turned out that the reduction of Cgs_par was more beneficial than the increase of Rg , leading to the improved RF performance with the gate head size decrease.In this work, our systematic research revealed that, unlike earlier reports [3-4], the reduction of the parasitic gate capacitance was essential for the improvement of the RF performance as opposed to the reduction of the gate resistance in LG = 0.15 μm GaN-based HEMTs for X-band RF applications. Acknowledgement This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MIST) (No. NRF-2021M3C1C3097672).

Novel T-Shaped Gate Structure of AlGaN/GaN HEMTs on Si for RF Application

Due to the high electron saturation velocity and breakdown electric field, GaN-based high electron mobility transistors (HEMTs) have been widely used in high frequency and power application, such as telecommunication, satellite communication, and radar system [1]. Since first demonstration of AlGaN/GaN HEMTs in 1993 [2], the RF performance of these device has continuously improved by the progress on epitaxy and device scaling technology [3].The current gain cut-off frequency (fT) and the maximum oscillation frequency (fmax) from the small-signal equivalent circuit of the HEMT are derived by the following equations [4].From these equations, it can be concluded that in order to achieve high frequency operation, HEMTs should be designed with a T-shaped gate structure that simultaneously achieves low gate resistance (Rg) and low parasitic capacitance (Cgs and Cgd). However, there are complex fabrication processes to form the T-shaped gate. Typically, the T-shaped gate structure is implemented through electron beam lithography process using a tri-layer resist such as PMMA/PMGI/PMMA, which requires multiple exposures or developments. Multiple exposures can cause overlay errors that can significantly affect the T-shaped gate with smaller gate lengths [5]. Also, it is difficult to obtain an undercut structure that enables a good lift-off and guarantees a high yield due to the need for precise dose control. In addition, since the T-shaped gate has an unstable structure in which a narrow foot supports the weight of a wide head, the gate may collapse during a subsequent process.In this work, we fabricated a novel T-shaped gate using the negative e-beam resist HSQ, which offers a simple T-shaped gate fabrication process. The HSQ that was exposed to e-beam is located underneath the gate head and on both sides of the gate foot in our novel T-shaped gate design, providing a robust structure. The HSQ-assisted gate HEMTs exhibit comparable DC/RF performance compared to conventional T-shaped gate HEMTs. Acknowledgement This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MIST) (No. NRF-2021M3C13097672).

(Invited) Application of 3D in-Situ X-Ray Visualization to Track the Formation of Dislocation Clusters during PVT Growth of SiC

SiC has become the key player among wide bandgap semiconductors for power electronic applications. Since the first description of the physical vapour transport (PVT) growth process of SiC by Tairov and Tsvetkov (J. Crystal Growth, 43, 209(1978)), there has been steady progress in SiC-based crystal growth, epitaxy and device processing. The success of SiC compared to Si is related to its superior material properties such as extremely high electrical breakdown field and high thermal conductivity compared to the standard silicon counterpart. In addition, SiC device processing utilises much of the standard Si processing equipment. A major reason for the success of SiC in power electronic applications compared to other wide bandgap counterparts such as GaN, Ga2O3 and diamond is related to the availability of large diameter SiC wafer materials (150mm = standard, 200mm = developped). Bulk SiC growth is now a very well developed process with comparatively high yields. The extraordinary physical properties also include obstacles related to the strong chemical bonding and complex phase diagram of the material, which pose challenges to the growth process. Therefore, there are still a number of open questions related to the nucleation, progression and termination of the bulk growth process that require fundamental research in materials science and technology.The aim of this presentation is (i) to give an overview of the state-of-the-art PVT growth process and (ii) to discuss a current research topic dealing with the early stage of the growth process and the defect formation that can occur during the initial nucleation of SiC. We have applied 3D in-situ visualisation of the growth process using X-ray computed tomography to visualise island formation on the large seeding area. These data are related to growth process instabilities such as temperature variations during the seeding process and axial doping level changes from the seed to the newly grown crystal. Both process instabilities induce mechanical stress on the SiC lattice and act as sources for dislocation generation and multiplication. We will show a series of growth processes with varying growth parameters that shed light on the initial growth stage of SiC.As the crystal diameter of SiC increases from 150 mm to 200 mm, the results of this study become increasingly important.

Effects of Thermal Boundary Resistance on Thermal Management of Gallium-Nitride-Based Semiconductor Devices: A Review.

Wide-bandgap gallium nitride (GaN)-based semiconductors offer significant advantages over traditional Si-based semiconductors in terms of high-power and high-frequency operations. As it has superior properties, such as high operating temperatures, high-frequency operation, high breakdown electric field, and enhanced radiation resistance, GaN is applied in various fields, such as power electronic devices, renewable energy systems, light-emitting diodes, and radio frequency (RF) electronic devices. For example, GaN-based high-electron-mobility transistors (HEMTs) are used widely in various applications, such as 5G cellular networks, satellite communication, and radar systems. When a current flows through the transistor channels during operation, the self-heating effect (SHE) deriving from joule heat generation causes a significant increase in the temperature. Increases in the channel temperature reduce the carrier mobility and cause a shift in the threshold voltage, resulting in significant performance degradation. Moreover, temperature increases cause substantial lifetime reductions. Accordingly, GaN-based HEMTs are operated at a low power, although they have demonstrated high RF output power potential. The SHE is expected to be even more important in future advanced technology designs, such as gate-all-around field-effect transistor (GAAFET) and three-dimensional (3D) IC architectures. Materials with high thermal conductivities, such as silicon carbide (SiC) and diamond, are good candidates as substrates for heat dissipation in GaN-based semiconductors. However, the thermal boundary resistance (TBR) of the GaN/substrate interface is a bottleneck for heat dissipation. This bottleneck should be reduced optimally to enable full employment of the high thermal conductivity of the substrates. Here, we comprehensively review the experimental and simulation studies that report TBRs in GaN-on-SiC and GaN-on-diamond devices. The effects of the growth methods, growth conditions, integration methods, and interlayer structures on the TBR are summarized. This study provides guidelines for decreasing the TBR for thermal management in the design and implementation of GaN-based semiconductor devices.

Comparative Study of Dielectric Thin Films for GaN HEMTs

As a typical representative of the third generation of semiconductor materials, attracts wide attention, wide band-gap semiconductor gallium nitride (GaN) has many advantages that silicon materials do not have, now it has been used to fabricate many devices. And as one of the heterojunctions MESFET, GaN HEMTs have many excellent properties, e.g., high electric breakdown field, large saturation velocity, and low ON-resistance (Ron), wide band gap, and high mobility. The material can be employed in several fields as a result of its good qualities. All these amazing properties make it an excellent semiconductor material for communication, radar detection, guidance and other civilian and military fields. Specifically, there are mobile phones, satellite television receivers, voltage converters and radar equipment, power adapter and car charging. However, in the high-power application, the current collapses affected the performance of the devices badly. The article will discuss both high dielectric constant and low dielectric, which are used for reducing the current collapse, and improve the devices performance.

Improved Breakdown Strength and Restrained Leakage Current of Sandwich Structure Ferroelectric Polymers Utilizing Ultra-Thin Al2O3 Nanosheets.

Flexible capacity applications demand a large energy storage density and high breakdown electric field strength of flexible films. Here, P(VDF-HFP) with ultra-thin Al2O3 nanosheet composite films were designed and fabricated through an electrospinning process followed by hot-pressing into a sandwich structure. The results show that the insulating ultra-thin Al2O3 nanosheets and the sandwich structure can enhance the composites' breakdown strength (by 24.8%) and energy density (by 30.6%) compared to the P(VDF-HFP) polymer matrix. An energy storage density of 23.5 J/cm3 at the ultrahigh breakdown strength of 740 kV/mm can be therefore realized. The insulating test and phase-field simulation results reveal that ultra-thin nanosheets insulating buffer layers can reduce the leakage current in composites; thus, it affects the electric field spatial distribution to enhance breakdown strength. Our research provides a feasible method to increase the breakdown strength of ferroelectric polymers, which is comparable to those of non-ferroelectric polymers.

Achieving high energy-storage performance of medium-entropy (Na0.25Bi0.25Ca0.25Sr0.25)TiO3 lead-free relaxor ferroelectric ceramic for pulsed power capacitor

Advanced electrostatic energy-storage science and technology based on dielectric ceramics capacitors are widely applied in pulsed power systems. Recently, entropy increasing design engineering has been considered as an available method to promote electrical characteristics in dielectric energy-storage ceramics. In this study, medium-entropy (Na0.25Bi0.25Ca0.25Sr0.25)TiO3 (NBCSTO) ceramics with good energy-storage properties were obtained by a conventional solid-state reaction method. The microstructure and element analysis results show that a perovskite structure was identified for the NBCSTO sample, and no secondary phases were detected. Furthermore, a dense microstructure and small grain size lead to a high breakdown electric field strength (EB) of 430 kV/cm of the NBCSTO ceramic, which also displays the features of relaxor ferroelectrics. Importantly, a high Wrec⁓5.84 J/cm3 along with a medium η⁓80 % were simultaneously achieved in the NBCSTO ceramic, as well as good energy-storage stability. Moreover, the NBCSTO ceramic exhibits both a high PD and a fast discharging speed. All the above results indicate that the NBCSTO ceramic may be potential eco-friendly material for capacitor used in the pulsed power systems.

Enhanced energy-storage performance in BNT-LST-based ceramics via polarization optimization and breakdown strength regulation

Dielectric storage ceramics are widely used in electronic products due to their speed charge-discharge rate. However, the low recoverable energy density, which is attributing to the high remanent polarization and low breakdown electric field, results in an inferior efficiency, which hinders their applications. Here, superior energy storage properties were achieved in the pseudo-cubic 0.5(Bi0.5Na0.5)TiO3–0.5(La0.1Sr0.8)TiO3-δ (BNT-0.5LST) ceramics at 323 kV/cm, and the recoverable energy density, energy efficiency, and breakdown strength in BNT-0.5LST ceramics were severally enhanced 10 times, 5.9 times and 1.3 times than those of BNT-0.1LST ceramics. Slim P-E loops and high polarization (28.13 μC/cm2) originated from the presence of polar nano-regions (PNRs), and the PNRs with weakly couple with each other decreased the remanent polarization. Large breakdown strength attributed to the broad band gap (3.302 eV) and refined grain (1.59 μm). Transmission electron microscopy proved the presence of PNRs in the pseudo-cubic matrix phase. The results have provided a novel route for fabricating the storage ceramics with the outstanding energy storage properties.

Tuning the Ferroelectric Response of Sandwich-Structured Nanocomposites with the Coordination of Ba0.6Sr0.4TiO3 Nanoparticles and Boron Nitride Nanosheets to Achieve Excellent Discharge Energy Density and Efficiency.

With the rapid development of new electronic products and sustainable energy systems, there is an increasing demand for electrical energy storage devices such as electrostatic capacitors. In order to comprehensively improve the dielectric, insulating, and energy storage properties of PVDF-based composites, sandwich-structured composites were prepared by layer-by-layer solution casting. The outer layers of the sandwich structure composite are both PVDF/boron nitride nanosheet composites, and the middle layer is a PVDF/Ba0.6Sr0.4TiO3 nanoparticles composite. The structural and electrical properties of the sandwich-structured composites were characterized and analyzed. The results show that when the volume percentage of Ba0.6Sr0.4TiO3 nanoparticles in the middle layer of the sandwich structure composite is 1 vol.%, the dielectric properties are significantly improved. Its dielectric constant is 8.99 at 10 kHz, the dielectric loss factor is 0.025, and it has better insulating properties and resistance to electrical breakdown. Benefiting from the high breakdown electric field strength and the large maximum electrical displacement, the sandwich-structured composites with 1 vol.% and Ba0.6Sr0.4TiO3 nanoparticles in the middle layer show a superior discharge energy density of 8.9 J/cm3, and excellent charge and discharge energy efficiency of 76%. The sandwich structure composite achieves the goal of simultaneous improvement in breakdown electric field strength and dielectric constant.

Electrical Properties of Ga2O3 Schottky Barrier Diodes with and without Mesa Structure

Devices based on wide bandgap (WBG) semiconductors like silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga2O3) are ideal for high-power electronics in harsh environments. Among the WBG semiconductors, ultrawide bandgap (UWBG) β-phase gallium oxide (Ga2O3), EG ≈ 4.8 eV, is emerging as a replacement for the current commercially available wide bandgap (WBG) power electronics due to its generational improvements in performance and manufacturing cost [1]. Ga2O3 has a high theoretical breakdown electrical field of 8 MV/cm which in turn gives its Baliga’s figure of merit for power devices that is larger than other WBG materials. The availability of high-quality Ga2O3 substrates produced from melt-grown bulk single crystals also facilitates the development of vertical power devices.In the current stage, the vertical Schottky barrier diode (SBD) with Ga2O3 can have an improved current spreading effect when compared to power diode devices from Si, SiC, and GaN. Especially, the Ga2O3 is expected to surpass the trade-off relationship between breakdown voltage (BV) and on resistance (Ron,sp) that other materials have [2]. Nevertheless, the Ga2O3 vertical SBD still cannot achieve the theoretical breakdown electric field. One of the key topics for WBG semiconductors application is a structure for improved electrical management such as field rings, junction termination extension, and field plates to reduce the leakage current in the reverse bias state.Here, we investigate the characteristics of Ga2O3 SBDs with and without mesa structure in extreme environments at high and low temperature. Conventional and mesa Ga2O3 SBDs were fabricated on the halide vapor phase epitaxy (HVPE) grown β-Ga2O3 (001). A Sn-doped substrate with 61016 cm-3 was used for the HVPE growth. In the SBD with mesa structure, the circular mesa with a diameter of 162 μm and a depth of 500 nm was formed around anode electrodes. The Ti/Au metal stack on the back side of the substrate acted as a cathode and the anode electrode deposited Ni/Au/Pt layers. After the fabrication process, current-voltage (I-V) measurements were performed on the SBDs between -5 V and 1 V. From the results, the values of Ron,sp at 0.7 V are 46.4 Ω•cm2 and 46.2 Ω•cm2 in conventional and mesa SBDs, respectively. And additionally, the leakage current at -5 V is reduced by approximately 44.3% in the mesa structure. To obtain the Schottky barrier height (SBH) from I-V and capacitance-voltage (C-V) measurements, the C-V was observed in the range of -5 V to 0.5 V at 100 kHz. The SBH values from I-V and C-V measurements, the mesa SBDs have 1% - 5% larger SBH compared to the conventional structure, and it could be related to lower leakage current. Moreover, the depletion depths of conventional and mesa SBDs were 52.2 nm and 57.8 nm, respectively, from C-V measurements. For considering the electrical characteristics in extreme temperatures, the I-V measurements of both SBDs structure will be measured between 75 K to 525 K. From an initial low temperature measurement series, we determine a Richardson constant of 49 A/cm2 comparable to what has been reported by other groups. Furthermore, we will extend the study by performing deep-level transient spectroscopy (DLTS) to understand the defect information in Ga2O3.

Photo-Enhanced Inverse Metal-Assisted Chemical Etching of α-Ga2O3 grown on Al2O3

Si-based semiconductor devices are not suitable for stable operations in the aerospace environments. Among the ultra-wide bandgap semiconductor materials, gallium oxide (Ga2O3) is attracting attention as the next-generation material for high-power semiconductor devices in extreme condition beyond Si, owing to its large band gap of 4.5-5.3 eV, high breakdown electric fields of 7-10 MV/cm, excellent chemical and thermal stability and radiation hardness. Alpha gallium oxide (α-Ga2O3) has the largest bandgap (4.8-5.3 eV) and the highest breakdown electric fields (~10 MV/cm) among the five Ga2O3 polymorphs, which facilitates the application of α-Ga2O3 as a high power device. However, the research on etching technology for α-Ga2O3 is rare. Etching technology is a crucial step of device fabrication. Chemical etching is free from plasma-induced damage which leads to superior device performance compared with dry etching, and high throughput with low cost is beneficial to industrial implementations. Chemical stability of Ga2O3 hinders the effective reaction with most chemical etchants. However, the photo-enhanced inverse metal assisted chemical (I-MAC) etching, where a noble metal with a high work function is utilized as a catalyst under UV irradiation, has emerged as a candidate for the chemical etching of Ga2O3. Deep-UV irradiation generates electron-hole pairs (EHPs) in the uncovered region of Ga2O3, and the metal electrode withdraws carriers from the photo-generated EHPs. The holes that are accumulated in the uncovered region of Ga2O3 react with gallium ions which produce gallium fluoride (GaF3) in a reaction with Hydrofluoric acid (HF). The etching process continues as the oxidant re-oxidizes the metal. The etch rate can be controlled by various parameter, including concentration and temperature of the etchant. In this work, for the I-MAC etch of α-Ga2O3 on sapphire substrate grown by halide vapor phase epitaxy, Pt was deposited on α-Ga2O3. Etch rate and surface roughness were characterized by atomic force microscopy after each step of the I-MAC etch. The I-MAC etch using HF and potassium persulfate (K2S2O8) solution with 185-nm UV irradiation was performed at constant durations under different etchant temperature conditions. The etch rates obtained at each temperature condition were fitted with the Arrhenius plot to estimate the activation energy of 0.898 eV. The etch depth showed a linear increase with time and the etch rate exhibits a direct dependency on the temperature of the etchant, indicating that the I-MAC etching of α-Ga2O3 is an activation-controlled reaction. As the I-MAC etching proceeded, surface roughness of α-Ga2O3 showed a tendency to increase. The rate at which the surface roughness increased increased with raising the etchant temperature. In the case of Pt there was no significant difference in the surface roughness after etching. After the completion of the I-MAC etch, the remaining Pt can be removed using aqua regia. The I-MAC etch process of α-Ga2O3 can allow us to fabricate α-Ga2O3 without plasma-damage. Figure 1

Characteristics, application and development trend of the third-generation semiconductor

Various devices made of the third-generation semiconductor have been gradually applied to various fields with the rapid development of the third-generation semiconductor materials equipment, manufacturing technology, and device physics represented by SiC and GaN. Firstly, the characteristics of the third-generation semiconductors is analyzed in this paper. Compared with the first-generation and second-generation semiconductors, the third-generation semiconductor has a wider band gap width, higher breakdown electric field, higher thermal conductivity, higher electron saturation rate and more expensive price. Then this paper will talk about the application of the third-generation semiconductor. The third-generation semiconductor materials can be mainly used in three fields, which are photoelectric, microwave radio frequency and power electronics. In terms of the photoelectric aspect, this paper takes the blue LED as an example. The blue LED is produced because of the wide band gap of the third-generation semiconductor. In the microwave RF aspect, the paper takes the 5G communication system as an example. Third-generation semiconductors make the high-frequency, high-power devices needed for 5G communications systems. In the power electronics aspect, the paper cites new energy vehicles as an example. Third-generation semiconductor components have a number of features needed for new-energy vehicles. For example, third-generation semiconductors can work at high temperatures. Finally, this paper will introduce the development trend of it. In the future, larger wafers will become mainstream. The third-generation semiconductors will be used in more fields. In addition, the new material systems will gradually mature.

Enhanced energy storage performance of (Pb, La)(Zr, Ti)O3/SrTiO3 multilayer films via a synergistic strategy

Dielectric film capacitors possess a larger dielectric breakdown field than that of their bulk ceramic counterparts, thus showing a better energy density. Herein, a synergistic strategy has been employed to enhance the energy storage density of (Pb, La)(Zr, Ti)O3/SrTiO3 multilayer films through combing the effects of atomic doping, heat treatment, and multilayer stacking. La partially substituting Pb improves relaxor characteristics of Pb(Zr, Ti)O3. A dense amorphous microstructure results in a relatively high breakdown electric field at a low annealing temperature. Additionally, the insertion of dielectric layer SrTiO3 into (Pb, La)(Zr, Ti)O3 suppresses the carriers transport due to the interface role and further improves the insulating strength and breakdown strength. Thus, a high recoverable energy density of 67.1 J/cm3 is achieved at an ultrahigh breakdown electric field of 7.45 MV/cm. Such a synergistic multiscale approach in this work is universally effective to improve the energy storage performance of dielectric multilayer films.