High Aspect Ratio Through Silicon Via Research Articles

Wafer Scale Insulation of High Aspect Ratio Through-Silicon Vias by iCVD.

In microelectronics, one of the main 3D integration strategies consists of vertically stacking and electrically connecting various functional chips using through-silicon vias (TSVs). For the fabrication of the TSVs, one of the challenges is to conformally deposit a low dielectric constant insulator thin film at the surface of the silicon. To date, there is no universal technique that can address all types of TSV integration schemes, especially in the case requiring a low deposition temperature. In this work, an organosilicate polymer deposited by initiated chemical vapor deposition (iCVD) was developed and integrated as an insulating layer for TSVs. Process studies have shown that poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (P(V3D3)) can present good conformality on high aspect ratio features by increasing the substrate temperature up to 100 °C. The trade-off is a moderate deposition rate. The thermal stability of the polymer has been investigated, and we show that a thermal annealing at 400 °C (with or without ultraviolet exposure) allows the stabilization of the dielectric films by removing residual oligomers. Then, P(V3D3) was integrated in high aspect ratio TSV (10 × 100 μm) on 300 mm silicon wafers using a standard integration flow for TSV metallization. Functional devices were successfully fabricated (including daisy chains of 754 TSVs) and electrically characterized. Our work shows that the metallization barrier should be carefully selected to eliminate the appearance of voids at the top corner of the TSV after the Cu annealing step. Moreover, an appropriate integration process should be used to avoid the appearance of cohesive cracks in the liner. This work constitutes a first proof of concept of the use of an iCVD polymer in a quasi-industrial microelectronic environment. It also highlights the benefit of iCVD as a promising technique to deposit conformal dielectric thin films in a microelectronic pilot line environment.

Thermal-Mechanical Property of High Aspect Ratio TSV in Advanced IC integration and Packaging

Advanced packaging of integrated circuits (IC) plays a critical role on the way towards high performance, high density, low power consumption and light weight of electronics. Through-silicon vias (TSV) is the heart of 3D IC integration and packaging. However, copper protrusion due to mismatch of coefficients of thermal expansion (CTE) between copper and silicon, which may result in the dielectric material breakdown, becomes the bottleneck of TSV in high-temperature application. In this paper, thermal-mechanical property of high aspect ratio TSV is investigated through experiments under different annealing process, which will help to accelerate the widely application of TSV in advanced packaging of electronics in the future.

Study on the 12 in. wafer uniformity of high aspect ratio TSV filling by using rotation cathode

In 2.5/3D(2.5/3-dimensional) packages, TSV (Through-Silicon Via) technology is crucial for achieving high performance and low power consumption. However, there are still challenges when it comes to uniformly filling TSVs on 300 mm whole wafers without defects. This study focuses on addressing this issue by designing a rotating cathode carrier with a 300 mm diameter, simulating the plating environment in different areas of a 300 mm wafer. The effects of plating conditions, such as cathode rotational speed and chip mounting position, on the filling of TSV are investigated. The TSV have a hole diameter of 10 μm and a depth of 100 μm.The findings reveal that when the cathode carrier rotates at a speed of 30 rpm, different areas of the analog wafer exhibit complete filling of TSV. Additionally, a surface plating layer with an average thickness of approximately 3 μm is obtained.

A Novel 2D/3D X-ray Microscopy Alignment and Inspection Solution for Thermocompression Bonding (TCB) in a Highly Integrated Flip Chip Fan-Out Wafer Level Package (FO-WLP)

As packaging drives to extend the capabilities of Moore’s Law via heterogenous integration, numerous bonding technologies have emerged as potential pathways, allowing for integration of both a variety of devices in the lateral space as well as vertical integration of chips via stacking. As vertical integration on interposer becomes more complex due to shrinking CDs and increasing die layers, alignment and shape control in the bonding process becomes critical. Thermocompression bonding (TCB) is particularly well-suited for larger die, where localized reflow allows a better control of chip gap height and tilt throughout the bonding process. TCB systems require both high accuracy and repeatability in all dimensions to provide a reliable system in package. While a 2D system can provide a plan view assessment of a single bond layer between two chips, it falls short in characterizing the critical z-dimension in a highly integrated chip stacking scenario. Therefore a robust solution is needed for both system alignment validation in the x,y plane as well as a capability to explore gap height and bump quality/buried issues in high aspect ratio TSV. This paper will explore an x-ray application of a stacked 15-layer die-to-interposer structure to qualitatively validate overall health of the TSV (bond, pad, fill) via a nondestructive volumetric method as well as quantitatively evaluate stacked die for via/ball/pad alignment to determine overall alignment shift during the bonding process. In the test vehicle for a flip chip FO-WLP process flow first presented by IMEC, a silicon (Si) bridge is utilized to connect the logic and through-package via dies with a bump pitch of 20µm for the logic die interconnect. This is done by carefully aligning the logic dies on the carrier and then placing the through-package dies aligned to the carrier and logic dies. In the final step, a high accuracy placement and stacking TCB tool attaches the Si bridge. To perform an accurate assessment for bump alignment and bond quality, an initial high-resolution 3D x-ray scan is performed on a 1.5mm3 region of interest with over 2,000 individual projections at a 1.4µm voxel resolution with a 4x objective, taking approximately two hours. The dataset is put through a deep-learning algorithm which generates an AI model. This model is then applied to a faster scan of 15 minutes with a 1.4µm voxel resolution for the same field of view (FOV) on a nearby array and the data is collected and processed. To verify alignment of the entire sample, data is collected on the tightest pitch (in this case 20µm) oriented in both the vertical (x) and horizontal (y) plane in the through-silicon via (TSV) region. The z-plane is analyzed and processed by computer vision algorithms, and individual interconnects are then quantified and sorted for solder height (z), width (x,y) and TSV misalignment (deviation from expected center, x1y1 → x2y2). To validate the model, a high-resolution uncorrected 20h scan and a 15min scan based on deep learning are collected for the same region of interest (ROI). The data is comparable. Furthermore, the global misalignment data between both datasets demonstrates similar misalignment propagating through the 15-layer stack.

Superconformal Film Growth: From Smoothing Surfaces to Interconnect Technology.

ConspectusElectronics manufacturing involves Cu electrodeposition to form 3D circuitry of arbitrary complexity. This ranges from nanometer-wide interconnects between individual transistors to increasingly large multilevel intermediate and global scale on-chip wiring. At larger scale, similar technology is used to form micrometer-sized high aspect ratio through-silicon vias (TSV) that facilitate chip stacking and multilevel printed circuit board (PCB) metallization. Common to all of these applications is void-free Cu filling of lithographically defined trenches and vias. While line-of-sight physical vapor deposition processes cannot accomplish this feat, the combination of surfactants and electrochemical or chemical vapor deposition enables preferential metal deposition within recessed surface features known as superfilling. The same superconformal film growth processes account for the long-reported but poorly understood smoothing and brightening action provided by certain electroplating additives. Prototypical surfactant additives for superconformal Cu deposition from acid-based CuSO4 electrolytes include a combination of halide, polyether suppressor, sulfonate-terminated disulfide, and/or thiol accelerator and possibly a N-bearing cationic leveler. Many competitive and coadsorption dynamics underlie functional operation of the additives. Upon immersion, Cu surfaces are rapidly covered by a saturated halide layer that makes the interface more hydrophobic, thereby supporting the formation of a polyether suppressor layer. Also, halide serves as a cosurfactant supporting the adsorption of amphiphilic molecular disulfide species on the surface while inhibiting copper sulfide formation and incorporation into the growing deposit. Furthermore, the dangling hydrophilic sulfonate end group of the accelerator enables activated metal deposition by hindering polyether suppressor assembly. A common thread in superconformal feature filling is additive-derived positive feedback of the metal deposition reaction within recessed or re-entrant regions. For submicrometer features or optically rough surfaces, area reduction that accompanies the motion of concave surface segments results in the most strongly bound adsorbates' enrichment, which for the suppressor-accelerator systems is the sulfonate-terminated disulfide accelerator species. The superfilling and smoothing process is quantitatively captured by the curvature-enhanced adsorbate coverage mechanism. For larger features, such as TSV, whose depths approach the thickness of the hydrodynamic boundary layer, significant compositional and electrical gradients couple with the metal deposition process to give a negative differential resistance and related nonlinear effects on morphological evolution. For certain suppressor-only electrolytes, remarkable bottom-up feature filling occurs where metal deposition disrupts inhibiting adsorbates at the bottom of the TSV or overruns the ability of the suppressor to form due to kinetic or transport limitations. Because the electrical response to changes in interface chemistry is more rapid than mass transport processes, deposition on planar substrates proceeds by bifurcation into passive and active zones, generating Turing patterns. On patterned substrates, active zone development is biased toward the most recessed regions. The distinction between packaging and on-chip metallization will be blurred as the dimensions of the former merge with those of early day on-chip 3D metallization.

Fabrication and Electrical Characterization of High Aspect Ratio Through-Silicon Vias with Polyimide Liner for 3D Integration.

High aspect ratio (HAR) through-silicon vias (TSVs) are in urgent need to achieve smaller keep-out zones (KOZs) and higher integration density for the miniaturization of high-performance three-dimensional (3D) integration of integrated circuits (IC), micro-electro-mechanical systems (MEMS), and other devices. In this study, HAR TSVs with a diameter of 11 μm and an aspect ratio of 10:1 are successfully fabricated in a low-cost process flow. Conformal polyimide (PI) liners are deposited using a vacuum-assisted spin coating technique, and the effects of spin coating time and speed on the deposition results are discussed. Then, continuous Cu seed layers are fabricated by sequential sputtering and ultrasound-assisted electroless plating. Additionally, void-free and seamless Cu conductors are formed by electroplating. Moreover, a semi-additive method is used to fabricate the redistribution layers (RDLs) on the insulating layers of photosensitive PI (PSPI). Notably, a plasma bombardment process is introduced to remove residual PSPI in the contact windows between RDLs and central pillars. Results show that the resistance of a single TSV from a daisy chain of 144 TSVs with density of 2000/mm2 is about 28 mΩ. Additionally, the S-parameters of a single TSV are obtained using L-2L de-embedding technology, and the experimental and simulated results agree well. The proposed low-cost fabrication technologies and the related electrical characterization of PI-TSVs are significant for the application of HAR TSVs in modern heterogeneous integration systems.

Covalently formation of insulation and barrier layers in high aspect ratio TSVs

Polymers have been widely explored as the alternative material for silicon oxide in through-silicon vias (TSVs). However, an acceptable adhesion between polymers and metallic diffusion barriers is often challenging, especially when it comes to ultrathin films with extremely low roughness. This paper proposes a cost-effective and highly reliable wet deposition path to successively fabricate polyacrylic acid (PAA) insulation films and nickel diffusion barriers on the silicon substrate. PAA films were firstly pretreated to form diazo functional groups through aryldiazonium chemistry. With an electrochemical reduction, catalytic palladium nanoparticles and palladium chelates were introduced to the pretreated substrate by robust Pd-C covalent bonds and electrostatic interaction, respectively. After being immersed into the plating solution, a continuous and uniform nickel layer on the PAA substrate with high adhesion strength can be obtained. Therefore, a stable interface between polymer insulation layers and nickel diffusion barrier can be provided by the proposed covalent fabrication approach. This wet polymer metallization approach on the flat silicon substrate was further extended in TSVs (3 μm × 30 μm) for practical deployment.

Void-free Copper Electrodeposition in High Aspect Ratio, Full Wafer Thickness Through-Silicon Vias with Endpoint Detection

High density interconnects are required for increased input/output for microelectronics applications, incentivizing the development of Cu electrochemical deposition (ECD) processes for high aspect ratio through-silicon vias (TSVs). This work outlines Cu ECD processes for 62.5 μm diameter TSVs, etched into a 625 μm thick silicon substrate, a 10:1 aspect ratio. Cu ECD in high aspect ratio features relies on a delicate balance of electrolyte composition, solution replenishment, and applied voltage. Implementing a CuSO4-H2SO4 electrolyte, which contains suppressor and a low chloride concentration, allows for a tunable relationship between applied voltage and localized deposition in the vias. A stepped potential waveform was applied to move the Cu growth front from the bottom of the via to the top. Sample characterization was performed through mechanical cross-sections and X-ray computed tomography (CT) scans. The CT scans revealed small seam voids in the Cu electrodeposit, and process parameters were tuned accordingly to produce void-free Cu features. During the voltage-controlled experiments, measured current data showed a characteristic current minimum, which was identified as an endpoint detection method for Cu deposition in these vias. We believe this is the first report of this novel endpoint detection method for TSV filling.

Solid-state qubits integrated with superconducting through-silicon vias

As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require, access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays—provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or low-loss signal and control routing. In this work, we demonstrate the integration of superconducting, high-aspect ratio TSVs—10 μm wide by 20 μm long by 200 μm deep—with superconducting qubits. We utilize TSVs for baseband control and high-fidelity microwave readout of qubits using a two-chip, bump-bonded architecture. We also validate the fabrication of qubits directly upon the surface of a TSV-integrated chip. These key 3D-integration milestones pave the way for the control and readout of high-density superconducting qubit arrays using superconducting TSVs.

Superconducting High-Aspect Ratio Through-Silicon Vias with DC-Sputtered Al for Quantum 3D integration

This paper presents the fabrication and electrical characterization of superconducting high-aspect ratio through-silicon vias DC-sputtered with aluminum. Fully conformal and void-free coating of $300~\mu \text{m}$ -deep and $50~\mu \text{m}$ -wide vias with Al, a CMOS-compatible and widely available superconductor, was made possible by tailoring a funneled sidewall profile for the axisymmetric vias. Single-via electric resistance as low as 80.44 $\text{m}\Omega $ at room temperature and superconductivity below 1.28 K were measured by a cross-bridge Kelvin resistor structure. This work thus demonstrates the fabrication of functional superconducting interposer layers, suitable for high-density 3D integration of silicon-based quantum computing architectures.

Cyclic Voltammetry Stripping Method for Determining Additive Concentration in Cu Electroplating Solution

Cu electroplating has been used in various fields. Electroplating process can form thin film of metal on a substrate and the application of Cu electroplating process expands from fabricating Cu foil to filling Cu microvia and interconnect in semiconductor chip and printed circuit boards (PCBs). [1] The mechanical properties of the Cu deposit and the morphology of Cu films deposited by electrochemical systems are controlled by additives. [2] Various combinations of additives are used to control the film properties of the deposit and induce bottom-up filling in various scales of vias and interconnects. Conventional additives used in Cu electroplating are classified into three categories. Accelerators increase Cu electrodeposition rate where they adsorb. Suppressors physically block the access of Cu2+ ions to the surface of the electrode, retarding the Cu electrodeposition rate. Levelers, generally slowing the plating rate like suppressors, have specific behavior dependent on the mass transport and are newly introduced to fill micro-scaled vias and through-holes. [3] As like other chemical processes, Cu electroplating accompanies degradation. Plating bath contains many kinds of components and bath conditions can be degraded during the Cu electroplating process. Therefore, monitoring the properties of the bath is necessary for various purpose. The additives, which are hard to monitor their chemical properties are decomposed to byproducts or incorporated into the deposit due to the chemical/electrochemical effects. Therefore, the degradation of organic additives decreases the concentration of the additives and produces byproducts. [4, 5] Because the concentration of the additives have critical effects on the fabricated Cu deposit, monitoring the concentration of the additives is important. CVS (cyclic voltammetry stripping) uses voltammetric approach in determining the concentrations and it concentrates on the stripping charge, which represents the electroplating rate affected by the concentration/type of additives. CVS obtains calibration curve of a target additive using standard solution whose concentration of the target additive is known and determines the concentration of the additive by interpolating the stripping charge of a sample solution. When monitoring additives used in Cu electroplating solution, optimized CVS methods have been devised for each type of additives. MLAT-CVS (modified linear approximation technique-CVS) is used for determining accelerator concentration, however in case of SPS (bis(3-sulfoproply) disulfide), the degradation byproduct, MPSA (3-mercapto-1-propanesulfonic acid), acts as an interference due to its different accelerating effects on Cu electroplating compared with SPS. Controlling the pH of the base and target solutions could completely convert the MPSA to SPS, which enabled the determination of total amount of accelerating agent when using MLAT-CVS method. The conversion ratio from SPS to MPSA responded to the devised function related to stripping charge, which enabled the determination of individual SPS/MPSA concentration. DT-CVS (dilution/titration-CVS) method is generally used for determining suppressor concentration. When the conventional DT-CVS analysis was applied to accelerator/suppressor two-additive target solutions, the accelerator could act as an interference as its effect on the DT-CVS was shown in Fig. 1. Even small concentrations of accelerator (CA) in CVS bath can make a change in determined suppressor concentration (CS). We suggested new method of determining the suppressor concentration in two-additive Cu electroplating solution by introducing iodide ion (I-) as an inhibitor of the accelerator. As mentioned above, I- has been recently developed to fill high-aspect ratio TSV (through silicon via) due to its excellent inhibition effect on Cu electrodeposition by deactivating SPS. RC-CVS (response curve-CVS) method could be applied to monitor I- concentration due to its leveling effect. From the optimization for the determination process, the mechanism of I- affecting Cu electroplating in addition to the successful monitoring of I- concentration in wide range with high resolution. This method was used to recover the performance of three-additive Cu electroplating solution for TSV filling. Fig. 1. Q/Q0 plots with various CAs as a function of CS and deviated concentrations of PEG-PPG by the effect of SPS at 0.6 evaluation value. References P.F. Chan, R.H. Ren, S.I. Wen, H.C. Chang, W.P. Dow, J. Electrochem. Soc., 164, D660 (2017).L. Bonou, M. Eyraud, R. Denoyel, Y. Massiani, Electrochim. Acta, 47, 4139 (2002).M.J. Kim, H.C. Kim, J.J. Kim, J. Electrochem. Soc., 163, D434 (2016).S. Choe, M.J. Kim, H.C. Kim, T. Lim, K.J. Park, K.H. Kim, S.H. Ahn, A. Lee, S.K. Kim, J.J. Kim, J. Electroanal. Chem., 714, 85 (2014).A. Frank, A.J. Bard, J. Electrochem. Soc., 150, C244 (2003). Figure 1

A Effect of Halide on Cobalt Electrodeposition for through-Silicon-Via(TSV) Application

The size of integrated circuit (IC) devices had gradually decreased. Because of limit to reduction, 3D interconnection technology had emerged. As one of the 3D interconnection technologies, Through Silicon Via (TSV) replaced conventional wire bond by making vertical electrical connections. TSVs could increase the device performance because TSV had advantages such as higher interconnection density, shorter length of interconnection, lower power consumption, and lower electrical resistance [1]. TSV was mainly plated with copper with low resistance and low electro-migration. However, copper annealing process, metal interconnect process and bonding process between chips and chips or wafers and wafers were performed at high temperature in BEOL, which causes problems such as thermal extrusion and keep-out zone. Thermal extrusion is enough to make the defect and crack at insulating layer or metal interconnect on TSV. And the keep-out zone could cause some degradation in device performance [3]. Therefore, Cobalt was used to fill TSV as alternative material which can reduce this problem because the CTE of cobalt was lower than that of copper. However, while many studies on copper TSV filling was reported, studies on cobalt TSV filling was insufficient. For the TSV bottom-up filling, TSVs were conventionally filled with some additives such as accelerator and suppressor by using the electrochemical deposition. In addition, halide was used to enhance adsorption of suppressor. Many studies confirmed effect of halide in copper electrodeposition [2, 4]. In this study, high-aspect ratio TSVs was filled with cobalt with suppressor as the single additive using the electrochemical deposition. The filling behavior was affected by suppressor concentration and the effect was saturated. In copper electrodeposition, halide ion is added because adsorption of suppressor is affected by chloride [2, 4]. Therefore, chloride, one of the halide, was added to confirm the effect of halide on cobalt electrodeposition. In cobalt electrodeposition, the role of chloride was different from that of copper electrodeposition. Electrochemical analysis explains the effect of chloride concentration in the cobalt filling. REFERENCES [1] Sanghyun Jin, Geon Wang, and Bongyoung Yoo, “ Through-Silicon-Via (TSV) Filling by Electrodeposition of Cu with Pulse Current at Ultra-Short Duty Cycle”, Journal of The Electrochemical Society, 2013, 160 (12) D3300-D3305 [2] Liu Yang, Aleksandar Radisic, Johan Deconinck, and Philippe M. Vereecken, “ Modeling the Bottom-Up Filling of Through-Silicon vias Through Suppressor Adsorption/Desorption Mechanism”, Journal of The Electrochemical Society, 2013, 160 (12) D3051-D3056 [3] Suk-Kyu Ryu, Kuan-Hsun Lu, Tengfei Jiang, Jang-Hi Im, Senior Member, Rui Huang, and Paul S. Ho, Fellow,“ Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration”, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2012, 6, VOL. 12, NO. 2, 255-262 [4] Ning Xiao, Deyu Li, Guofeng Cui, Ning Lia, Qing Li, Gang Wu, “Adsorption behavior of triblock copolymer suppressors during the copper electrodeposition”, Electrochimica Acta, 116 (2014) 284– 291

Electroless Grafting of Polymer Insulation Layers in Through-Silicon Vias

A through-silicon via (TSV) with a polymeric insulation layer is promising in three-dimensional packaging technology because of its outstanding electrical properties. In this study, we present an electroless grafting method to realize the fabrication of a thin insulation layer in high aspect ratio TSVs. The proposed method is based on the polymerization of a vinyl monomer and an aryl diazonium salt on a silicon surface. Both poly(acrylic acid) and poly(methyl methacrylate) insulation layers were successfully prepared in TSVs to demonstrate the feasibility of the proposed method to fabricate hydrophilic and hydrophobic layers. The resulting polymer insulation layer exhibited high step coverage and superior dielectric properties. The electroless grafting method is a novel synthesis route to prepare polymeric insulation layers with outstanding dielectric properties in high aspect ratio TSVs.

Influence of the Temperature-Dependent Cu+1-Accelerator Complex Formation on Through-Silicon Via Filling

The influence of the temperature-dependent Cu+1-accelerator complex formation on through-silicon via (TSV) filling was studied by means of electrochemical polarization and plating experiments. Electrochemical studies revealed increasing cuprous ion concentration upon addition of the accelerator additive in comparison to the additive-free electrolyte and further increase upon increasing temperature. This indicated formation of a Cu+1-accelerator complex. The electrochemical results were compared to TSV plating experiments at different temperatures. Despite improved mass transport of cupric ions into the high aspect ratio TSV feature at elevated temperatures, large voids were obtained under these conditions, while void-free bottom-up filling was achieved at room temperature. This effect was ascribed to acceleration of the copper deposition in the upper part of the feature due to increasing Cu+1-accelerator complex concentration at higher temperatures. The resulting counter action the effect of the suppressor additive in this part of the features is assumed to yield the observed voids by closure of the features at an early stage of the plating process. Thus, the results presented here reveal the importance of taking into account the comprehensive impact factors on copper deposition for TSV applications and help to improve and fine tune the process to challenging structures.

3D system integration on 300 mm wafer level: High-aspect-ratio TSVs with ruthenium seed layer by thermal ALD and subsequent copper electroplating

The copper electrochemical deposition (Cu-ECD) filling capability of high aspect ratio through silicon vias (HAR-TSVs) and homogeneity over 300 mm wafers were investigated on a film stack of thermal ALD (thALD) TaxNy barrier with thermal ALD Ru seed in comparison to TixNy barrier with a standard Cu i-PVD seed layer using a commercial 300 mm plating tool. As a first step, Cu-ECD was conducted on wafers with TSV blind holes with aspect ratios (AR) of 10 to 12. To achieve this, a thermal ALD film stack of approximately 6 nm TaxNy and 9 nm Ru (with a sheet resistance of [25.6 ± 1.4] Ω/ϒ) were deposited at 250 °C. The reactants for the barrier layer were (tert-butylimido)tris(diethylamino)tantalum(V) (TBTDET) and ammonia (NH3) as co-reactant. For the Ru seed layer deposition (ethylcyclopentadienyl)(pyrrolyl)ruthenium(II) (ECPR) and molecular oxygen as co-reactant were used supplemented by a hydrogen purge step after every third ALD cycle. The corresponding ALD growth was observed during the entire process by in-situ real-time spectroscopic ellipsometry (irtSE). Blister-free deposition and satisfactory film stack adhesion with no delamination was verified ex situ by scanning electron microscopy (SEM). The deposited copper inside the TSVs was analyzed by focused ion beam (FIB) imaging and X-ray tomography.The Cu ECD filling capability in HAR-TSVs was shown on a film stack of thALD TaxNy thALD Ru seed using a commercial industry standard 300 mm plating tool. A novel blister-free ultra-thin Ru ALD film having good adhesion properties and unique advantages, e. g. high conformity in high-aspect-ratio through-silicon vias large-scale film uniformity over 300 mm wafers, as well as good reproducibility was developed.

Pulse Electrodeposition of Cu through-Silicon-Via (TSV) with Surface Suppressor

In recent years, many researches have been focused on the miniaturization of the integrated circuit (IC) feature size to improve the performance of semiconductor devices. However, we are facing the problems such as physical limit of the miniaturization and then increasing processing cost. To overcome these problems the Through-Si-Via (TSV) interconnection, a kind of the 3D interconnection, is a promising technology that could achieve high density, lower energy consumption and high performance in the IC. Since the TSV filling process is costly in the entire TSV process, the TSV filling process which the Cu electrodeposition for TSV is one of key processes. The TSV bottom-up filling which the filling of Cu from the bottom to the top of via with suppressed lateral growth is the solution to ensure a void free filling in high aspect ratio TSV. The bottom-up filling could be achieved by using additives like a suppressor and an accelerator in the electrolyte. In a theoretical model, the suppression breakdown at the bottom of TSV cause the bottom-up filling of TSV. Simultaneous desorption of suppressor by high potential due to ion depletion in the via bottom leads focus of current at the via bottom. Due to adsorption/desorption behavior of the suppressor, the bottom-up TSV filling could be achieved by only using the suppressor.1-3 Furthermore, it was reported that the suppressor at the sidewall is replaced by the accelerator and then the bottom-up filling performance was degraded.3 Lu et al. introduced the nanotwin Cu thin film, which had been attained with pulse electrodeposition.4 Mechanical properties of the Cu thin film is significantly enhanced by highly dense coherent twin boundaries without the degradation of electrical conductivity. Because it could effectively block the dislocation motion without interrupting the migration of electrons.4 The mechanical property of TSV interconnection such as thermal behavior is important as well as the electrical property including electrical conductivity for improvement TSV performance. Therefore, the nanotwin Cu is proper for the TSV interconnection. In this study, nanotwin Cu was applied to fill into high aspect ratio of via (diameter = 5 µm, depth = 60 µm) with pulse current conditions. The deposition condition between direct current and pulse current was compared to observe the filling characteristics. The mechanical properties as the thermal expansion behavior, which is critical to adopting integrated devices, of nanotwin Cu were investigated. As a result, the results with pulse current condition showed obvious improved the TSV filling property than direct current condition. 1. T. P. Moffat and D. Josell, J. Electrochem. Soc., 159, D208 (2012). 2. T. Moffat and D. Josell, Journal of The Electrochemical Society, 159, D208 (2012). 3. L. Yang, A. Radisic, J. Deconinck, and P. M. Vereeckena, J. Electrochem. soc., 160, D3051 (2013). 4. L. Lu, Science, 304, 422-426 (2004).

Interface charge trapping induced flatband voltage shift during plasma-enhanced atomic layer deposition in through silicon via

A Through Silicon Via (TSV) is a key component for 3D integrated circuit stacking technology, and the diameter of a TSV keeps scaling down to reduce the footprint in silicon. The TSV aspect ratio, defined as the TSV depth/diameter, tends to increase consequently. Starting from the aspect ratio of 10, to improve the TSV sidewall coverage and reduce the process thermal budget, the TSV dielectric liner deposition process has evolved from sub-atmospheric chemical vapour deposition to plasma-enhanced atomic layer deposition (PE-ALD). However, with this change, a strong negative shift in the flatband voltage is observed in the capacitance-voltage characteristic of the vertical metal-oxide-semiconductor (MOS) parasitic capacitor formed between the TSV copper metal and the p-Si substrate. And, no shift is present in planar MOS capacitors manufactured with the same PE-ALD oxide. By comparing the integration process of these two MOS capacitor structures, and by using Elastic Recoil Detection to study the elemental composition of our films, it is found that the origin of the negative flatband voltage shift is the positive charge trapping at the Si/SiO2 interface, due to the positive PE-ALD reactants confined to the narrow cavity of high aspect ratio TSVs. This interface charge trapping effect can be effectively mitigated by high temperature annealing. However, this is limited in the real process due to the high thermal budget. Further investigation on liner oxide process optimization is needed.

Wet Metallization of High Aspect Ratio TSV Using Electrografted Polymer Insulator to Suppress Residual Stress in Silicon

Through-silicon-vias (TSV) are the key to 3-D integrated microsystems. Their fabrication leads to reliability issues linked to the thermo-mechanical stress induced in the silicon around the vias. In this paper, we propose reducing the silicon residual stress in high aspect ratio copper TSVs (HAR TSV) using an electrografted polymer insulator, poly-4-vinylpyridine (P4VP), to replace the traditional silicon oxide layer. We use Raman spectroscopy to make the first investigation of the residual stress in the Si around P4VP-insulated TSVs and compare it to SiO2-insulated TSVs. The results show that P4VP acts as a stress buffer layer because of its particular mechanical properties as the measured residual stress in Si is significantly reduced at room temperature around the polymer insulated HAR TSVs. The potential benefits of such a technology are not only better thermo-mechanical reliability of a 3-D integrated microsystem but also greater integration density.

A Study on the Thermomechanical Reliability Risks of Through-Silicon-Vias in Sensor Applications.

Reliability risks for two different types of through-silicon-vias (TSVs) are discussed in this paper. The first is a partially-filled copper TSV, if which the copper layer covers the side walls and bottom. A polymer is used to fill the rest of the cavity. Stresses in risk sites are studied and ranked for this TSV structure by FEA modeling. Parametric studies for material properties (modulus and thermal expansion) of TSV polymer are performed. The second type is a high aspect ratio TSV filled by polycrystalline silicon (poly Si). Potential risks of the voids in the poly Si due to filling defects are studied. Fracture mechanics methods are utilized to evaluate the risk for two different assembly conditions: package assembled to printed circuit board (PCB) and package assembled to flexible substrate. The effect of board/substrate/die thickness and the size and location of the void are discussed.

Preventing TSV Protrusion Via Controlling Impurity Content in Copper Electrodeposits

3D IC integration is the latest technological breakthrough for maximizing its performance while reducing wiring lengths, interconnection latency, and power consumption. Through-silicon via (TSV) is an essential feature of the 3D IC integration. Filling high aspect ratio TSVs by the conductive materials can be a challenging task. Copper electrodepostion is often adopted due to its optimal electrical preoperties, simplicity, and cost-effectiveness. However, the coefficient of thermal expansion (CTE) of copper is much higher (16.7 ppm/℃) than that of silicon (2.3 ppm/℃). Therefore, the CTE mismatch between copper and silicon substrate can induce thermal stresses, which may lead to TSV protrusion and interfacial delamination. In previous studies, this is mostly managed via suitable heat treatment. This study however proposes a novel method for controlling TSV protrusion. Copper with JGB (Janus Green B, C30H31ClN6) concentration increases (and at the level of 0.2mM of JGB), while the sheet resistance decrease by 7% for the initial resistance. Here, the crystal growth is not observed that is due to impurity pinning or solute dragging effect at grain boundaries. This leads to the conclusion that controlling impurity contents may relieve stress of TSV overhang area. To prevent TSV protrusion, we also perform the same concentration split tests on TSV pattern wafers. Figure 1. EBSD IPF maps of Cu electrodeposit after annealing at 80 ℃ for 90 min with various JGB concentrations of (a) 0, (b) 0.01, (c) 0.03, (d) 0.1, (e) 0.2 and (f) 1 mM in the Cu plating bath. Figure 1