High Aspect Ratio Silicon Nanowires Research Articles

Liquid and solid states on-chip micro-supercapacitors using silicon nanowire-graphene nanowall-pani electrode based on microfabrication technology

Liquid and solid states on-chip micro-supercapacitors based on polyaniline (PANI) coated on graphene nanowalls which grown on silicon nanowires were reported in this work. Novel micro-fabrication technologies were investigated to create three dimension (3D) hierarchical electrodes. High aspect ratio silicon nanowires were produced by metal-assisted chemical etching (MACE). 3D hierarchical graphene nanowalls were grown on silicon nanowire surface by a microwave plasma-enhanced chemical vapor deposition (PECVD). Graphene nanowalls were subsequently coated by conductive PANI. Both of liquid and solid state micro-supercapacitors were successfully fabricated with symmetric face to face high density nanowire arrays separated by liquid and gel electrolytes, respectively. The areal energy and power density of the liquid-state on-chip micro-supercapacitor are 11.7 μWh/cm2 and 0.42 mW/cm2, respectively, while those of the solid-state on-chip micro-supercapacitor are 10.8 μWh/cm2 and 0.78 mW/cm2.

High aspect ratio silicon nanowires control fibroblast adhesion and cytoskeleton organization

Cell–cell and cell–matrix interactions are essential to the survival and proliferation of most cells, and are responsible for triggering a wide range of biochemical pathways. More recently, the biomechanical role of those interactions was highlighted, showing, for instance, that adhesion forces are essential for cytoskeleton organization. Silicon nanowires (Si NWs) with their small size, high aspect ratio and anisotropic mechanical response represent a useful model to investigate the forces involved in the adhesion processes and their role in cellular development. In this work we explored and quantified, by single cell force spectroscopy (SCFS), the interaction of mouse embryonic fibroblasts with a flexible forest of Si NWs. We observed that the cell adhesion forces are comparable to those found on collagen and bare glass coverslip, analogously the membrane tether extraction forces are similar to that on collagen but stronger than that on bare flat glass. Cell survival did not depend significantly on the substrate, although a reduced proliferation after 36 h was observed. On the contrary both cell morphology and cytoskeleton organization revealed striking differences. The cell morphology on Si-NW was characterized by a large number of filopodia and a significant decrease of the cell mobility. The cytoskeleton organization was characterized by the absence of actin fibers, which were instead dominant on collagen and flat glass support. Such findings suggest that the mechanical properties of disordered Si NWs, and in particular their strong asymmetry, play a major role in the adhesion, morphology and cytoskeleton organization processes. Indeed, while adhesion measurements by SCFS provide out-of-plane forces values consistent with those measured on conventional substrates, weaker in-plane forces hinder proper cytoskeleton organization and migration processes.

Passivation of high aspect ratio silicon nanowires by using catalytic chemical vapor deposition for radial heterojunction solar cell application

High aspect ratio silicon nanowires (SiNWs) prepared by metal-assisted chemical etching were passivated by using catalytic chemical vapor deposition (Cat-CVD).

On the Use of Scalable NanoISFET Arrays of Silicon with Highly Reproducible Sensor Performance for Biosensor Applications.

As a prerequisite to the development of real label-free bioassay applications, a high-throughput top–down nanofabrication process is carried out with a combination of nanoimprint lithography, anisotropic wet-etching, and photolithography methods realizing nanoISFET arrays that are then analyzed for identical sensor characteristics. Here, a newly designed array-based sensor chip exhibits 32 high aspect ratio silicon nanowires (SiNWs) laid out in parallel with 8 unit groups that are connected to a very highly doped, Π-shaped common source and individual drain contacts. Intricately designed contact lines exert equal feed-line resistances and capacitances to homogenize the sensor response as well as to minimize parasitic transport effects and to render easy integration of a fluidic layer on top. The scalable nanofabrication process as outlined in this article casts out a total of 2496 nanowires (NWs) on a 4 inch p-type silicon-on-insulator (SOI) wafer, yielding 78 sensor chips based on nanoISFET arrays. The sensor platform exhibiting high-performance transistor characteristics in buffer solutions is thoroughly characterized using state-of-the-art surface and electrical measurement techniques. Deploying a pH sensor in liquid buffers after high-quality gas-phase silanization, nanoISEFT arrays demonstrate typical pH sensor behavior with sensitivity as high as 43 ± 3 mV·pH–1 and a device-to-device variation of 7% at the wafer scale. Demonstration of a high-density sensor platform with uniform characteristics such as nanoISFET arrays of silicon (Si) in a routine and refined nanofabrication process may serve as an ideal solution deployable for real assay-based applications.

Reduced porosity in metal‐assisted chemical etching of vertical Si nanowire arrays by an induced magnetic field

High aspect ratio silicon nanowires (Si NWs) are produced by metal‐assisted chemical etching (MacEtch) combined with a magnetic field. The vertically applied magnetic field enhances the adhesion between a catalytic metal film and a semiconductor surface. As a result, very uniform Si NWs are formed with increased etch rate due to an easy transfer of holes from metal to Si. Importantly, the porosity of the Si NWs is dramatically reduced by an applied magnetic field because the metal film quickly sinks into the Si, thereby decreasing the excess hole diffusion from the NW sidewall. The combined process of MacEtch and a magnetic field is a promising approach to form high aspect ratio Si NWs with minimized etching damage.

Porosity Control and Transfer in Silicon Nanostructures through Electrochemical & Chemical Etching

Porous silicon particles and nanostructures are receiving growing interest from the scientific community. Two important parameters usually used to define a porous material are porosity and pore size. However, internal surface area and pore morphology are also of high importance, as they determine the material performances in many applicative domains such as Li-ion batteries (1), catalysis, separation, drug delivery (2) etc. High surface area porous silicon structures were prepared through silicon anodization in acidic HF electrolyte under galvanostatic control. The layers were then either taken off mechanically, forming powders, or subjected to a metal-assisted chemical etching (MaCE) post-treatment to produce high aspect ratio silicon nanowires through the depth of the porous film. In the first scenario, careful attention was paid to the electrolyte composition in order to increase the internal surface area of the powders. In acidic solutions (i.e. HF mixed with strong acids such as HCl or H2SO4), powders with surface area exceeding 850 m²/g were achieved by lowering the average pore size to around 3 nm, whilst maintaining moderate porosity (~ 65%) (3). In the latter scenario, MaCE (4) on porous silicon thin films facilitated the transfer of the parameters defining the mesoporous framework (porosity, pore diameter, surface area, pore orientation) from the thin film to high aspect ratio nanowires. This consisted of periodic modulation of the porosity with depth and applying MaCE post-treatment as illustrated by electron microscopy images, below, the nanowires clearly displayed the porosity gradient of the original porous silicon thin film. The control of both anodization conditions, through an accurate choice of the silicon wafer doping type and level and electrolyte composition, to achieve ultra-high surface area porous powder, and porous layer post-treatment such as MaCE, to convert the porous framework from thin film to nanowires, provide new and promising opportunities in many application fields. X. Li, M. Gu, S. Hu, R. Kennard, P. Yan, X. Chen, C. Wang, M.J. Sailor, J.G. Zhang and J. Liu Nat. Comm., 5, 4105 (2014).C. Chiappini, X. Liu, J.R. Fakhoury and M. Ferrari, Adv. Funct. Mater., 20, 2231 (2010).A. Loni, T. Defforge, E. Caffull, G. Gautier and L.T. Canham, Micro. Meso. Mater., (2015): DOI:10.1016/j.micromeso.2015.03.006Z.Huang, N.Geyer, P.Werner, J.de Boor, U.Gosele. Adv.Mater23 : 285 (2011) Figure 1

One dimensional silicon nanostructures prepared by oxidized porous silicon under heat treatment

One dimensional high aspect ratio Si nanostructures were prepared by using oxidized sponge like nanostructured porous silicon (pSi) as a seed material. This can be considered as a complementary technique to synthesize silicon nanowires such as vapour–liquid–solid method (VLS). One dimensional silicon nanostructures were fabricated by subjecting pSi to heat treatment without metal assistance. It is shown that the aspect ratio can be tuned by controlling the concentration of oxygen (SiO2) and the porosity of the seed material (pSi). The atomic percentage of oxygen incorporated into pSi was estimated by Energy Dispersive X-ray Spectroscopy (EDS). Field Emission Scanning Electron Microscope (FESEM) confirms unambiguously the formation of silicon nanowires. The broad peak observed around 490cm−1 in Raman spectra further confirms the formation of Si NWs. At higher oxygen concentration, narrower (∼20nm) and longer (∼1μm) silicon nanowires have been achieved. The observed change in photoluminescence (PL) peak position towards lower wavelength as a function of the aspect ratio of Si NWs is in good agreement with quantum confinement effects. This work demonstrates a new oxide assisted method to prepare high aspect ratio silicon nanowires without using any metal catalysts.

Wafer-Scale, Highly-Ordered Silicon Nanowires Produced by Step-and-Flash Imprint Lithography and Metal-Assisted Chemical Etching

ABSTRACTA combinatory approach of Step-and-Flash Imprint Lithography (SFIL) and Metal-Assisted Chemical Etching (MacEtch) was used to generate near perfectly-ordered, high aspect ratio silicon nanowires (SiNWs) on 4" silicon wafers. The ordering and shapes of SiNWs depends only on the SFIL nanoimprinting mould used, thereby enabling arbitary SiNW patterns not possible with nanosphere and interference lithography (IL) to be generated. Very densely packed SiNWs with periodicity finer than that permitted by conventional photolithography can be produced. The height of SiNWs is, in turn, controlled by the etching duration. However, it was found that very high aspect ratio SiNWs tend to be bent during processing. Hexagonal arrays of SiNW with circular and hexagonal cross-sections of dimensions 200nm and less were produced using pillar and pore patterned SFIL moulds. In summary, this approach allows highlyordered SiNWs to be fabricated on a wafer-level basis suitable for semiconductor device manufacturing.

Synthesis, Characterization and Kinetics of Epitaxial-Oriented Silicon Nanowire Arrays on Si Substrates

Abstract The fabrication of vertical-oriented, high aspect ratio silicon nanowires (SiNWs) with controllable density and length is of interest for the development of nanowire-based electronics and photovoltaic devices. Here we reported a both simple and economical method for synthesizing large-area epitaxial-oriented SiNW arrays, which was achieved on the Si (111) substrates by Au catalyzed vapor-liquid-solid mechanism using the conventional chemical vapor deposition furnace system. Their morphologies and microstructures were investigated with scanning electron microscopy and transmission electron microscopy, respectively. The results showed that most of nanowires were vertically grown on substrates, their density and length can be well controlled. As-grown SiNW is composed of a single crystalline silicon core and a thin amorphous silicon oxide coating layer. Furthermore, their growth kinetics was discussed in detail. It indicates that there are both the substrate-nanowire Si adatom surface diffusion and the slight radial growth during the upgrowth of nanowire, and besides, the migration of Au on the sidewall of nanowire was also found for such epitaxial-oriental SiNWs.

Surface roughness and electron backscattering in high aspect ratio silicon nanowires

Four contact current voltage characteristics of high aspect ratio, moderately doped silicon nanowires will be presented and discussed. A nonlinear behavior of the current as a function of the voltage drop has been detected, at room temperature, in small silicon nanowires: the current increases quadratically with respect to the voltage drop increasing. The dependency of this nonlinear behavior with temperature is reported.In this work it will be shown that a possible explanation of this effect can be given taking in account the silicon nanowire surface roughness, that drives the carrier backscattering. This hypothesis is supported by Monte Carlo simulations based on a simple model. The simulation results are in qualitative agreement with the experimental data.