Thick HfO2 Research Articles

The thickness measurement of ultrathin films from new high-k material HfO2 by grazing incidence x-ray reflectivity

The thickness of HfO2 ultrathin films was determined by grazing incidence x-ray reflectivity (GIXRR) with simulation. Two samples were prepared by atomic layer deposition, and the Si substrate of one sample was treated by HF acid (1:20) to erase the native oxide layer, while the other was not. According to the GIXRR, the films consisted of two contamination layers, an interface layer, a HfO2 layer and a native oxide layer (except for the acid-treated sample) from top to bottom. As a result, the HfO2 thickness of the two samples was 1.23 nm and 1.25 nm respectively, and the thicknesses of the interface layers between the HfO2 and the Si substrate were 0.1 nm and 0.95 nm respectively. The chemical states of the film were investigated by ultrasonification and x-ray photoemission spectroscopy (XPS), and the thickness was verified by transmission electron microscopy (TEM). All these phenomena proved that GIXRR is a powerful and effective piece of technology for characterizing HfO2 ultrathin film.

Atomic layer deposition of HfO2 on graphene through controlled ion beam treatment

The polymer residue generated during the graphene transfer process to the substrate tends to cause problems (e.g., a decrease in electron mobility, unwanted doping, and non-uniform deposition of the dielectric material). In this study, by using a controllable low-energy Ar+ ion beam, we cleaned the polymer residue without damaging the graphene network. HfO2 grown by atomic layer deposition on graphene cleaned using an Ar+ ion beam showed a dense uniform structure, whereas that grown on the transferred graphene (before Ar+ ion cleaning) showed a non-uniform structure. A graphene–HfO2–metal capacitor fabricated by growing 20-nm thick HfO2 on graphene exhibited a very low leakage current (<10−11 A/cm2) for Ar+ ion-cleaned graphene, whereas a similar capacitor grown using the transferred graphene showed high leakage current.

Post-Cleaning Effect on a HfO2 Gate Stack Using a NF3/NH3 Plasma.

The effects of dry cleaning of a HfO2 gate stack using NF3 only and a NF3/NH3 gas mixture plasma were investigated. The plasma dry cleaning process was carried out after HfO2 deposition using an indirect down-flow capacitively coupled plasma (CCP) system. An analysis of the chemical composition of the HfO2 gate stacks by XPS indicated that fluorine was incorporated into the HfO2 films during the plasma dry cleaning. Significant changes in the HfO2 chemical composition were observed as a result of the NF3 dry cleaning, while they were not observed in this case of NF3/NH3 dry cleaning. TEM results showed that the interfacial layer (IL) between the HfO2 and Si thickness was increased by the plasma dry cleaning. However, in the case of NF3/NH3 dry cleaning using 150 W, the IL thickness was suppressed significantly compared to the sample that had not been dry cleaned. Its electrical properties were also improved, including the low gate leakage currents, and reduced EOT. Finally, the finding show that the IL thickness of the HfO2 gate stack can be controlled by using the novel NF3/NH3 dry cleaning process technique without any the significant changes in chemical composition and metal-oxide-semiconductor (MOS) capacitor characteristics.

Ta-Mo Isomorphous Alloy Systems for Metal Gate Apllications

Tantalum-molybdenum (Ta-Mo) thin films with various compositions are deposited on Si and HfO2/Si substrates by rf (radio frequency) magnetron sputtering. The isomorphous Ta-Mo thin film shows an amorphous structure with Mo/Ta rf power at 20/80 W. It is reported that an amorphous structure of gate electrodes can reduce threshold voltage variability among different devices, caused by different orientations of polycrystalline grains [1]. This amorphous layer may eliminate the effect for the fabrication of next generation CMOS devices. Different thicknesses of HfO2 dielectrics (20, 40, 60, 80, and 100 Å) are obtained by metal-organic chemical vapor deposition. The Ta-Mo thin films are deposited on HfO2/Si by cosputtering Ta and Mo targets. The composition of Ta-Mo alloys are controlled by varying the rf power (0/100, 20/80, 40/60, 60/40, 80/20, 100/0 W) on Ta and Mo targets. After that, a TaN layer is deposited on Ta-Mo layers to form a TaN/Ta-Mo/HfO2/Si MOS capacitor. The capacitor is further annealed at 400oC in a N2-H2 mixture for 30 min to study the thermal stability of the gate structure. The crystal structure is identified by grazing incident angle X-ray diffraction. Chemical bonding of Ta-Mo films is characterized by X-ray photoelectron spectroscopy. The resistivity is measured by using a four-point probe. Electrical properties of the MOS capacitors are characterized by capacitance–voltage (C-V) measurements. The work function is extracted from the C-V curves with different thicknesses of HfO2. The GIAXRD result suggests that the Ta and Mo phases appear for Ta-Mo films deposited with Mo/Ta rf power at 0/100 W and 100/0 W, respectively. Both of them are body-centered cubic (BCC) structures. For Ta-Mo thin films deposited with different Mo/Ta rf powers, the structures are also BCC structures, except for film deposited with Mo/Ta rf powers at 20/80 W. It exhibits an amorphous structure. In addition, the lattice constant decreases but the grain size increases as the rf power on Mo targets increases. The physical properties of Ta-Mo films and the effective work functions of the bilayer TaN/Ta-Mo gate electrodes will be addressed. [1] M. E. Grubbs, X. Zhang, M. Deal, Y. Nishi, and B. M. Clemens, Appl. Phys. Lett. 97, 223505 (2010). Figure 1

Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source

This paper presents the low-frequency noise (LFN) behavior of vertical tunnel FETs (TFETs). The experimental input characteristics with different source compositions (Si and Ge) and different HfO2 thicknesses in the gate-stack (2 and 3 nm) are presented. A brief analog parameters analysis, including the transconductance, output conductance, and intrinsic voltage gain behavior under different bias conditions, shows that TFETs are promising for analog applications. For the LFN study, the standard number fluctuations model for MOSFETs was used in order to verify and compare the TFETs noise behavior, exploring the influence of different conduction mechanisms in each bias region. In the proposed model, the effective channel length ( $L_{\mathrm{eff}}$ ) is replaced by the tunneling length, resulting in good agreement between the experimental data and the model. The temperature influence on the TFET noise behavior is also investigated.

THE IMPACT OF (NUMBEROF GATE METALS) ONTHRESHOLD VOLTAGEANDDRAIN-INDUCED BARRIER LOWERING (DIBL) OF CYLINDRICAL GATE ALL AROUND SILICON NANOWIRE MOSFETs

Inthispaper, silicon nanowireJunctionlesstransistors, gateallaround, cylindricalMOSFETs with (four,three and two) metals gateis compared. The gate metals at the source end is with the highest work function called the control gate and the metals at the drain end is with the lowest work function.The gate length is 30 nm and the length of gate metals, are equal.Sio2 thickness of 1 nm, Hfo2 thickness of 3 nm and gatethickness is 2 nm. N D = N S =1 × 10 20 cm − 3 , N G =1 × 10 19 cm − 3 .In this study,simulator Atlas Silvaco device is usedforsimulation. In this paper, the influence ofthe number ofgate metals on theDIBL, Ion, Ioff and threshold voltage been investigated.By increasing thenumber ofgate metals,DIBL and Ioff decreases,but Ion and threshold voltage increases.Therefore, if the number of gate metals is higher then transistor performance is better.

Relaxation Effect in RRAM Arrays: Demonstration and Characteristics

In this letter, two distinct retention degradation regions, a rapid resistance relaxation effect followed by a slow resistance loss process, were observed from high-resistance state (HRS) of HfO x -based resistive random access memory (RRAM) array retention tests. The influence of resistance, thickness of HfO x , baking temperature, and RESET pulsewidth on the relaxation effect for HRS were studied in detail. Random telegraph noise (RTN) characterization suggests that this early loss of data for HRS is due to new oxygen vacancies generation which could shorten the gap between the filament and the TaO x layer. Possible causes were provided to describe the relaxation effect and to understand the RTN characteristics correlated with relaxation effect in RRAM array.

Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors.

The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer.

Electro-plasmonic 2 × 2 channel-routing switch arranged on a thin-Si-doped metal/insulator/semiconductor/metal structure.

Plasmonics as a new field of chip-scale technology is the interesting substrate of this study to propose and numerically investigate a metal/insulator/semiconductor/metal (MISM)-structure 2×2 plasmonic routing switch. As a planar subwavelength arrangement, the presented design has two npn-doped side-coupled dual waveguides whose duty is to route the propagating surface plasmon polaritons through the device. Relying on the MISM structure, which has a MOS-like thin-film arrangement of typically 45 nm doped silicon covered by a layer of 8 nm thick HfO(2) gate insulator, the routing configuration is electrically addressed based on the carrier-induced plasma dispersion effects as an external electro-plasmonic switching control. Finite-element-method-conducted electromagnetic simulations are employed to evaluate the switch optical response at telecom wavelength of λ=1550 nm, due to which the balanced operation measure of extinction ratios larger than 10 dB and insertion losses of around -1.8 dB are obtained for both channels of CROSS and STRAIGHT. Compared with other photonic and plasmonic switching counterparts, this configuration, besides its potential for CMOS compatibility, can be utilized as a high-speed compact building block to sustain higher-speed, more miniaturized, and less consuming electro-optic routing/switching protocols toward complicated optical integrated circuits and systems.

Interfacial and electrical characteristics of a HfO2/n–InAlAs MOS-capacitor with different dielectric thicknesses**Project supported by the National Basic Research Program of China (Grant No. 2010CB327505) and the Advance Research Foundation of China (Grant No. 914xxx803-051xxx111).

A HfO2/n–InAlAs MOS-capacitor has the advantage of reducing the serious gate leakage current when it is adopted in InAs/AlSb HEMT instead of the conventional Schottky-gate. In this paper, three kinds of HfO2/n–InAlAs MOS-capacitor samples with different HfO2 thickness values of 6, 8, and 10 nm are fabricated and used to investigate the interfacial and electrical characteristics. As the thickness is increased, the equivalent dielectric constant εox of HfO2 layer is enhanced and the InAlAs-HfO2 interface trap density Dit is reduced, leading to an effective reduction of the leakage current. It is found that the HfO2 thickness of 10 nm is a suitable value to satisfy the demands of most applications of a HfO2/n–InAlAs MOS-capacitor, with a sufficiently low leakage current compromised with the threshold voltage.

HfO2 dielectric thickness dependence of electrical properties in graphene field effect transistors with double conductance minima

We investigate the electrical properties in back-gated graphene field effect transistors (GFETs) with SiO2 dielectric and different thickness of high-k HfO2 dielectric. The results show that transform characteristic (Ids–Vgs) curves of GFETs are uniquely W-shaped with two charge neutrality point (left and right) in both SiO2 and HfO2 dielectric (SiO2-GFETs and HfO2-GFETs). The gate voltage reduces drastically in HfO2-GFETs compared with that in SiO2-GFETs, and it becomes much smaller with the decline of HfO2 thickness. The left charge neutrality point in Id–Vg curves of all HfO2-GFETs is negative, compared to the positive ones in SiO2-GFETs, which means that there exists n-doping in graphene with HfO2 as bottom dielectric. We speculate that this n-doping comes from the HfO2 layer, which brings fixed charged impurities in close proximity to graphene. The carrier mobility is also researched, demonstrating a decreasing trend of hole mobility in HfO2-GFETs contrast to that in SiO2-GFETs. In a series of HfO2-GFETs with different HfO2 dielectric thickness, the hole mobility shows a tendency of rise when the thickness decreases to 7 nm. The possible reason might be due to the introduced impurities into HfO2 film from atomic layer deposition process, the concentration of which varies from the thickness of HfO2 layer.

Integration of High‐k Oxide on MoS2 by Using Ozone Pretreatment for High‐Performance MoS2 Top‐Gated Transistor with Thickness‐Dependent Carrier Scattering Investigation

A top-gated MoS2 transistor with 6 nm thick HfO2 is fabricated using an ozone pretreatment. The influence to the top-gated mobility brought about by the deposition of HfO2 is studied statistically, for the first time. The top-gated mobility is suppressed by the deposition of HfO2 , and multilayered samples are less susceptible than monolayer ones.

Damage evaluation in graphene underlying atomic layer deposition dielectrics.

Based on micro-Raman spectroscopy (μRS) and X-ray photoelectron spectroscopy (XPS), we study the structural damage incurred in monolayer (1L) and few-layer (FL) graphene subjected to atomic-layer deposition of HfO2 and Al2O3 upon different oxygen plasma power levels. We evaluate the damage level and the influence of the HfO2 thickness on graphene. The results indicate that in the case of Al2O3/graphene, whether 1L or FL graphene is strongly damaged under our process conditions. For the case of HfO2/graphene, μRS analysis clearly shows that FL graphene is less disordered than 1L graphene. In addition, the damage levels in FL graphene decrease with the number of layers. Moreover, the FL graphene damage is inversely proportional to the thickness of HfO2 film. Particularly, the bottom layer of twisted bilayer (t-2L) has the salient features of 1L graphene. Therefore, FL graphene allows for controlling/limiting the degree of defect during the PE-ALD HfO2 of dielectrics and could be a good starting material for building field effect transistors, sensors, touch screens and solar cells. Besides, the formation of Hf-C bonds may favor growing high-quality and uniform-coverage dielectric. HfO2 could be a suitable high-K gate dielectric with a scaling capability down to sub-5-nm for graphene-based transistors.

Resistive switching characteristics of integrated polycrystalline hafnium oxide based one transistor and one resistor devices fabricated by atomic vapor deposition methods

In this work, the bipolar resistive switching (RS) characteristics of polycrystalline hafnium oxide are studied in embedded 1 transistor-1 resistor (1T1R) resistive random access memory (RRAM) devices. The HfO2 films with varied thickness from 15 to 25 nm were grown by the atomic vapor deposition method at 400 °C. The HfO2 films are polycrystalline, as evaluated by applying atomic force microscopy and x-ray diffraction. In addition, current–voltage characteristics of the 1T1R devices were investigated. The forming voltages of 15 nm thick HfO2 films are about 4 V and increase gradually with increasing film thickness. A reproducible resistance switching behavior was observed with a high resistance ratio of ∼20 during DC cycling of 100 times. The observed SET and RESET voltages are about 1.2 and 1.6 V, respectively, indicating that the 1T1R RRAM device can be operated below 2 V. The current–voltage characteristics are discussed in the frame of the quantum point contact model.

Impact of Band-Engineering to Performance of High-k Multilayer Based Charge Trapping Memory**Supported by the National Basic Research Program of China under Grant No 2011CBA00602, and the National Key Scientific and Technological Project under Grant No 2013ZX01032001-001-003.

Impact of band-engineering to the performance of charge trapping memory with HfO2/Ta2O5/HfO2 (HTH) as the charge trapping layer is investigated. Compared with devices with the same total HfO2 thickness, structures with Ta2O5 closer to substrates show larger program/erase window, because the 2nd HfO2 (next to blocking oxide) serving as part of blocking oxide reduces the current tunneling out of/in the charge trapping layer during program and erase. Moreover, trapped charge centroid is modulated and contributed more to the flat-band voltage shift. Further experiments prove that devices with a thicker 2nd HfO2 layer exhibit larger saturate flat-band shift in both program and erase operation. The optimized device achieves a 7 V memory window and good reliability characteristics.

Defect evaluation in InGaAs field effect transistors with HfO2 or Al2O3 dielectric

The performance of InGaAs metal oxide semiconductor field effect transistors with Al2O3 or HfO2 as gate oxide is evaluated and compared. The Al2O3 transistors show the lowest subthreshold slope and mid gap Dit, however, the HfO2 transistors reach a higher maximum transconductance (gmax) due to the higher oxide capacitance. Both high-κ dielectrics show a gm-frequency dispersion due to tunneling into border traps with a negligible activation energy as determined from temperature dependent measurements. The total amount of trapped charge at border traps is lower in the HfO2 devices. Scaling the HfO2 thickness further reduces the gm-frequency dispersion, possibly due to detrapping to the gate electrode.

Study of Hysteresis in Vertical Ge-Source Heterojunction Tunnel-FETs at Low Temperature

Tunnel Field-Effect transistors (TFETs) are promising successors of MOSFETs in future low-power technology nodes, where the carrier injection is based on gate controlled band-to-band tunneling (BTBT) instead of the drift-diffusion as in conventional MOSFETs, leading to low leakage current and low power dissipation (1-2). Another advantage of TFETs is that due to the built-in tunnel barrier, their subthreshold swing (SS) is not limited by ln(10).k.T/q and can reach values smaller than 60mV/dec at room temperature (1-2).The major concern of TFETs is the influence of defects at the channel-gate dielectric interface, in the gate dielectric and in the semiconductor channel, which can lead to trap-assisted tunneling (TAT) and degrade the device SS and performance. In this work, an experimental study of the hysteresis in the IDS-VGS behavior of TFETs with different HfO2 thicknesses has been performed. The influence of low temperature on the hysteresis was also analyzed.The studied devices are vertical gate all-around tunnel field-effect transistors (TFETs). These devices were fabricated at imec, Belgium, according to the flow described in (3) (figure 1).Two process conditions were used with different thicknesses of HfO2 in the gate stack, i.e., 2nm and 3nm, deposited on top of 1nm SiO2 and followed by 5nm TiN and 30nm amorphous Si. A 15nm-thick in-situ boron doped crystalline Ge (c-Ge) source was grown by selective epitaxy to form a Si-Ge heterojunction at the channel-source interface (3).Plotting the drain current (IDS) at room temperature as function of the gate voltage (VGS) for the TFETs with different thicknesses of HfO2 (figure 2), one can observe that the device with the thinner HfO2 (2nm) presents a slightly higher on-current (ION) and a steeper SS. This can be attributed to the better gate-to-channel electrostatic control, due to the reduction of the tunneling path at the source/channel region by increasing the electric field (4-5).In order to study the influence of the oxide trap density (NOT) on the TFET behavior, double sweep curves have been recorded as a function of VGS (figure 3) for a TFET with 3nm and 2nm of HfO2 and temperatures ranging from 300K to 78K.Since at low temperature the influence of TAT and SRH carrier generation is minimized, the BTBT prevails over other mechanisms, resulting in lower SS values upon cooling. Since high interface (6) and oxide trap densities prevent the SS to reach values below the theoretical limit, their detailed study becomes necessary. For VGS higher than 1.3V, the drain current (IDS) is dominated by BTBT, as confirmed by the extracted activation energy, and as expected presents a weak dependence on temperature variation, showing a slight decrease for the lowest temperature. At lower electric field (VGS<1.3V) the TAT is the predominant conduction mechanism, which is strongly temperature dependent, resulting in a relatively high decrease of IDS with the temperature reduction.Focusing on the hysteresis, it is possible to observe that while the device with a thinner HfO2 does not show hysteresis in the whole temperature range, devices with 3nm HfO2 present hysteresis, which increases with decreasing temperature. The hysteresis occurs because when the gate voltage sweep up is performed, the traps in the oxide become charged by electrons injected in the gate, whereas, when the sweep down is performed, the IDS curves are shifted due to the discharge of the traps in the oxide, resulting in a relaxation of the flat band voltage to its original value.The oxide defects are generally slow-state-traps, which are sensitive to temperature at low fields and their density tends to decrease upon heating (7), resulting in a DVGS increase at low temperature. The values of DVGS are summarized in table 1 together with the extracted NOT values at different temperatures.Observing the IDS x 1/T for VGS=0.5V (figure 4), the influence of TAT decreases when the temperature decreases, while the hysteresis increases. This can suggest that there is no important relation between the oxide traps and TAT.(1) W. M. Reddick et al., Appl. Phys. Lett., 67, 494-496, (1995). (2) T. Krishnamohan et al., Tech. Dig. IEDM2008, 947-950, (2008).(3) R. Rooyackers et al., Tech. Dig. IEDM2013, 4, 2, (2012).(4) A. S. Verhulst et al., J. Appl. Phys., 104, 6, (2008).(5) D. Leonelli et al., Solid-State Electronics, 65-66, 28-32, (2011).(6) F. S. Neves et al., EuroSOI2013, 1, 1-2, (2013). (7) J.-Y. Rosaye et al., Journal of Electron Devices, 1, 1-6, (2003). Figure 1

Impact of Gate Stack Dielectric on Intrinsic Voltage Gain and Low Frequency Noise in Ge pMOSFETs

Concerning future high-performance applications, materials such as germanium (Ge) and III/V, have been extensively studied as alternative for the channel region instead of silicon. The high mobility makes Ge a promising channel material for both low power and high performance applications of advanced devices [1]. On the other hand, gate stack engineering is challenging in Ge devices, in view of the higher density of interface states typically observed [2]. This work analyses the influence of gate stack layers (GSL) on intrinsic voltage gain and low frequency noise in planar Ge pMOSFET devices. The GSL is composed of germanium oxide (GeOx), aluminum oxide (Al2O3) and hafnium oxide (HfO2), where both Al2O3 and HfO2film thicknesses were varied. There are also two different plasma powers under evaluation. Furthermore, the analog parameters were analyzed at high temperature, ranging from 25 to 150 °C. The devices used in this work have been fabricated on a p-type silicon substrate at Imec/Belgium. There are four wafers with different dielectric composition as shown in table 1. The planar device dimensions are channel width (W) of 10 µm and channel length (L) of 130, 250, 1 and 10 µm. The low frequency noise (LFN) was measured in linear operation showing no clear impact of the gate stack processing. From the normalized noise power spectral density versus drain current it is derived that the predominant flicker noise is due to trapping by border traps in the gate stack and more specifically in the GeOx layer. Representing the square root of the input-referred voltage noise spectral density (SVG 0.5) versus Id/gmyields the flat-band value (intercept) and the mobility scattering coefficient is obtained from the slope of a linear fit in Fig. 1. Among the studied wafers (figure 2), D20 (which has the thinnest Al2O3 thickness) presents the lowest value of the intrinsic voltage gain (AV) for the channel length range studied due to the degradation of the Early voltage (VEA). Furthermore, for the other wafers no significant AV variation betweem the wafers was observed. It suggests that neither the HfO2 thickness nor the plasma power presented a relevant influence on the AVvalue. Considering that the AV for all studied wafers, except D20, present the same trend at room temperature (figure 2), wafer D18 was chosen to investigate the analog basic parameter performances from 25 to 150 °C. In figure 3 is can be seen that the transconductance (gm) is strongly degraded as the temperature increases due to mobility degradation. On the other hand, the output conductance (gD) presented almost no difference with the temperature rise. Figure 4 focuses on the AV as a function of temperature. It can be seen that AVdecreases 5 dB as the temperature increases from 25 to 150 °C, due to the influence of the gm reduction. [1] J.-H. Han et al., Microelectronic Engineering, v.109, p. 266–269, 2013. [2] V.P.-H Hu et al.,TED, v.60, I. 10, p. 3596 – 3600, October, 2013. [3] S. Takagi et al., Microelectronic Engineering, v.109, p. 389–395, 2013. Figure 1

A study of capacitance–voltage hysteresis in the HfO2/InGaAs metal-oxide-semiconductor system

In this work, we performed a study of capacitance–voltage (C–V) hysteresis in HfO2/InGaAs metal-oxide-semiconductor (MOS) systems. The charge trapping density estimated from the C–V hysteresis is comparable to or even greater than the typical interface state density in high-k/InGaAs MOS systems. Based on an oxide thickness series, it is demonstrated that the magnitude of C–V hysteresis increases linearly with the increasing HfO2 thickness, with the corresponding density of trapped charge being a constant value over the range of oxide thicknesses, indicating that the charge trapping is occurring in a plane near/at the HfO2/InGaAs interfacial transition region. C–V hysteresis with a hold in accumulation was also investigated. It is observed that the C–V hysteresis has a power law dependence on the stress time in accumulation at the initial stage of stressing and tends to reach a plateau for sufficiently long stress times. Moreover, a larger gate voltage used during the stress increases the oxide field, allowing more border traps to be accessed.

Doping profile modification approach of the optimization of HfO x based resistive switching device by inserting AlO x layer

HfO x based resistive switching devices with thin AlO x layer inserted between HfO x and TiN top electrode (TE) and Pt bottom electrode (BE) were fabricated respectively. Both devices show robust bipolar resistive switching phenomenon. Experimental result reveals that TiN/AlO x /HfO x /Pt device with appropriately thick HfO x film shows significant enhancement in performance as compared with other samples, having lower voltage and excellent uniformity. The role of inserted AlO x layer and thickness of HfO x film on resistive switching properties are discussed and clarified through comparative experiments, which is considered to be a doping effect. The experimental result is consistent with the model where resistive switching happens near TiN top electrode (TE) due to partial rupture and reconstruction of conducting filaments (CFs) assisted by the doping. The different doping profiles near top electrode of the samples were confirmed by XPS depth analysis. This work provides detailed information about the optimization of HfO x based resistive switching device by a doping profile modification approach.