Heterojunction Bipolar Transistor Structure Research Articles

Investigation of Hydrogen Flux Influence on InGaP Layer and Device Uniformity

In this study, we conduct a comprehensive examination of the influence of hydrogen (H2) carrier gas flux on the uniformity of epitaxial layers, specifically focusing on the InGaP single layer and the full structure of the InGaP/GaAs heterojunction bipolar transistor (HBT). The results show that an elevated flux of H2 carrier gas markedly facilitates the stabilization of layer uniformity. Optimal uniformity in epitaxial wafers is achievable at a suitable carrier gas flux. Furthermore, this study reveals a significant correlation between the uniformity of the InGaP single layer and the overall uniformity of HBT structures, indicating a consequential interdependence.

Three Terminal Perovskite/Silicon Solar Cell with Bipolar Transistor Architecture

Solar photovoltaic energy is the most prominent candidate to speed up the transition from the existing non-renewable energy system to a more efficient and environmentally friendly one. Currently, silicon cells dominate the photovoltaic market owing to their cost-effectiveness and high efficiency, nowadays approaching the theoretical limit. Higher efficiency can be achieved by tandem devices, where a wide bandgap semiconductor is stacked on top of the silicon cell. Thin-film perovskite technology has emerged as one of the most promising for the development of silicon-based tandems because of the optimal perovskite opto-electronic properties and the fast progress achieved in the last decade. While most of the reported perovskite/silicon tandem devices exploit a two-terminal series connected structure, three-terminal solutions have recently drawn significant attention due to their potential for higher energy yield. In this work, we report for the first time a theoretical study, based on validated optical and electrical simulations, of three-terminal perovskite/silicon solar cells employing a hetero-junction bipolar transistor structure. With respect to other three-terminal tandems proposed so far, the transistor structure can be implemented with rear-contact silicon cells, which are simpler and more common than interdigitated back-contact ones.

Challenges for Sige Bicmos in Advanced-Node SOI

D-band (110-170GHz) spectrum is gaining attention for various applications, including 6G mm-Wave, sub-THz sensing, and radar. These systems require lattice spacing for antenna elements at sub-1mm and a very low loss signal path from antenna to integrated chip. A highly efficient front-end in a very small form factor will be required for these systems. This drives the requirement for a monolithically integrated high-gain, high-efficiency front-end that also leverages the benefits of a high-speed / high-density digital CMOS. Silicon germanium (SiGe) heterojunction bipolar transistors (HBT) integrated along with a high-density CMOS provide such an all-silicon monolithic solution.The US government is fostering the expansion of “unique and differentiated domestic manufacturing” with funding through DARPA’s Technologies for Mixed-mode Ultra Scaled Integrated Circuits (T-MUSIC) [1] program to enable disruptive RF mixed-mode technologies by developing high performance RF analog integrated with advanced digital CMOS. Through the T-MUSIC program, DARPA seeks to: 1) advance RF and mixed-mode devices to support ultra-wideband RF frontends from HF to 100 GHz; 2) integrate those devices with high density digital CMOS electronics at the wafer scale to enable embedded digital intelligence; 3) develop and explore ultra-high resolution broadband mixed-mode circuit building blocks for DoD-relevant applications; 4) explore innovative device topologies and materials to form THz devices in an advanced digital CMOS fabrication platform; and 5) establish a domestic ecosystem that facilitates enduring DoD access to differentiated capabilities for high performance RF mixed-mode SoCs.Under T-MUSIC, GlobalFoundries is demonstrating BiCMOS on 45nm PDSOI, which is the focus of this paper, and 22nm FDSOI CMOS with goals of increasing HBT performance of fT/fMAX from 350/500 GHz to 400/600 GHz and 600/700 GHz. HBTs with fT/fMAX of 380/550GHz GHz have been demonstrated building upon previously published results [2]. This paper will touch on some of the challenges that were encountered in achieving that result and discuss those anticipated in future work.Achieving these results required scaling transistor dimensions. Vertical scaling of the emitter, base and collector layers, with higher doping concentrations, reduces transit time but results in higher current densities and higher electric fields. Lateral scaling of the transistor structure reduces parasitic capacitance and resistance but concentrate the power dissipation in a smaller area. The thermal conductivity of silicon is 148W/m-K whereas that of silicon dioxide is ~1.4W/m-K. Even a thin layer of oxide will significantly increase the self-heating of the HBT. Therefore, we replace the SOI with coplanar epitaxy in regions where the HBTs are formed.The vertical scaling of the HBT requires limiting the thermal cycles that the HBT will experience during processing and suggests forming the HBT as late as possible in the CMOS process. However, the thermal cycles associate with the epitaxy and film depositions to form the HBT impact the CMOS transistors which suggests forming the HBT early in the process. We found a point in the process that offers the best compromise minimizing the impact to the doped-channel PDSOI CMOS while achieving the HBT performance goals. Work is just beginning on integration tradeoffs for FDSOI with metal gate and high-K dielectrics.Advanced-node CMOS processes can form components having smaller dimensions which offers advantages for lateral scaling but also presents challenges for forming the HBT. The contact height in 45nm is significantly less than the height of the HBT structure used in GF’s 9HP process. We changed the formation of the emitter and base so that the emitter and base contacts are almost coplanar in contrast to 9HP where the emitter was almost twice the height of the base. This problem is being further exasperated as we migrate to 22nm.The shrinking of BEOL wiring dimensions, along with the ability of the HBT to drive high currents, presents challenges in designing within limits imposed by electromigration. The use of wider wires is constrained by metal density rules. The use of stacked metal levels and redundant vias impact the parasitic capacitances and resistances of the interconnects.The paper and presentation will review these, and other challenges encountered in achieving BiCMOS integration of SiGe HBTs with fT/fMAX of 380/550GHz GHz [see figure] on a 45nm PDSOI CMOS and touch future work.This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA) and is Approved for Public Release, Distribution Unlimited. The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.[1] https://www.darpa.mil/attachments/T-MUSIC_Proposers%20Day_Presentations_Combined.pdf [2] J. Pekarik et al., 2021 IEEE BCICTS, 2021, pp. 1-4, Figure 1

Performance improvement of three terminal heterojunction bipolar transistor based hybrid solar cell using nano-rods

In this research, performance enhancement of three terminal heterojunction bipolar transistor structure based solar cell (HBTSC) is investigated via implementing perovskite layer as emitter absorber region and nanorods within emitter. For this study, a p-n-p hybrid HBTSC structure has been proposed with MAPbI3/CdS/ACZTSe materials for photon absorber layer, and MgF2 for anti-reflection layer (ARL). The purpose of this research is mainly to optimize emitter (MAPbI3) and CdS nanorods thickness of HBTSC structure therefore boosting device efficiency through optoelectronic and electrical simulations. During obtaining the results, the effects of the surface, Shockley–Read–Hall (SRH) and radiative recombination mechanisms has been considered. Two new proposed structures based on planar MAPbI3/CdS/ACZTSe & MAPbI3/CdS nanorods/CdS/ACZTSe perovskite–kesterite based hybrid HBTSCs has been introduced. The maximum efficiency (η) of 23.45% and short-circuit current density (Jsc) of 39.93 mAcm−2 are obtained for planar MAPbI3/CdS/ACZTSe based perovskite–kesterite HBTSCs with open-circuit voltage (Voc) of 760.05 mV and fill factor (FF) of 77.28%, respectively. As for MAPbI3/CdS nanorods/CdS/ACZTSe based hybrid HBTSCs with η of 27.91%, Jsc of 42.03 mAcm−2, Voc of 786.8 mV, and FF of 84.39%, a total improvement of 4.46% is achieved when compared to planar hybrid perovskite–kesterite HBTSCs structure.

Simulation Study on Novel GaN‐Based n−p−n Heterojunction Bipolar Transistors with a Quaternary AlGaInN Emitter and a Two‐Dimensionally Conductive Base

Herein, a simulation study on novel GaN‐based n−p−n heterojunction bipolar transistors (HBTs) with a quaternary n‐AlGaInN emitter and a thin GaInN quantum well (QW) layer inserted in its p‐GaN base is reported. The idea of the quaternary AlGaInN emitter facilitates the design and independent growth of the energy bandgaps and lattice strain. In addition, the p‐GaN base inserted with the thin GaInN QW is expected to be effective in enhancing its lateral conduction via 2D hole gases (2DHGs). The simulation results indicate that the designed GaInN QW definitely functions to generate and transport the 2DHGs and ultimately contributes to the improvement of the device performance. In other words, the lateral resistivity of the p‐GaN base is reduced from 1.8 × 10−1 to 7.0 × 10−2 Ω cm with the use of the GaInN QW insertion layer. Further, the simulation study focusing on the lateral distance between the n‐emitter and p‐base electrodes exhibits stable device characteristics for the HBT with the GaInN QW insertion layer compared with the conventional HBT structure. Dynamic analysis of the carrier concentration distribution indicates that the QW functions as a low‐resistance current path and it has the effect of avoiding the punch‐through phenomenon.

Design and simulation of integration of vertical cavity surface emitting lasers and heterojunction bipolar transistor

Vertical cavity surface emitting lasers (VCSELs) are widely used in the field of short-range optical communication and optical interconnection because of their advantages such as low threshold current, large modulation bandwidth, easy two-dimensional integration, easy coupling with optical fibers and low cost. The VCSELs and heterojunction bipolar transistor (HBT) are longitudinal current devices, so they can be well integrated on the same wafer, and the output light power can be modulated by the HBT base current. Integration of VCSELs and HBT are designed in this paper. The VCSELs and PNP InGaP/GaAs HBT form a direct series structure. The reflectivity of DBR is 99.72% at a resonant wavelength of 850 nm and 99.57% after adding HBT separately. Therefore, the addition of HBT has little influence on the reflectivity of DBR at the resonant wavelength. The electro-optical characteristics of the integrated structure are simulated by using PICS3D software. An interim collector is added into the model in order to ensure that the simulation can be carried out smoothly. Firstly, HBT is conducted and the current flows from the emitter to the interim collector. Then, the voltage across the interim collector and the N-type electrode is increased to make VCSELs conducted and the current of the transition collector drop to zero. The interim collector can be removed from the actual structure because the current is zero. The simulation results show that the current gain coefficient is 400, and the maximum modulation rate of the base current to the output light power rises up to 280 mW/mA. The maximum temperature in the active region increases with the base current increasing, and the output light power first increases and then tends to be saturated. The ac optical gain characteristics of the integrated structure is simulated by PICS3D, and the simulation result shows that cutoff frequency exceeds 1 GHz. The addition of HBT limits the modulation rate of the integrated structure, and further optimization of HBT structure parameters and geometric dimension are needed to improve the modulation rate. The integrated structure and simulation method established in this paper can also be used to integrate LED, LD, DFB or other luminescent devices with HBT.

Isolation of Hole Versus Electron Current at p-Si/TiO2 Selective Contact Using a Heterojunction Bipolar Transistor Structure

Carrier-selective contacts provide an exciting avenue for developing high-efficiency, low-cost silicon photovoltaics (PV). However, evaluating and understanding the different current mechanisms across a carrier-selective contact is difficult as the current measured represents the sum of both electron and hole current components. In this paper, we develop a heterojunction bipolar transistor (HBT) structure with the electron-selective p-type Si/titanium dioxide(TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )/Al contact as the base-emitter junction, which enables one to separately measure the electron and hole currents across the selective contact. An HBT with a current gain as large as ~220 is achieved. The method is then used to evaluate the current mechanisms across a p-Si/TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al heterojunction PV cell, where the TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /p-Si replaces the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -p junction. We determine that there is an optimal TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> thickness of 4.1 nm for CVD-deposited TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ; and at the optimal thickness, the hole current is 8% of the total current, thus demonstrating that TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si is indeed a hole-blocking electron-selective contact. The hole current ratio is corroborated with reverse-recovery experiments, confirming the validity of the HBT method.

Single-Event Upset Mitigation in a Complementary SiGe HBT BiCMOS Technology

The single-event upset response of SiGe-based digital circuits designed in a third-generation, bulk C-SiGe ( npn + pnp ) BiCMOS platform is investigated. Heavy-ion, broad-beam experiments across data rate, incidence angle, and bit stream pattern show that the pnp -based shift registers exhibit significant reductions in error cross section when compared with npn -only designs. Ion-strike simulations using 3-D TCAD models agree with the experimental findings, where the pnp SiGe heterojunction bipolar transistor (HBT) exhibits reduced sensitive area and transient duration, leading to large reductions in collected charge at the collector (output) terminal. The circuit-level, heavy-ion measurements are in agreement with previous device-level, pulsed-laser studies, where the single-event effect (SEE) improvement of pnp SiGe HBTs was attributed to the n-well isolation layer present in the vertical material stack of the pnp SiGe HBT structure. These results provide confirmation that precision analog, RF/mm-wave, and high-speed digital applications utilizing unhardened, high-performance bulk pnp SiGe HBTs should benefit from an inherently improved SEE response.

GaAsP/InGaP HBTs grown epitaxially on Si substrates: Effect of dislocation density on DC current gain

Heterojunction bipolar transistors (HBTs) with GaAs0.825P0.175 bases and collectors and In0.40Ga0.60P emitters were integrated monolithically onto Si substrates. The HBT structures were grown epitaxially on Si via metalorganic chemical vapor deposition, using SiGe compositionally graded buffers to accommodate the lattice mismatch while maintaining threading dislocation density at an acceptable level (∼3 × 106 cm−2). GaAs0.825P0.175 is used as an active material instead of GaAs because of its higher bandgap (increased breakdown voltage) and closer lattice constant to Si. Misfit dislocation density in the active device layers, measured by electron-beam-induced current, was reduced by making iterative changes to the epitaxial structure. This optimized process culminated in a GaAs0.825P0.175/In0.40Ga0.60P HBT grown on Si with a DC current gain of 156. By considering the various GaAsP/InGaP HBTs grown on Si substrates alongside several control devices grown on GaAs substrates, a wide range of threading dislocation densities and misfit dislocation densities in the active layers could be correlated with HBT current gain. The effect of threading dislocations on current gain was moderated by the reduction in minority carrier lifetime in the base region, in agreement with existing models for GaAs light-emitting diodes and photovoltaic cells. Current gain was shown to be extremely sensitive to misfit dislocations in the active layers of the HBT—much more sensitive than to threading dislocations. We develop a model for this relationship where increased base current is mediated by Fermi level pinning near misfit dislocations.

Low-voltage triggering SCRs for ESD protection in a 0.35 μm SiGe BiCMOS process

A heterojunction bipolar transistor (HBT) trigger Silicon Controlled Rectifier (SCR) device (HTSCR) in the 0.35μm Silicon-germanium (SiGe) BiCMOS technology is proposed for Electrostatic Discharge (ESD) protection in this paper. The trigger voltage of the HTSCR is decided by the collector-to-emitter breakdown voltage of the HBT structure in floating base configuration (BVCEO). The underlying physical mechanisms critical to the trigger voltage are demonstrated based on the transmission line pulsing (TLP) measurement results and physics-based simulation results. The experiment results show that the trigger voltage of the fabricated HTSCR reduces to less 64% of that of the conventional MLSCR, and It2 of the HTSCR is 80% more than that of the conventional MLSCR. In order to reduce the chip area, an optimized HTSCR (OHTSCR) is also proposed. The OHTSCR has a smaller layout area and a lower trigger voltage.

A novel HBT trigger SCR in 0.35 μm SiGe BiCMOS technology**Project supported by the Central Universities Fundamental Research Project (No. ZYGX2015J035) and the Sichuan Science and Technology Support Project (No. 2016GZ0115).

The silicon-controlled rectifier (SCR) device is known as an efficient electrostatic discharge (ESD) protection device due to the highest ESD robustness in the smallest layout area. However, SCR has some drawbacks, such as high trigger voltage and low holding voltage. In order to reduce the trigger voltage of the SCR device for ESD protection, a new heterojunction bipolar transistor (HBT) trigger silicon controlled rectifier (HTSCR) device in 0.35 μm SiGe BiCMOS technology are proposed. The underlying physical mechanisms critical to the trigger voltage are demonstrated based on transmission line pulsing (TLP) measurement and physics-based simulation results. The simulation results prove that the trigger voltage of the HTSCR is decided by the collector-to-emitter breakdown voltage of the HBT structure in floating base configuration. The ESD experiment test results demonstrate the HTSCR can offer superior performance with a small trigger voltage, an adjustable holding voltage and a high ESD robustness. In comparison to the conventional MLSCR, the trigger voltage of the fabricated HTSCR can reduce to less than 50% of that of the MLSCR, and the It2 of the HBT trigger SCR is 80% more than that of the MLSCR.

A Study on Self-Heating and Mutual Thermal Coupling in SiGe Multi-Finger HBTs

In this paper, the self-heating and mutual thermal coupling in a state-of-the-art SiGe:C multi-finger heterojunction bipolar transistor (HBT) was investigated in static dc operation conditions. Multi-finger HBT structure was created using Sentaurus structure editor with dimensions similar to the layout of SiGe:C multi-finger HBTs in ST-Microelectronics BiCMOS55 (B55) technology (f T > 300 GHz, f max > 400 GHz) as per ST’s BiCMOS55 process design kit guidelines. Three-dimensional thermal technology computer aided design (TCAD) simulations were carried out to obtain the temperature distribution in static dc operation. The lattice temperature (T Lattice) and heat flux (F Heat) distribution inside the device were studied. The impact of back-end-of-line (BEOL) layers on static thermal behavior of the state-of-the-art SiGe:C multi finger HBTs was also investigated. The temperature dependent thermal resistance of different fingers of the trench isolated SiGe multi-finger HBT was extracted without and with back-end-of-line (BEOL) effect. An electro-thermal dc compact model of self-heating and mutual thermal coupling in multi-finger HBTs was proposed and applied to compare the modeling results with the TCAD simulation results. Very good agreement was achieved between results obtained from TCAD simulation and those obtained from compact model-based simulation.

(Invited) Monolithic Integration of III-V As- and P-Based Devices on Si through Direct MBE Growth and Using Lattice Engineered Substrates

Mainstream silicon (Si) CMOS technology is finally experiencing limitations of pure Si-based material and process. For digital electronics, to extend Moore’s law, the industry increasingly is investigating alternative materials and technologies to enhance channel transport properties and reduce power dissipation for future generation transistor circuitry. Heterogeneous integration of compound III-V semiconductor devices on Si may realize high performance integrated circuits for analog and digital applications and can incorporate optoelectronic components for high-speed data transfer. Such integration provides the combined advantages of high volume production of Si-based electronic circuitry with superior high-speed performance of III-V components. At IQE, we developed molecular beam epitaxy (MBE) growth processes for the production of high quality III-V based transistor structures monolithically integrated onto CMOS-compatible substrates by direct MBE growth on Si wafers and also by utilization of specialized Si-on-Lattice-Engineered-Substrate (SOLES) substrates. Through work with industry partners, IQE has grown InP-based high electron mobility transistor (HEMT) and quantum well field effect transistor (QWFET) structures directly on Si substrates by MBE. Following a high-K gate dielectric fabrication process, QWFET devices demonstrated high transconductance of 1750μS/μm and high drive current of 0.49mA/μm at VDS=0.5V. [1] As part of a program funded by the US Defense Advanced Research Projects Agency, IQE developed a direct MBE growth approach of an InP-based heterojunction bipolar transistor (HBT) structure on the SOLES substrates, and together with our collaborators successfully created clusters of high-speed III-V HBT circuitry monolithically integrated side-by-side with Si CMOS on the same wafer. [2] In this paper, we will discuss structural and electronic properties of epitaxial device material, including dislocation filtering in the mismatched metamorphic buffers, and compare performance of devices fabricated on Si with reference material grown on lattice-matched InP substrates. [1] Radosavljevic, M.; Chu-Kung, B.; Corcoran, S.; Dewey, G.; Hudait, M. K.; Fastenau, J. M.; Kavalieros, J.; Liu, W. K.; Lubyshev,D.; Metz, M.; Millard, K.; Mukherjee, N.; Rachmady, W.; Shah, U.; Chau, R. (2009), IEDM Tech. Dig., p.13.1. [2] W. K. Liu, D. Lubyshev, J. M. Fastenau, Y. Wu, M. T. Bulsara, E. A. Fitzgerald, M. Urteaga, W. Ha, J. Bergman, B. Brar, W. E. Hoke, J. R. LaRoche, K. J. Herrick, T. E. Kazior, D. Clark, D. Smith, R. F. Thompson, C. Drazek, and N. Daval, J. Crystal Growth, 311, 1979 (2009).

A comparison of 100 MeV oxygen ion and 60Co gamma irradiation effects on advanced 200 GHz SiGe heterojunction bipolar transistors

The third-generation (200 GHz) silicon–germanium heterojunction bipolar transistors were irradiated with 100 MeV oxygen [O7+] ions in the dose range from 1 to 100 Mrad. The different electrical characteristics like forward-mode and inverse-mode Gummel characteristics, the normalized base current, excess base current, the current gain, damage constant, neutral base recombination, avalanche multiplication and the output characteristics were measured before and after irradiation. The ion irradiation results were compared with 60Co gamma irradiation results to understand the linear energy transfer effects on the electrical characteristics on silicon–germanium heterojunction bipolar transistors. The stopping range of ions in matter simulation study was conducted to understand the energy loss of 100 MeV O7+ ions in silicon–germanium heterojunction bipolar transistor structure.

Effect of ultrathin AlN spacer on electronic properties of GaN/SiC heterojunction bipolar transistors

GaN/SiC heterojunction bipolar transistors (HBTs) with an ultrathin AlN spacer layer at the n-GaN/p-SiC emitter junction are proposed for the control of the electronic properties of GaN/SiC heterojunctions. The insertion of an AlN spacer is found to be promising in terms of improving electron injection efficiency owing to the reduced potential barrier (0.54 eV) to electron injection and reduced recombination via interface traps. We also investigated the effect of pre-irradiation of active nitrogen atoms (N*) prior to AlN growth for the control of the electronic properties of GaN/AlN/SiC heterojunctions. We found that the potential barrier was further reduced to 0.46 eV by N* pre-irradiation. The HBT structure was successfully fabricated using our newly developed process featuring ion implantation and Pd ohmic contacts to obtain a low contact resistivity to a p-SiC base at a temperature as low as 600 °C. A fabricated HBT without an AlN layer showed a low current gain (α ∼ 0.001), whereas the GaN/AlN/SiC HBT showed improved current gains of 0.1 in the case of using a 1-nm-thick AlN spacer without N* pre-irradiation and 0.2 in the case of using a 2-nm-thick AlN spacer with N* pre-irradiation.

Analytical Approach to Design of Proportional-to-the-Absolute-Temperature Current Sources and Temperature Sensors Based on Heterojunction Bipolar Transistors

Embedded temperature sensors based on proportional-to-the-absolute-temperature (PTAT) current sources have the potential to lay the foundation for low-cost temperature-aware integrated circuit architectures if they meet the requirements of miniaturization, fabrication process match, and precise estimation in a wide range of temperatures. This paper addresses an analytical approach to the minimum-element PTAT circuit design capitalizing on the physics-based modeling of the heterojunction bipolar transistor (HBT) structures. It is shown that a PTAT circuit can be implemented on only two core HBT elements with good accuracy. Derived parametric relations allow a straightforward specification of the thermal gain at the design stage, which affects sensor sensitivity. Further derived current-to-temperature mapping expresses a temperature estimate based on the measured PTAT output current. Numerical examples indicate attainable estimation accuracy of 0.43% in case of a measurement instance taken in the absence of measurement noise.

Degradation Mechanisms for GaN and GaAs High Speed Transistors

We present a review of reliability issues in AlGaN/GaN and AlGaAs/GaAs high electron mobility transistors (HEMTs) as well as Heterojunction Bipolar Transistors (HBTs) in the AlGaAs/GaAs materials systems. Because of the complex nature and multi-faceted operation modes of these devices, reliability studies must go beyond the typical Arrhenius accelerated life tests. We review the electric field driven degradation in devices with different gate metallization, device dimensions, electric field mitigation techniques (such as source field plate), and the effect of device fabrication processes for both DC and RF stress conditions. We summarize the degradation mechanisms that limit the lifetime of these devices. A variety of contact and surface degradation mechanisms have been reported, but differ in the two device technologies: For HEMTs, the layers are thin and relatively lightly doped compared to HBT structures and there is a metal Schottky gate that is directly on the semiconductor. By contrast, the HBT relies on pn junctions for current modulation and has only Ohmic contacts. This leads to different degradation mechanisms for the two types of devices.

Design of a 250-Gbit/s SiGe HBT Electrooptic Modulator

We present a rigorous electrical and optical analysis of a highly scaled, graded-base, SiGe heterojunction bipolar transistor (HBT) electrooptic (EO) modulator. In this study, we propose a 2-D electrical model and a 3-D optical model for a graded-base SiGe HBT structure that is capable of operating at a data bit rate of 250 Gbit/s or higher. In this structure, apart from a polysilicon/low doped emitter <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$( \hbox{width} = 90\ \hbox{nm})$</tex></formula> and a strained SiGe graded base <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$( \hbox{depth} = 8.5\ \hbox{nm})$</tex></formula> , a selectively implanted collector (SIC) <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(\hbox{depth} = 26\ \hbox{nm})$</tex></formula> is introduced. Furthermore, at a base-emitter swing of 0 to 1.0 V, this model predicts a rise time of 3.48 ps and a fall time of 0.55 ps. Optical simulations predict a <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\pi$</tex></formula> phase shift length <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(L_{\pi})$</tex></formula> of 204 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu \hbox{m}$</tex></formula> , with an extinction ratio of 13.2 dB at a wavelength of 1.55 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu\hbox{m}$</tex></formula> .

Accurate Calculation of Junction Temperature of HBTs

Heterojunction bipolar transistors (HBTs) offer high power and linearity for microwave and mixed-signal applications. The large-signal performance of an HBT is frequently limited by the maximum operating current, which is set by thermal considerations. Hence, an accurate determination of the junction temperature in HBT devices and the corresponding microwave/millimeter-wave monolithic integrated circuits (MMICs)/DAC is critical to achieving maximum performance while maintaining reliable operation. An original accurate closed-form expression is presented for the thermal resistance of HBT structures from which the maximum junction temperature can be determined. The model's validity is verified by numerical simulations and experimental data. The model agrees with two sets of experimental data to within 2% and 6%. The closed-form solution offers device and MMIC designers a fast assessment of the performance and reliability of devices and circuits. Circuit optimization for required performance can be achieved efficiently.

Modeling and Analysis of an 80-Gbit/s SiGe HBT Electrooptic Modulator

We present a rigorous electrical and optical analysis of a strained and graded base SiGe Heterojunction Bipolar Transistor (HBT) electrooptic (EO) modulator. In this paper, we propose a 2-D model for a graded base SiGe HBT structure that is capable of operating at a data bit rate of 80 Gbit/s or higher. In this structure, apart from a polysilicon/monosilicon emitter <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(\hbox{Width} = 0.12\ \mu\hbox{m})$</tex> </formula> and a strained SiGe graded base <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(\hbox{Depth} = 40\ \hbox{nm})$</tex> </formula> , a selectively implanted collector (SIC) <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(\hbox{Depth} = 0.6\ \mu \hbox{m})$</tex></formula> is introduced. Furthermore, the terminal characteristics of this new device modeled using MEDICI are closely compared with the SiGe HBT in the IBM production line, suggesting the possibility of fast deployment of the EO modulator using established commercial processing. At a subcollector depth of 0.4 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula> and at a base-emitter swing of 0 to 1.1 V, this model predicts a rise time of 5.1 ps and a fall time of 3.6 ps. Optical simulations predict a <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\pi$</tex></formula> phase shift length <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$({ \rm L}_{\pi})$</tex></formula> of 240.8 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula> with an extinction ratio of 7.5 dB at a wavelength of 1.55 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula> . Additionally, the tradeoff between the switching speed, <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$L_{\pi}$</tex></formula> and propagation loss with a thinner subcollector is analyzed and reported.