Single-Event Upset Mitigation in a Complementary SiGe HBT BiCMOS Technology

Abstract

The single-event upset response of SiGe-based digital circuits designed in a third-generation, bulk C-SiGe ( npn + pnp ) BiCMOS platform is investigated. Heavy-ion, broad-beam experiments across data rate, incidence angle, and bit stream pattern show that the pnp -based shift registers exhibit significant reductions in error cross section when compared with npn -only designs. Ion-strike simulations using 3-D TCAD models agree with the experimental findings, where the pnp SiGe heterojunction bipolar transistor (HBT) exhibits reduced sensitive area and transient duration, leading to large reductions in collected charge at the collector (output) terminal. The circuit-level, heavy-ion measurements are in agreement with previous device-level, pulsed-laser studies, where the single-event effect (SEE) improvement of pnp SiGe HBTs was attributed to the n-well isolation layer present in the vertical material stack of the pnp SiGe HBT structure. These results provide confirmation that precision analog, RF/mm-wave, and high-speed digital applications utilizing unhardened, high-performance bulk pnp SiGe HBTs should benefit from an inherently improved SEE response.