Performance Of Heterojunction Bipolar Transistors Research Articles

(Invited) Epitaxial Process Development and Challenges for Advanced SiGe BiCMOS

Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) are used daily, mainly in the communication field. Their co-integration with Complementary Metal Oxide Semiconductor (CMOS) technology, i.e. BiCMOS, enables versatile microchips that combine analog, radio-frequency and digital functions. Applications that drive the development of BiCMOS technologies today are Low Earth Orbit (LEO) satellite communications, for which the minimum noise figure of SiGe HBT (NFMIN) between 10 and 30 GHz is one of the most critical figures of merit on the receiver side. It is expected that BiCMOS will play a significant role in the 6G infrastructure, in particular for communications in the D-band spectrum (110-170 GHz), for which the challenge at HBT level is to demonstrate maximum oscillation frequency fMAX > 500 GHz.Benefitting from mature CMOS technologies, the smallest CMOS node used in BiCMOS chips is the 45 nm partially depleted silicon on insulator [1]. STMicroelectronics has been using the 55 nm node since 2014 [2]. These nodes are today sufficient to address the digital content of the targeted circuits, while offering the right performance/cost trade-off. Although the HBT performance depends on lateral scaling too, it is mainly driven by the 1D dopant profile. Multiple Si and SiGe layers are grown by Reduced Pressure-Chemical Vapor Deposition (RP-CVD) epitaxy, defining the core of the device. For a self-aligned architecture such as STMicroelectronics’ EXBIC architecture, four epitaxy steps with different doping levels are required (Fig. 1) [3]. Improvement of key electrical parameters such as NFMIN and fMAX depends on the optimization of these epitaxies.Specifically, the collector epitaxy can be performed by non-selective or selective epitaxy, each with its advantages and drawbacks. Non-selective epitaxy is performed early in the BiCMOS process flow, with no thermal budget impact on the CMOS process. This kind of epitaxy is also cheaper but can cause auto-doping at the epitaxial interface [4] and put constraints on the collector integration, that are solved by the selective epitaxy of the collector. This scheme is used in the latest devices from both STMicroelectronics [3] and GlobalFoundries [5].The transit time of electrons through the base is determined by its thickness and its composition. Significant performance gains have been achieved by switching from pure Si to a graded SiGe base architecture. The bandgap variation due to the graded SiGe composition creates a pseudo-electric field that accelerates the minority carriers transport through the base and limits electron-hole recombination. The addition of carbon into the base limits the boron diffusion and reduces the base thickness, further improving performance. However, only substitutional carbon atoms are required while interstitial carbon atoms must be avoided. The amount of carbon, incorporated in fully substitutional sites, is controlled by the silicon precursor used during RP-CVD epitaxy. At a given temperature it has been shown that a more reactive silicon precursor allows for better substitutional carbon incorporation. By switching from SiH2Cl2 (DCS) to SiH4, the amount of substitutional carbon atoms was increased by 250 % [6]. Following this idea, Si2H6 has been introduced as a silicon precursor to achieve even better substitutional carbon incorporation due to its higher reactivity [7].The emitter process is usually performed by non-selective Si:As epitaxy. This type of epitaxy produces polycrystalline Si:As with a monocrystalline Si:As core above the crystalline base. The emitter resistance can be reduced by processing a fully monocrystalline emitter. A possible solution involving low temperature deposition and solid phase epitaxial regrowth is proposed [8].An overview of the existing problems for each epitaxy step will be given, outlining potential solutions to increase HBT performance to meet customer requirements.[1] J. Pekarik et al., IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 1-4 (2021)[2] P. Chevalier et al., IEEE International Electron Devices Meeting (IEDM),77-79 (2014)[3] A. Gauthier et al., IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 187-190 (2023).[4] P. Jerier and D. Dutartre, J. Electrochem. Soc. 146 ,331 (1999)[5] J. Pekarik et al., ECS Transactions, 109, 141 (2022)[6] F. Brossard et al., International SiGe Technology and Device Meeting (ISTDM), 1-2 (2006)[7] J. Vives et al., ECS Transactions, 109 (4), 237-248 (2022)[8] F. Deprat et al., ECS Transactions, 109, 159 (2022) Figure 1

A parameter extraction method for InP HBT small‐signal model considering emitter–collector laminated capacitance effect

AbstractThe extraction of small‐signal parameters is of great importance for the modeling of InP heterojunction bipolar transistors (HBTs). This letter proposes an improved small‐signal parameter extraction method that considers both the emitter–collector capacitance effect and the current crowding effect. The corresponding parameter extraction procedure based on closed‐form equations is outlined. Furthermore, the model parameter extraction method is validated using two different‐sized InP HBT devices with multibias S‐parameters. The results demonstrate that the established small‐signal model exhibits greater than 90% accuracy across the frequency range of 1–110 GHz. In particular, in the high‐frequency band (above 50 GHz), the proposed model exhibits an improvement in accuracy of 7.4% after considering the emitter–collector capacitance and current crowding effects. This method can contribute to accurate modeling of the noise and large‐signal performance of InP HBT.

Investigation of cryogenic current–voltage anomalies in SiGe HBTs: Role of base–emitter junction inhomogeneities

The deviations of cryogenic collector current–voltage characteristics of SiGe heterojunction bipolar transistors (HBTs) from ideal drift-diffusion theory have been a topic of investigation for many years. Recent work indicates that direct tunneling across the base contributes to the non-ideal current in highly scaled devices. However, cryogenic discrepancies have been observed even in older-generation devices for which direct tunneling is negligible, suggesting that another mechanism may also contribute. Although similar non-ideal current–voltage characteristics have been observed in Schottky junctions and were attributed to a spatially inhomogeneous junction potential, this explanation has not been considered for SiGe HBTs. Here, we experimentally investigate this hypothesis by characterizing the collector current ideality factor and built-in potential of a SiGe HBT vs temperature using a cryogenic probe station. The temperature dependence of the ideality factor and the relation between the built-in potential as measured by capacitance–voltage and current–voltage characteristics are in good qualitative agreement with the predictions of a theory of electrical transport across a spatially inhomogeneous junction. These observations suggest that inhomogeneities in the base–emitter junction potential may contribute to the cryogenic non-idealities. This work helps to identify the physical mechanisms limiting the cryogenic microwave noise performance of SiGe HBTs.

Challenges for Sige Bicmos in Advanced-Node SOI

D-band (110-170GHz) spectrum is gaining attention for various applications, including 6G mm-Wave, sub-THz sensing, and radar. These systems require lattice spacing for antenna elements at sub-1mm and a very low loss signal path from antenna to integrated chip. A highly efficient front-end in a very small form factor will be required for these systems. This drives the requirement for a monolithically integrated high-gain, high-efficiency front-end that also leverages the benefits of a high-speed / high-density digital CMOS. Silicon germanium (SiGe) heterojunction bipolar transistors (HBT) integrated along with a high-density CMOS provide such an all-silicon monolithic solution.The US government is fostering the expansion of “unique and differentiated domestic manufacturing” with funding through DARPA’s Technologies for Mixed-mode Ultra Scaled Integrated Circuits (T-MUSIC) [1] program to enable disruptive RF mixed-mode technologies by developing high performance RF analog integrated with advanced digital CMOS. Through the T-MUSIC program, DARPA seeks to: 1) advance RF and mixed-mode devices to support ultra-wideband RF frontends from HF to 100 GHz; 2) integrate those devices with high density digital CMOS electronics at the wafer scale to enable embedded digital intelligence; 3) develop and explore ultra-high resolution broadband mixed-mode circuit building blocks for DoD-relevant applications; 4) explore innovative device topologies and materials to form THz devices in an advanced digital CMOS fabrication platform; and 5) establish a domestic ecosystem that facilitates enduring DoD access to differentiated capabilities for high performance RF mixed-mode SoCs.Under T-MUSIC, GlobalFoundries is demonstrating BiCMOS on 45nm PDSOI, which is the focus of this paper, and 22nm FDSOI CMOS with goals of increasing HBT performance of fT/fMAX from 350/500 GHz to 400/600 GHz and 600/700 GHz. HBTs with fT/fMAX of 380/550GHz GHz have been demonstrated building upon previously published results [2]. This paper will touch on some of the challenges that were encountered in achieving that result and discuss those anticipated in future work.Achieving these results required scaling transistor dimensions. Vertical scaling of the emitter, base and collector layers, with higher doping concentrations, reduces transit time but results in higher current densities and higher electric fields. Lateral scaling of the transistor structure reduces parasitic capacitance and resistance but concentrate the power dissipation in a smaller area. The thermal conductivity of silicon is 148W/m-K whereas that of silicon dioxide is ~1.4W/m-K. Even a thin layer of oxide will significantly increase the self-heating of the HBT. Therefore, we replace the SOI with coplanar epitaxy in regions where the HBTs are formed.The vertical scaling of the HBT requires limiting the thermal cycles that the HBT will experience during processing and suggests forming the HBT as late as possible in the CMOS process. However, the thermal cycles associate with the epitaxy and film depositions to form the HBT impact the CMOS transistors which suggests forming the HBT early in the process. We found a point in the process that offers the best compromise minimizing the impact to the doped-channel PDSOI CMOS while achieving the HBT performance goals. Work is just beginning on integration tradeoffs for FDSOI with metal gate and high-K dielectrics.Advanced-node CMOS processes can form components having smaller dimensions which offers advantages for lateral scaling but also presents challenges for forming the HBT. The contact height in 45nm is significantly less than the height of the HBT structure used in GF’s 9HP process. We changed the formation of the emitter and base so that the emitter and base contacts are almost coplanar in contrast to 9HP where the emitter was almost twice the height of the base. This problem is being further exasperated as we migrate to 22nm.The shrinking of BEOL wiring dimensions, along with the ability of the HBT to drive high currents, presents challenges in designing within limits imposed by electromigration. The use of wider wires is constrained by metal density rules. The use of stacked metal levels and redundant vias impact the parasitic capacitances and resistances of the interconnects.The paper and presentation will review these, and other challenges encountered in achieving BiCMOS integration of SiGe HBTs with fT/fMAX of 380/550GHz GHz [see figure] on a 45nm PDSOI CMOS and touch future work.This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA) and is Approved for Public Release, Distribution Unlimited. The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.[1] https://www.darpa.mil/attachments/T-MUSIC_Proposers%20Day_Presentations_Combined.pdf [2] J. Pekarik et al., 2021 IEEE BCICTS, 2021, pp. 1-4, Figure 1

Microscopic Simulation of the RF Performance of SiGe HBTs With Additional Uniaxial Mechanical Stress

A very detailed investigation of high-speed silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) showed an underestimation of the measured peak cutoff frequency by simulations with a hydrodynamic (HD) model. It was speculated that this might be due to a breakdown of the HD approximation or unknown additional mechanical stress. We repeated those simulations with the more fundamental Boltzmann transport equation (BTE) based on the same device model (doping profiles, 2-D geometry, parasitics, and so on) and obtained almost similar results showing that this failure was not due to a breakdown of the HD approximation. Since additional uniaxial stress along the direction of the lateral base has been shown to increase the cutoff frequency, we investigated this effect. We found by 2-D device simulations that the increase in the peak cutoff frequency is rather small, and at high stress levels, it even decreases, if the uniaxial stress is applied homogenously. This is due to the reduction of the conductivity of the highly doped collector layer by the stress. If the stress is limited to the intrinsic transistor, the increase in the cutoff frequency is monotonic with growing stress. On the other hand, the collector current for a given base–emitter voltage also increases with stress leading to an overestimation of the collector current compared with the measurements. If this increase is corrected by a slight decrease in the germanium profile, the gain in the peak cutoff frequency is lost. Thus, the underestimation of the peak cutoff frequency cannot be explained by an additional homogeneous uniaxial stress in the intrinsic transistor.

A Compact Macromodeling Method for Characterizing Large-signal DC and AC Performance of InP and GaAs HBTs

In this paper, a compact macromodeling method for characterizing the large-signal characteristics of heterojunction bipolar transistors (HBTs) is proposed and successfully applied to describe the DC and AC performance of InP and GaAs HBT devices. Using the Symbolically-defined Device (SDD) technology, an empirical macro circuit preserving the Spice Gummel-Poon (SGP) intrinsic network and a simplified thermal network is established. The empirical current and charge functions are embedded in the SDD macro circuit network module. Compared with other large-signal models, the proposed model description and the relevant parameter extraction are relatively simpler, and at the same time, this method can maintain high fitting accuracy. To assess the validity and the accuracy of the proposed model, the compact large-signal model is constructed for 1 ㎛ InP HBT and 1 ㎛ GaAs HBT. Based on the complete extraction of the model parameters, excellent consistency is obtained between the measured and modeled results.

Investigation of f T-Doubler Technique to Improve RF Performance of Inverse-Mode SiGe HBTs

This letter presents the application of the f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -doubler technique, for the first time, to improve the unitygain frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of inverse-mode (TM) silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs). An f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -doubler structure, which used three identical SiGe HBTs with the same emitter area of 0.07 (width) × 0.9 (length) μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , is implemented in a commercial 0.13-μm SiGe-BiCMOS technology platform. A peak f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 77 GHz is extrapolated for the TM f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> doubler, whereas a peak f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of a single TM SiGe HBT is found to be 53 GHz, exhibiting an increase of about 46% in f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> from the f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -doubler technique. The maximum oscillation frequency of the TM f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> doubler using Mason's unilateral gain is about 158 GHz. Tn addition, small-signal model parameters of the TM f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> doubler are presented, which show the TM f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -doubler structures can be treated as a single transistor element for highfrequency circuit design.

Design and Simulation of Improved SOI SiGe Hetero-Junction Bipolar Transistor Architecture with Strain Engineering

In order to improve the electrical and frequency characteristics of SiGe heterojunction bipolar transistors (HBTs), a novel structure of SOI SiGe heterojunction bipolar transistor is designed in this work. Compared with traditional SOI SiGe HBT, the proposed device structure has smaller window widths of emitter and collector areas. Under the act of additional uniaxial stress induced by Si0.85Ge0.15, all the collector region, base region and emitter region are strained, which is beneficial to improve the performance of SiGe HBTs. Employing the SILVACOⓇ TCAD tools, the numerical simulation results show that the maximum current gain βmax, the Earley voltage VA are achieved for 1062 and 186 V, respectively, the product of β and VA, i.e., β ×VA, is 1.975 × 105 V and, the peak cutoff frequency fT is 419 GHz when the Ge component in the base has configured to be a trapezoidal distribution. The proposed SOI SiGe HBT architecture has a 52.9% improvement in cutoff frequency fT compared to the conventional SOI SiGe HBTs.

(Invited) High-Performance GaN Hbts with Regrown Emitters

GaN-based hetero-junction bipolar transistors (HBTs) are suitable for power amplifiers because they have inherent advantages such as high current and power density, high linearity and normally off operation. However, low conductivity in the p-type base layer and plasma-induced dry-etching damage slow down the improvement of GaN HBTs. Although GaN-based HBTs demonstrated large current gain (β) and high current and power density by using p-type InGaN base [1], N2-incorporation dry-etching process, wet repairing and regrown base contact layer [2,3], etching damage also exists, which limits the maximum oscillation frequency (fmax) [4]. This essay reports an AlGaN/GaN heterojunction bipolar transistor (HBT) on sapphire with selective-area regrown (SAG) n-AlGaN emitter by metal-organic chemical vapor deposition (MOCVD). 1-μm n+-GaN, 0.5-μm undoped-GaN and 100-nm p-GaN are grown on sapphire in sequence by MOCVD. Then a 100-nm thick SiO2 mask layer is deposited on the wafer and patterned for SAG emitter. Then the wafer is reloaded to reactor to grow an n-AlGaN emitter layer at 980 ℃ and 50 torr. Hall measurements performed on p-GaN base layer indicate a hole concentration of 9.8×1017 /cm3 and mobility of 14.1 cm2/V.s. The SAG n-AlGaN emitter is 100-nm thick with the Al component of 7%. The electron concentration and mobility of the SAG n-AlGaN layer are 1.6×1018 /cm3 and 290 cm2/V s. Ohmic contact is achieved on the base contact with the calculated sheet resistance Rs of 238 KΩ/sq, and the specific contact resistance ρc of 2×10-3 Ω.cm2. As a result, the fabricated HBTs exhibit high β of 110, which is highest among reported values on GaN-based HBTs on sapphire substrates. The common-emitter I-V characteristics show a high J C of 22 kA/cm2 and power density of 220 kW/cm2 with a low Voffset <1V and Vknee<5V. These voltage are the lowest among reported values on GaN-based HBTs with comparable emitter areas, owing to the realization of base ohmic contact that decreases base resistance. The open-base breakdown voltage is 98 V with the leakage current of 1 μA, as a consequence the breakdown field is about 2.2 MV/cm. we also demonstrated RF performance of GaN HBTs with fT of 4 GHz at the collector voltage of 9 V, although the chip size is large. It is expected that high RF performance can be achieved by down scaling the device layout. These results for GaN HBTs/sapphire show that high performance III-N HBTs can be achieved with regrowth technology. In this talk, we will demonstrate that a large performance improvement can be obtained for RF HBT devices by the use of regrowth emitter. The current gain is increased with the emitter area decreasing. It is favorable for RF HBT devices, which are expected to achieve higher current gain, benefiting from small recombination current. By down scaling the device layout, an RF HBT is expected to be used in PA in the next generation communication.

Cryogenic Characterization of RF Low-Noise Amplifiers Utilizing Inverse-Mode SiGe HBTs for Extreme Environment Applications

The cryogenic performance of radiation-hardened radio-frequency (RF) low-noise amplifiers (LNAs) is presented. The LNA, which was originally proposed for the mitigation of single-event transients (SETs) in a radiation environment, uses inverse-mode silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) in its core cascode stages. In this prototype, the upper common-base SiGe HBT is configured in inverse mode for balanced RF performance and reduced SET sensitivity. In order to better exploit the inverse-mode LNAs in a variety of extreme-environment applications, the RF performance of the LNA was characterized using liquid nitrogen to evaluate cryogenic operation down to 78 K. While the SiGe LNA exhibits acceptable RF performance for all temperature conditions, there is a noticeable gain drop observed at 78 K compared to the conventional forward-mode design. This is attributed to the limited high-frequency performance of an inverse-mode SiGe HBT. As a guideline, compensation techniques, including layout modifications and profile optimization, are discussed for the mitigation of the observed gain degradation.

Impact of finger numbers on the performance of proton-radiated SiGe power HBTs at room and cryogenic temperatures

Multi-finger silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) are attractive to the radiation-intense environment. This paper investigates the performance of proton-radiated SiGe power HBTs with different finger numbers (8, 24, 40, and 80 emitter fingers) at room and cryogenic temperatures. Different proton radiation fluences (1 × 1012 p/cm2, 2 × 1013 p/cm2, and 5 × 1013 p/cm2) and ambient temperatures (300 K and 77 K) were used to study the irradiation performance of the HBTs. Results show that the number of emitter fingers has a significant impact on the performance of the SiGe power HBTs for different temperatures and irradiation conditions. Underlying mechanisms have been discussed. This study provides guidelines on designing and using SiGe power HBTs for integrated circuits in radiation environments at room and cryogenic temperatures.

(Invited) Development of III-Nitride Bipolar Transistor Switches and Rectifiers

The successful development of III-V nitride materials systems have led to active research of electronic devices in the past decades. III-nitride (III-N)-based devices have a bandgap engineering flexibility, large energy gap, direct band structure, and high carrier mobility when compared to Si- and SiC -based devices, providing new performance improvement opportunities for high-speed and energy-efficient electronics. In particular, tremendous efforts have been devoted to the quest for heterojunction field effect transistors (HFETs). Today, commercial GaN HFETs are available for microwave power amplifiers and power electronic circuits. On the other hand, bipolar transistors are also essential devices in order to fully exploit the potential of III-N materials systems and the associated semiconductor technologies. For instance, insulated-gate-bipolar transistors would require integrated bipolar transistor and unipolar transistor structures to optimally operate such devices in a vertical current conduction form. The development of III-N bipolar switches in either two-terminal or three-terminal forms have therefore been actively sought. Unfortunately, myriad technological challenges in the growth and the fabrication processing have limited the progress of III-N bipolar transistors for years. These particular device technologies are still in the early stage of the technology development. In this presentation, we will review the development status of III-N bipolar transistor switches and vertical GaN rectifiers. Early development of heterojunction bipolar transistors (HBTs) using AlGaN/GaN heterojunctions was unsuccessful because of the limited current drive and current gain. The GaN/InGaN HBTs, on the other hand, showed promising device performance. We studied optimized epitaxial growth in a metalorganic chemical vapor deposition (MOCVD) reactor, developed a direct-growth (or non-regrowth) mesa-type III-N HBT fabrication processing technology, and achieved state-of-the-art of GaN/InGaN NPN HBT performance.[1],[2],[3],[4] These devices exhibited high-current gain of >100, high current drive density of >100 kA/cm2, and high d.c. power handling capability of > 3 MW/cm2. Small-signal microwave amplification with a cut-off frequency (f T) of 8GHz was also demonstrated experimentally. Similarly, GaN-based rectifiers have been studied in recent years and these devices have reportedly demonstrated switching performance approaching theoretical values. At Georgia Tech, our preliminary study demonstrated that 800-V homojunction GaN PIN rectifiers can achieve a specific on-state resistance of R ON = 2.8 mOhm-cm2. [5]The large turn-on voltage of GaN PIN diodes, however, could be problematic in circuit applications. To address this problem, GaN junction-barrier Schottky (JBS) rectifiers are also under study. Using a nickel as the Schottky contact material and an additional MOCVD regrowth step, our preliminary results demonstrated a GaN JBS diode with a turn-on voltage of ~0.8V, a value similar to typical silicon PN diodes. These results demonstrated the feasibility of using bipolar carrier transport mechanisms and PN junctions in III-N devices for power amplifications and switching circuits. Further device design and processing techniques that help achieve these performance characteristics will be discussed in the conference. [1] Z. Lochner, et. al. , Appl. Phys. Lett. 99 (19), 193501-1–3 (2011). [2] Y. Zhang, et. al. Phys. Stat. Sol. (c) 8 (7–8), 2451–2453 (2011). [3] S. Shen et. al., IEEE Electron Device Lett., 32 (8), 1065–1067 (2011). [4] Y. Lee, et. al. , Physica Status Solidi(a), 209(3), 497-500 (2012). [5] T. Kao, et. al., IEEE Trans. Electron Devices, 62(8) 2679-2683 (2015).

The Use of Inverse-Mode SiGe HBTs as Active Gain Stages in Low-Noise Amplifiers for the Mitigation of Single-Event Transients

A cascode configuration with inverse-mode (IM) common-emitter silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) is proposed for the mitigation of single-event transients (SETs) in low-noise amplifiers (LNAs). Conventionally, despite their SET-mitigation capability, IM SiGe HBTs have been considered to be unsuitable for active gain stages due to severe degradation in RF performance. However, with the benefits of aggressive technology scaling, the high frequency performance of IM SiGe HBTs has been significantly improved, thereby enabling them to be utilized in active gain stages with acceptable RF performance. The cascode with IM common-emitter and common-base SiGe HBTs is used for a 2.4 GHz prototype LNA and it achieves adequate RF gain (10 dB) and noise figure (1.9 dB). With regard to SET mitigation, a through-wafer two-photon absorption pulsed-laser experiment is conducted to test the efficacy of this radiation-hardening approach in an advanced 90 nm SiGe BiCMOS platform. The proposed IM-SiGe-HBT-based LNA exhibits 85% reduction in transient peaks compared to the conventional forward-mode cascode LNA.

A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT**Project supported by the National Natural Science Foundation of China (Grant Nos. 61574010, 60776051, 61006059, and 61006044), the Beijing Municipal Natural Science Foundation, China (Grant No. 4142007), and the Beijing Municipal Education Committee, China (Grant No. KM200910005001).

The product of the cutoff frequency and breakdown voltage (fT×BVCEO) is an important figure of merit (FOM) to characterize overall performance of heterojunction bipolar transistor (HBT). In this paper, an approach to introducing a thin N+-buried layer into N collector region in silicon-on-insulator (SOI) SiGe HBT to simultaneously improve the FOM of fT×BVCEO and thermal stability is presented by using two-dimensional (2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness (TBOX) on fT, BVCEO, and the FOM of fT×BVCEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fT, slightly increases BVCEO to some extent, but ultimately degrades the FOM of fT×BVCEO. Although the fT, BVCEO, and the FOM of fT×BVCEO can be improved by increasing SOI insulator SiO2 layer thickness TBOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiO2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N+-buried layer is introduced into collector region to not only improve the FOM of fT×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N+-buried layer in collector region is investigated in detail. The result show that the FOM of fT×BVCEO is improved and the device temperature decreases as the N+-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N+-buried layer into collector region provides an effective method to improve SOI SiGe HBT overall performance.

Design and On-Wafer Characterization of $G$ -Band SiGe HBT Low-Noise Amplifiers

This paper presents the design and thorough on-wafer characterization of two G-band low-noise amplifiers (LNAs) implemented using 0.13- $\mu \text{m}$ silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) with peak $f_{T}/f_{\max }$ of 300/500 GHz. The impact of the substrate network and optimized via interconnections on the SiGe HBT performance is investigated to ensure that maximum performance is extracted from each SiGe HBT. The two LNAs are separately implemented using only cascode pairs and only common-emitter (CE) SiGe HBTs to determine which configuration yields better performance in a multistage G-band LNA. The cascode LNA achieves a peak gain of 24.0 dB at 158 GHz with a mean noise figure (NF) of 8.2 dB from 145 to 165 GHz, while the CE LNA achieves a 17.2 dB of gain at 183 GHz with a mean NF of 8.0 dB across 165–200 GHz. A novel implementation of blackbody noise sources for on-wafer Y-factor NF measurements reduces the waveguide length needed to transition between the antenna and the probe, which significantly reduces the sensitivity to jitter. To the authors’ knowledge, these LNAs achieve the lowest reported NF of all SiGe LNAs at these frequencies to date, and the results demonstrate that SiGe HBTs are viable options for millimeter-wave performance-constrained applications.

Influence of temperature on transit times and microwave noise performances of SiGe HBT

The influence of temperature (300 K and 40 K) on intrinsic transit times and microwave noise performances of silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) is investigated. At 300 K, we compared measured and modelled S-parameters and four noise parameters, and we found a good agreement. At 40 K, we compared measured and modelled S-parameters, and we deduced noise performances from the S-parameter measurements. The electric model includes correlated junction noise sources and a proper extraction of the transit times involved in these sources. Moreover, the microwave noise model considers all the physical phenomena that impact noise performances in SiGe HBTs. We analysed three devices having different Ge content (10%–20%, 10%–25% and 10%–30%). At 40 K, the device with 10%–25% reaches one of the lowest base transit times (τB), the lowest minimum noise figure (NFmin), and the lowest equivalent noise resistance (Rn), for operation frequencies up to the maximum device dynamic performances (f ≈ fT) These results demonstrate the excellent potential to develop cryogenic applications of SiGe HBTs.

Lateral solid phase epitaxy of amorphously grown Si1 − xGex layers on SiO2/Si(100) substrates using in-situ RPCVD postannealing

Lateral solid phase epitaxy (L-SPE) in non-doped or in-situ B-doped amorphous- (a-) SiGe deposited on SiO2 patterned Si(100) wafers by in-situ postannealing in reduced pressure chemical vapor deposition system was investigated for possible heterojunction bipolar transistor (HBT) base link resistivity improvement. Using Si2H6 as Si precursor gas, an epitaxial and amorphous layer was grown on the mask window and on the SiO2 area, respectively. By inserting a-Si buffer underneath, the deposited a-SiGe surface became smoother. After the L-SPE process, an improved L-SPE length was observed due to suppressed random nucleation on SiO2. The L-SPE length increased with increasing postannealing time and saturated due to random poly-grain formation on the SiO2. At the same L-SPE time, increased L-SPE length was observed at higher temperature and at higher Ge concentration. With increasing B concentration in the a-SiGe, the L-SPE length firstly increased. However, after reaching 2×1019atom/cm3, the L-SPE length reduced again down to the undoped case. These results of L-SPE process might have potential to improve dynamic performance of SiGe HBT by reducing the base link resistivity by widening the monocrystalline region around bipolar window.

Static Performance of SiGe HBTs at Low Temperature

—This paper analyse is the impact of cryogenic temperatures for SiGe Heterojunction Bipolar Transistors (HBTs) base, realised in BiCMOS9 0.13μm industrial process. The use of these components in microwaves applications exposed to various temperatures is fundamental aspect to predict in precise way its electric characteristics. This paper investigates the temperature dependence from (170 K to 300 K) of DC, for NPN SiGe heterojunction bipolar transistors (HBTs) and notably modeling high performance Si/SiGe HBT for telecommunication and radar detection (&gt;0.5THz) in low temperature (cryogenic temperature).

(Invited) Towards 0.7 Terahertz Silicon Germanium Heterojunction Bipolar Technology – The DOTSEVEN Project

DOTSEVEN is a very ambitious European R&D project targeting the development of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) technologies with cut-off frequencies (fmax) of around 700 GHz. The project started in October 2012 and will end in March 2016. It is the continuation of the predecessor project DOTFIVE which succeeded to push fmax of SiGe HBTs into the 500 GHz region for the first time. Besides enhancing the speed performance of the SiGe HBT drastically, the challenging task of its integration into a 130 nm BiCMOS process will be addressed too. The capabilities and benefits of the technology will be demonstrated by benchmark circuits and advanced system applications in the 0.1 to 1 THz range like THz imaging and sensing, wireless Gb/s communications and millimeter-wave radar. Process development and circuit design will be assisted by improved TCAD and physics-based device simulation and accurate compact device modeling.

An Investigation on the Optimization and Scaling of Complementary SiGe HBTs

We use predictive technology computer-aided design to investigate the device design challenges and optimization issues that will be necessarily encountered in scaling of complementary silicon-germanium (C-SiGe) heterojunction bipolar transistors (HBTs). A fully integrated simulation framework was developed to design and optimize device doping and Ge profiles for any given target performance, using important circuit-relevant figures-of-merit. This methodology was successfully utilized to realize device profiles for multiple C-SiGe technology nodes within the context of a C-SiGe scaling roadmap. A method for optimizing the ac performance of SiGe HBTs geared for both high-performance and low-power applications is also presented. The performance metrics of the optimized profiles presented here are then compared with those of existing fabricated devices reported in the literature.