Heterogeneous System-on-chip Research Articles

Fast, closed-loop iterative system-on-chip of deflection efficiency enhancement for a liquid crystal optical phased array.

To implement a liquid crystal optical phased array (LC-OPA) on a practical free-space laser communication terminal, there are two essential parameters: insertion loss and the closed-loop bandwidth required to meet the dynamic linking condition of the acquisition-tracking-pointing sub-system. Real-time hardware platforms and deflection efficiency optimization algorithms have been suggested since the invention of LC-OPA. In this paper, the so-called ZYNQ platform, a field-programmable-gate-array-based heterogeneous system-on-chip (SoC), is utilized to keep real-time response and accelerate data generation, such as beam steering, beamforming, beam enhancement, etc. In addition, a novel, to the best of our knowledge, optimization algorithm is proposed on the concept of dimension reduction of the number of objective variables. After deploying on this heterogeneous SoC platform, numerical simulations and experimental results both verify that, compared to the conventional PC-based system, the integrated SoC platform offers 15.8 times faster iterative speed, a rapid convergence rate, and excellent robustness, yet with less usage of power, physical size, and monetary cost. The efficiency enhancement process costs only a few seconds at any angle, laying the foundation for practical in-line applications.

Accelerator Integration for Open-Source SoC Design

The open-source hardware community contributes a variety of processors and accelerators, but combining them effectively into a complete System-on-Chip (SoC) remains a difficult task. We present a design flow for the seamless hardware and software integration of accelerators into a complete SoC and for its evaluation through rapid FPGA-based prototyping. By leveraging ESP, our open-source platform for agile heterogeneous SoC design, we demonstrate FPGA prototypes of various SoC designs, featuring the NVIDIA Deep Learning Accelerator and the Ariane RISC-V 64-bit processor core.

DeepSoCS: A Neural Scheduler for Heterogeneous System-on-Chip (SoC) Resource Scheduling

In this paper, we present a novel scheduling solution for a class of System-on-Chip (SoC) systems where heterogeneous chip resources (DSP, FPGA, GPU, etc.) must be efficiently scheduled for continuously arriving hierarchical jobs with their tasks represented by a directed acyclic graph. Traditionally, heuristic algorithms have been widely used for many resource scheduling domains, and Heterogeneous Earliest Finish Time (HEFT) has been a dominating state-of-the-art technique across a broad range of heterogeneous resource scheduling domains over many years. Despite their long-standing popularity, HEFT-like algorithms are known to be vulnerable to a small amount of noise added to the environment. Our Deep Reinforcement Learning (DRL)-based SoC Scheduler (DeepSoCS), capable of learning the “best” task ordering under dynamic environment changes, overcomes the brittleness of rule-based schedulers such as HEFT with significantly higher performance across different types of jobs. We describe a DeepSoCS design process using a real-time heterogeneous SoC scheduling emulator, discuss major challenges, and present two novel neural network design features that lead to outperforming HEFT: (i) hierarchical job- and task-graph embedding; and (ii) efficient use of real-time task information in the state space. Furthermore, we introduce effective techniques to address two fundamental challenges present in our environment: delayed consequences and joint actions. Through an extensive simulation study, we show that our DeepSoCS exhibits the significantly higher performance of job execution time than that of HEFT with a higher level of robustness under realistic noise conditions. We conclude with a discussion of the potential improvements for our DeepSoCS neural scheduler.

Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-D SoCs

Three-dimensional integration, employing through-silicon vias (TSVs), improves the system-on-chip (SoC) performance. However, redundancy schemes are required to cope with the relatively poor TSV manufacturing yield. Existing redundancy schemes do not exploit technological heterogeneity between the dies. Hardware costs can differ for the individual dies. This demands asymmetrical schemes with low complexity in costly mixed signal or RF dies. Furthermore, redundant TSVs are only used in the case of a defect. In the most probable case of correct manufacturing, they are unused. Another emerging technique using redundant lines is low-power coding (LPC). This paper presents a hybrid TSV redundancy technique based on coding, which can be used for LPC and for yield enhancement. Furthermore, the approach is strongly asymmetric. In case of a fault, a configuration is only required for the encoder or decoder located in the cheaper die, while in the costly die, a minimal set of XOR gates is sufficient. A case study for an existing heterogeneous SoC shows that the proposed technique decreases area overhead and power consumption compared to the best previous technique by over 69 % and 33%, respectively.

A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications

This paper proposes a reconfigurable system on chip (SoC) for smart power applications. The system is composed of an ultra-low-power microcontroller for standard software programmability, coupled to an embedded-FPGA (eFPGA) to perform control-driven applications and lightweight digital signal processing, at lower power consumption and higher responsiveness than with processor-based execution. To the best of our knowledge, this is the first heterogeneous reconfigurable SoC targeting smart power applications. The SoC targets BCD technologies integrating bipolar, CMOS, and DMOS devices, typically featuring a small number of metal layers when compared with the traditional CMOS technologies. The added value of the proposed system is that the digital system is fully synthesizable since the eFPGA is based on a soft-core approach. This paper presents the results of integrating an eFPGA with a computational capability of $\simeq 1\text{k}$ equivalent gates in STMicroelectronics 90-nm BCD technology featuring five metal layers and high- $k$ transistors. We benchmarked our architecture on a wide range of applications relevant to the smart power domain. eFPGA integration in SoCs introduces a 20%–27% area overhead but has a straightforward benefit in terms of energy consumption, which proves reduction from about $10\times $ to $800\times $ . In terms of latency, the eFPGA implementation allows a gain from $8\times $ to $145\times $ comparing the pure cycles count.

MICROPROCESSOR FOR INTELLIGENT SPACE SURVEILLANCE SYSTEMS WITH SPACEWIRE/GIGASPACEWIRE/SPACEFIBRE LINKS

The article presents architecture and main features of 90 nm CMOS radiation tolerant MCDE50F ASIC as multiprocessor heterogeneous SoC (System-on-Chip) which contains MIPS64 RISC core, graphic processing unit (GPU) and application-specific computer vision Elcore50 DSP. High-speed data input/output is performed by multiprotocol SpaceFibre/GigaSpaceWire/ SpaceWire ports combined with built-in multichannel SpaceFibre/GigaSpaceWire/SpaceWire based switch. MCDE50F ASIC is intended for space “intelligent” surveillance system applications, which require high computational performance in signal and image processing, including computer vision functions support, and high-speed deliverance of massive data arrays. An example of onboard data processing system structure based on MCDE50F ASIC is presented. Performance characteristics of MCDE50F ASIC implementing OpenVX standard functions are also given.

Optical character recognition on heterogeneous SoC for HD automatic number plate recognition system

Automatic number plate recognition (ANPR) systems are becoming vital for safety and security purposes. Typical ANPR systems are based on three stages: number plate localization (NPL), character segmentation (CS), and optical character recognition (OCR). Recently, high definition (HD) cameras have been used to improve their recognition rates. In this paper, four algorithms are proposed for the OCR stage of a real-time HD ANPR system. The proposed algorithms are based on feature extraction (vector crossing, zoning, combined zoning, and vector crossing) and template matching techniques. All proposed algorithms have been implemented using MATLAB as a proof of concept and the best one has been selected for hardware implementation using a heterogeneous system on chip (SoC) platform. The selected platform is the Xilinx Zynq-7000 All Programmable SoC, which consists of an ARM processor and programmable logic. Obtained hardware implementation results have shown that the proposed system can recognize one character in 0.63 ms, with an accuracy of 99.5% while utilizing around 6% of the programmable logic resources. In addition, the use of the heterogenous SoC consumes 36 W which is equivalent to saving around 80% of the energy consumed by the PC used in this work, whereas it is smaller in size by 95%.

HD number plate localization and character segmentation on the Zynq heterogeneous SoC

Automatic number plate recognition (ANPR) systems have become widely used in safety, security, and commercial aspects. A typical ANPR system consists of three main stages: number plate localization (NPL), character segmentation (CS), and optical character recognition (OCR). In recent years, to provide a better recognition rate, high-definition (HD) cameras have started to be used. However, most known techniques for standard definition (SD) are not suitable for real-time HD image processing due to the computationally intensive cost of processing several-folds more of image pixels, particularly in the NPL stage. In this paper, algorithms suitable for hardware implementation for NPL and CS stages of an HD ANPR system are presented. Software implementation of the algorithms was carried on as a proof of concept, followed by hardware implementation on a heterogeneous system-on-chip (SoC) device that contains an ARM processor and a field-programmable gate array (FPGA). Heterogeneous implementation of these stages has shown that this HD NPL algorithm can localize a number plate in 16.17 ms, with a success rate of 98.0%. The CS algorithm can then segment the detected plate in 0.59 ms, with a success rate of 99.05%. Both stages utilize only 21% of the available on-chip configurable logic blocks.

PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoC

Accurate estimation of power at the system level is essential for system-on-chip (SoC) architects. The integration of heterogeneous processors like CPUs and emerging coarse-grained reconfigurable architectures (CGRAs) in SoCs significantly complicates the power-estimation process. This brief presents an accurate and efficient system-level power modeling framework, power modeling with a customized calibration, for processors on heterogeneous SoCs. Quantitative criteria are developed to classify the computing resources of heterogeneous SoCs, including instruction-driven processing architectures and CGRAs-based architectures, into two categories automatically. A novel power-modeling technique featuring a genetic algorithm and backpropagation neural network (GA-BPNN) is introduced to address CGRA-alike architectures, which cannot be properly handled by the traditional linear regression-based power calibration method. Experimental results show that the power estimation error for CGRAs using GA-BPNN is less than 5% with three orders faster speed compared with gate-level estimations. In the meanwhile, accuracy is improved on most benchmarks compared with the linear model. The average improvement in accuracy is 81% and ranges between 29% and 99%.

Programmable System-on-Chip for Silicon Prototyping

This paper presents a programmable system-on-chip (SoC) design methodology which integrates multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced by sharing a common SoC platform. In this implementation, an integrated SoC platform is comprised of eight SoC projects. When these eight SoC projects are designed separately, the total area is approximately 143.03 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , while the area of the integrated platform is about 24.43 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The area reduction is significant, so is the fabrication cost. Once the integrated platform chip is fabricated, three programming schemes are carried out to allow the integrated chip to act as the individual SoC design projects. A test chip is designed and implemented using the TSMC 0.13-μm CMOS generic logic process technology.

Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications

A heterogeneous multicore system-on-chip (SoC) has been developed for high-definition (HD) multimedia applications that require secure DRM (digital rights management). The SoC integrates three types of processors: two specific-purpose accelerators for cipher and high-resolution video decoding; one general-purpose accelerator (MX); and three CPUs. This is how our SoC achieves high performance and low power consumption with hardware customized for video processing applications that process a large amount of data. To achieve secure data control, hardware memory management and software system virtualization are adopted. The security of the system is the result of the cooperation between the hardware and software on the system. Furthermore, a highly tamper-resistant system is provided on our SiP (System in a package), through DDR2 SDRAMs and a flash memory that contain confidential information in one package. This secure multimedia processor provides a solution to protect contents and to safely deliver secure sensitive information when processing billing transactions that involve digital content delivery. The SoC was implemented in a 90 nm generic CMOS technology.

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A multicore system-on-chip (SoC) has been developed for various applications (recognition, inference, measurement, control, and security) that require high-performance processing and low power consumption. This SoC integrates three types of synthesizable processors: eight CPUs (M32R), two multi-bank matrix processors (MBMX), and a controller (M32C). These processors operate at 1 GHz, 500 MHz, and 500 MHz, respectively. These three types of processors are interconnected on this chip with a high-bandwidth multi-layer system bus. The eight CPUs are connected to a common pipelined bus using a cache coherence mechanism. Additionally, a 512-kB L2 cache memory is shared by the eight CPUs to reduce internal bus traffic. A multi-bank matrix processor with 2-read/1-write calculation and background I/O operation has been adopted. The 1-GHz CPU is realized using a delay management network which consists of delay monitors that can be applied for any kind of application or process technology. Our configurable heterogeneous architecture with nine CPUs and two matrix processors reduces power consumption by 45%. </para>

System level processor/communication co-exploration methodology for multiprocessor system-on-chip platforms

Current and future system-on-chip (SoC) designs will contain an increasing number of heterogeneous programmable units combined with a complex communication architecture to meet flexibility, performance and cost constraints. Such a heterogeneous multiprocessor SoC architecture has enormous potential for optimisation, but requires a system-level design environment and methodology to evaluate architectural alternatives. A methodology is proposed to jointly design and optimise the processor architecture together with the onchip communication based on the LISA processor design platform in combination with SystemC transaction level models. The proposed methodology advocates a successive refinement flow of the system-level models of both the processor cores and the communication architecture. This allows design decisions based on the best modelling efficiency, accuracy and simulation performance possible at the respective abstraction level. The effectiveness of our approach is demonstrated by the exemplary design of a dual-processor JPEG decoding system.