Accelerator Integration for Open-Source SoC Design

Abstract

The open-source hardware community contributes a variety of processors and accelerators, but combining them effectively into a complete System-on-Chip (SoC) remains a difficult task. We present a design flow for the seamless hardware and software integration of accelerators into a complete SoC and for its evaluation through rapid FPGA-based prototyping. By leveraging ESP, our open-source platform for agile heterogeneous SoC design, we demonstrate FPGA prototypes of various SoC designs, featuring the NVIDIA Deep Learning Accelerator and the Ariane RISC-V 64-bit processor core.