Geometry effect with respect to ESD and radiative charged particles in SoC

Abstract

Thermal grown silicon dioxide (SiO 2 ) used as gate oxide are found commonly in a SoC (system-on-chip) design for the CMOS technology of 40nm and above, which is vulnerable under ESD (electrostatic discharge) stress typically known as CDM (charged device model) events. Reliability in SoC designs towards ESD protection and RadHard (radiation hardening) against single event effects (SEE) displays a key measure and desired feature in high-end applications such as automotive and aeronautical electronic systems. Using the calculated values of linear energy transfer LET and Range of radiative Alpha particles in SiO 2 , in relation to the geometrical sizes in an SoC design, we continue analyze the potential ionizing radiation damage to transistor gate of CMOS in analogous to ESD damage described by CDM and TLP (transmission-line pulse) method. In this paper we present TLP testing structures with various rise times up to 10 ns on the thermal grown oxide from 70nm to 400nm with focus on the PMOS device, which is more likely damaged in the event of CDM stress due to its hot carrier penetrations to the gate oxide from the source area. Comparative results of Alpha particles are also presented and discussed as in a previous work using radiative particles of protons.