An automated clock distribution topology in SoC designs

Abstract

System on chip (SoC) consists of microprocessors, memories, busses, communication protocols, interfaces and other hard and soft intellectual property (IP) components where power consumption, synchronization and testability are crucial. Fast run time is one of the main key winning factors for SoC designs while clock is the most performance critical signals in SoC design flow. High reusability, correct-by-construction design and automation are the main issues to ensure consistence and sustainable rate in fast design turnaround time. In this paper, an automated H-tree clock distribution topology that enables fast turnaround time of SoC designs is presented. An automated balanced multiple clock domain H-tree can eliminate wire or repeater dominant to reduce process, voltage and temperature (PVT) impact and keep design turnaround time to minimum while maintaining approximately zero skew.