PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoC

Abstract

Accurate estimation of power at the system level is essential for system-on-chip (SoC) architects. The integration of heterogeneous processors like CPUs and emerging coarse-grained reconfigurable architectures (CGRAs) in SoCs significantly complicates the power-estimation process. This brief presents an accurate and efficient system-level power modeling framework, power modeling with a customized calibration, for processors on heterogeneous SoCs. Quantitative criteria are developed to classify the computing resources of heterogeneous SoCs, including instruction-driven processing architectures and CGRAs-based architectures, into two categories automatically. A novel power-modeling technique featuring a genetic algorithm and backpropagation neural network (GA-BPNN) is introduced to address CGRA-alike architectures, which cannot be properly handled by the traditional linear regression-based power calibration method. Experimental results show that the power estimation error for CGRAs using GA-BPNN is less than 5% with three orders faster speed compared with gate-level estimations. In the meanwhile, accuracy is improved on most benchmarks compared with the linear model. The average improvement in accuracy is 81% and ranges between 29% and 99%.