XDFOI(TM) (x-Dimensional Fan-Out Integration) is a heterogeneous integration technology platform of JCET Group, which includes multiple advanced 2D/2.5D/3D chiplet and SiP (System-in-Package) integration solutions. Since the semiconductor Si node advances beyond 14 nm, the soaring cost of design and manufacture has shifted attention to advanced heterogeneous integration strategies, such as System-on-Chip (SoC) and SiP. SoC benefits from the shorter interconnections, while SiP has the advantages on cost, sourcing, cycle time and reliability. As a key member of XDFOI(TM), FO multi-chip-module (FO-MCM) and its further integration with fcBGA, is a viable and flexible technique to meet the challenge of exponentially generated date and information of our society. Meanwhile, the size of XDFOI(TM) chips and related fcBGA packages gets larger and larger, corresponding warpage and reliability issues become more and more complicated and important. In this paper, large size 2.5D FO-MCM chips (L * W ≥ 900 mm2), which were fabricated by chip-first process as S-in-1 FO types (S=2/3/4: the quantity of Si chiplets) with different Si thickness combination, together with raw Si chip (L * W) as 1-in-1 control type, were assembled with large size fcBGA (≥ 65x65 mm2) to study the impact of Si chiplet split and Si thickness on warpage. Furthermore, reliability (TC 500/1000 cycles, uHAST 96/192 hrs, and HTSL 500/1000 hrs) of these large size XDFOI(TM) fcBGA packages were also proceeded to investigate the corresponding warpage/reliability relationship.